- f4caf69 The tLDR et al instructions were emitting either a reg/reg or reg/imm by Bill Wendling · 15 years ago
- a92bac6 Fix some invalid alignments for Neon vld-dup and vld/st-lane instructions. by Bob Wilson · 15 years ago
- 48575f6 Making use of VFP / NEON floating point multiply-accumulate / subtraction is by Evan Cheng · 15 years ago
- 6c4c982 Add support for NEON VLD3-dup instructions. by Bob Wilson · 15 years ago
- 86c6d80 Add support for NEON VLD3-dup instructions. by Bob Wilson · 15 years ago
- b1dfa7a Add support for NEON VLD2-dup instructions. by Bob Wilson · 15 years ago
- ff96b63 Fix a cut-n-paste-error. by Evan Cheng · 15 years ago
- 6b19491 Avoid isel movcc of large immediates when the large immediate is available in a register. These immediates aren't free. by Evan Cheng · 15 years ago
- 63f3544 Add conditional move of large immediate. by Evan Cheng · 15 years ago
- e5e0ef1 Fix an obvious typo which inverted an immediate. by Evan Cheng · 15 years ago
- 875a6ac Add conditional mvn instructions. by Evan Cheng · 15 years ago
- cdfad36 Simplify uses of MVT and EVT. An MVT can be compared directly by Duncan Sands · 15 years ago
- e691360 Break ARM addrmode4 (load/store multiple base address) into its constituent by Jim Grosbach · 15 years ago
- 665814b Add support for alignment operands on VLD1-lane instructions. by Bob Wilson · 15 years ago
- f40deed Shifter ops are not always free. Do not fold them (especially to form by Evan Cheng · 15 years ago
- 3e55612 First part of refactoring ARM addrmode2 (load/store) instructions to be more by Jim Grosbach · 15 years ago
- 3ab5658 trailing whitespace by Jim Grosbach · 15 years ago
- 3454ed9 Support alignment for NEON vld-lane and vst-lane instructions. by Bob Wilson · 15 years ago
- a425716 Allow use of the 16-bit literal move instruction in CMOVs for Thumb2 mode. by Jim Grosbach · 15 years ago
- 3bbdcea Allow use of the 16-bit literal move instruction in CMOVs for ARM mode. by Jim Grosbach · 15 years ago
- 8289162 Add specializations of addrmode2 that allow differentiating those forms by Jim Grosbach · 15 years ago
- be91232 Add braces for legibility. by Jim Grosbach · 15 years ago
- 2a6e616 Set alignment operand for NEON VST instructions. by Bob Wilson · 15 years ago
- 40ff01a Set alignment operand for NEON VLD instructions. by Bob Wilson · 15 years ago
- 52a261b fix a long standing wart: all the ComplexPattern's were being by Chris Lattner · 15 years ago
- 23da0b2 Fix QOpcode assignment to Opc. by Eric Christopher · 15 years ago
- bd916c5 Convert some VTBL and VTBX instructions to use pseudo instructions prior to by Bob Wilson · 15 years ago
- 8466fa1 Switch all the NEON vld-lane and vst-lane instructions over to the new by Bob Wilson · 15 years ago
- 979b061 remove some dead code. t2addrmode_imm8s4 is never used in a by Chris Lattner · 15 years ago
- f572191 Finish converting the rest of the NEON VLD instructions to use pseudo- by Bob Wilson · 15 years ago
- ffde080 Convert VLD1 and VLD2 instructions to use pseudo-instructions until by Bob Wilson · 15 years ago
- 5bcb8a6 temporarily revert r112664, it is causing a decoding conflict, and by Chris Lattner · 15 years ago
- 43a6c5e We have a chance for an optimization. Consider this code: by Bill Wendling · 15 years ago
- e5ce4f6 Use pseudo instructions for VST1 and VST2. by Bob Wilson · 15 years ago
- fd7fd94 We don't need to custom-select VLDMQ and VSTMQ anymore. by Bob Wilson · 15 years ago
- d4bfd54 Change ARM VFP VLDM/VSTM instructions to use addressing mode #4, just like by Bob Wilson · 15 years ago
- 01ba461 Use pseudo instructions for VST3. by Bob Wilson · 15 years ago
- 70e48b2 Use pseudo instructions for VST1d64Q. by Bob Wilson · 15 years ago
- 709d592 Start converting NEON load/stores to use pseudo instructions, beginning here by Bob Wilson · 15 years ago
- 00d3dda Don't call tablegen'ed Predicate_* functions in the ARM target. by Jakob Stoklund Olesen · 15 years ago
- a2c519b Add -disable-shifter-op to disable isel of shifter ops. On Cortex-a9 the shifts cost extra instructions so it might be better to emit them separately to take advantage of dual-issues. by Evan Cheng · 15 years ago
- 78dfbc3 Also use REG_SEQUENCE for VTBX instructions. by Bob Wilson · 15 years ago
- d491d6e Use REG_SEQUENCE nodes to make the table registers for VTBL instructions be by Bob Wilson · 15 years ago
- 978189e Remove an unused and a pointless variable. by Duncan Sands · 15 years ago
- e368b46 Eliminate unnecessary uses of getZExtValue(). by Dan Gohman · 15 years ago
- 07f6e80 Remove the hidden "neon-reg-sequence" option. The reg sequences are working by Bob Wilson · 15 years ago
- 40cbe7d For NEON vectors with 32- or 64-bit elements, select BUILD_VECTORs and by Bob Wilson · 15 years ago
- 51e28e6 Early implementation of tail call for ARM. by Dale Johannesen · 15 years ago
- 18f30e6 Clean up 80 column violations. No functional change. by Jim Grosbach · 15 years ago
- 13ef840 Add the cc_out operand for t2RSBrs instructions. I missed this when I changed by Bob Wilson · 15 years ago
- 7bb31e3 Fix a few places that depended on the numeric value of subreg indices. by Jakob Stoklund Olesen · 15 years ago
- 558661d Switch ARMRegisterInfo.td to use SubRegIndex and eliminate the parallel enums by Jakob Stoklund Olesen · 15 years ago
- 3c3195c Target instruction selection should copy memoperands. by Evan Cheng · 15 years ago
- 6206124 Turn on -neon-reg-sequence by default. by Evan Cheng · 15 years ago
- 8f6de38 Model vst lane instructions with REG_SEQUENCE. by Evan Cheng · 15 years ago
- 7189fd0 Model 128-bit vld lane with REG_SEQUENCE. by Evan Cheng · 15 years ago
- 7092c2b Model 64-bit lane vld with REG_SEQUENCE. by Evan Cheng · 15 years ago
- 12c2469 Model VST*_UPD and VST*oddUPD pair with REG_SEQUENCE. by Evan Cheng · 15 years ago
- 5c6aba2 Model VLD*_UPD and VLD*odd_UPD pair with REG_SEQUENCE. by Evan Cheng · 15 years ago
- 7f68719 Fix comments. by Evan Cheng · 15 years ago
- 0ce537a Model some vst3 and vst4 with reg_sequence. by Evan Cheng · 15 years ago
- e9e2ba0 Model some vld3 instructions with REG_SEQUENCE. by Evan Cheng · 15 years ago
- 603afbf Model vld2 / vst2 with reg_sequence. by Evan Cheng · 15 years ago
- 429009b Add a missing break statement to fix unintentional fall-through by Bob Wilson · 15 years ago
- d31f00b Fix unintentional fallthrough. Patch by Edmund Grimley-Evans <Edmund.Grimley-Evans@arm.com> by Jim Grosbach · 15 years ago
- de8aa4e Model CONCAT_VECTORS of two 64-bit values as a REG_SEQUENCE. by Evan Cheng · 15 years ago
- 94cc6d3 With -neon-reg-sequence, models forming a Q register from a pair of consecutive D registers as a REG_SEQUENCE. by Evan Cheng · 15 years ago
- 3a1287b Update ARM DAGtoDAG for matching UBFX instruction for unsigned bitfield by Jim Grosbach · 15 years ago
- d858e90 Use const qualifiers with TargetLowering. This eliminates several by Dan Gohman · 15 years ago
- 47b7b9f Use getAL() rather than a major constant. by Evan Cheng · 15 years ago
- 3a1588a Use default lowering of DYNAMIC_STACKALLOC. As far as I can tell, ARM isle is doing the right thing and codegen looks correct for both Thumb and Thumb2. by Evan Cheng · 15 years ago
- 0ea7d21 ARM SelectDYN_ALLOC should emit a copy from SP rather than referencing SP directly. In cases where there are two dyn_alloc in the same BB it would have caused the old SP value to be reused and badness ensues. rdar://7493908 by Evan Cheng · 15 years ago
- df9a4f0 Fix VLDMQ and VSTMQ instructions to use the correct encoding and address modes. by Bob Wilson · 15 years ago
- 11d9899 Change VST1 instructions for loading Q register values to operate on pairs by Bob Wilson · 15 years ago
- 621f195 Change VLD1 instructions for loading Q register values to operate on pairs by Bob Wilson · 15 years ago
- a697975 Rename some VLD1/VST1 instructions to match the implementation, i.e., the by Bob Wilson · 15 years ago
- 226036e Re-commit r98683 ("remove redundant writeback flag from ARM address mode 6") by Bob Wilson · 15 years ago
- 95ffecd Rename some instructions for consistency and sanity: use "_UPD" suffix for by Bob Wilson · 15 years ago
- a43e6bf Revert 98683. It is breaking something in the disassembler. by Bob Wilson · 15 years ago
- bb6c77e Remove redundant writeback flag from ARM address mode 6. Also remove the by Bob Wilson · 15 years ago
- 7c306da Sink InstructionSelect() out of each target into SDISel, and rename it by Chris Lattner · 15 years ago
- 014bf21 Split SelectionDAGISel::IsLegalAndProfitableToFold to by Evan Cheng · 15 years ago
- 518bb53 move target-independent opcodes out of TargetInstrInfo by Chris Lattner · 16 years ago
- f609bb8 Fix r93758. Use isel patterns instead of c++ selection code to select rbit and make sure we pick different instructions for ARM vs. Thumb2. by Evan Cheng · 16 years ago
- 3482c80 Patch by David Conrad: by Jim Grosbach · 16 years ago
- 507d32a Fix an off-by-one error that caused the chain operand to be dropped from Neon by Bob Wilson · 16 years ago
- eeb3a00 Change SelectCode's argument from SDValue to SDNode *, to make it more by Dan Gohman · 16 years ago
- 5cdc3a9 Materialize global addresses via movt/movw pair, this is always better by Anton Korobeynikov · 16 years ago
- ac0869d Add predicate operand to NEON instructions. Fix lots (but not all) 80 col violations in ARMInstrNEON.td. by Evan Cheng · 16 years ago
- 9ef4835 Fix codegen of conditional move of immediates. We were not making use of the immediate forms of cmov instructions at all. by Evan Cheng · 16 years ago
- 07ba906 Refactor cmov selection code out to a separate function. No functionality change. by Evan Cheng · 16 years ago
- ed54de4 80 col violation. by Evan Cheng · 16 years ago
- e516549 Use Unified Assembly Syntax for the ARM backend. by Jim Grosbach · 16 years ago
- 8a5ec86 Support alignment specifier for NEON vld/vst instructions by Jim Grosbach · 16 years ago
- 73bb251 Remove uninteresting and confusing debug output. by Dan Gohman · 16 years ago
- 69e8445 Prune unnecessary include. by Bob Wilson · 16 years ago
- 6a3b5ee Test commit. Added '.' to the comment line. by Johnny Chen · 16 years ago
- 8000c6c Don't generate sbfx / ubfx with negative lsb field. Patch by David Conrad. by Evan Cheng · 16 years ago
- 2095659 Match more patterns to movt. by Evan Cheng · 16 years ago
- 681a2ad Remove unused variables to fix build warning. by Bob Wilson · 16 years ago