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gerrit-public.fairphone.software / fp2-dev / platform / external / llvm / f7769e3c2f11c4a2dcacae253ab8043b6c41a1b4 / lib
  1. 02082ef Remove 'v' from mnemonic to fix asm matching failures. by Craig Topper · 12 years ago
  2. 3cdc382 Use an additional multiclass to merge the 128/256-bit SSE/AVX instruction definitions for a bunch of SSE2 integer arithmetic instructions. by Craig Topper · 12 years ago
  3. a05f7cb Reformat the docs. by Nadav Rotem · 12 years ago
  4. 09a326d Use an additional multiclass to merge the 128/256-bit SSE/AVX instruction definitions for PAND/POR/PXOR/PANDN by Craig Topper · 12 years ago
  5. 1fe132a Merge an AVX/SSE 256-bit and 128-bit multiclass. by Craig Topper · 12 years ago
  6. b5c590a Mark VANDNPD/VANDNPDS as not commutable. by Craig Topper · 12 years ago
  7. 174a3d3 Remove alignment from a bunch more VEX encoded operations in the folding tables. by Craig Topper · 12 years ago
  8. d83a73a Remove alignment from folding table for VMOVUPD as an unaligned instruction it shouldn't require alignment... by Craig Topper · 12 years ago
  9. 1ac0046 Remove alignment requirements from (V)EXTRACTPS. This instruction does 32-bit stores which aren't required to be aligned on SSE or AVX. by Craig Topper · 12 years ago
  10. a777284 BBVectorize: Use VTTI to compute costs for intrinsics vectorization by Hal Finkel · 12 years ago
  11. 0f77910 Remove alignment requirement from VCVTSS2SD in folding tables. Reverting r171049. This instruction doesn't require alignment. by Craig Topper · 12 years ago
  12. 1d59f5f LoopVectorize: Enable vectorization of the fmuladd intrinsic by Hal Finkel · 12 years ago
  13. 64a7a24 BBVectorize: Enable vectorization of the fmuladd intrinsic by Hal Finkel · 12 years ago
  14. cd9ea51 Expand PPC64 atomic load and store by Hal Finkel · 12 years ago
  15. 59a65f7 [msan] Fix handling of vectors of pointers. by Evgeniy Stepanov · 12 years ago
  16. 6607716 [msan] Fix handling of select with vector condition. by Evgeniy Stepanov · 12 years ago
  17. 99f7806 X86: Shave off one shuffle from the pcmpeqq sequence for SSE2 by making use of and commutativity. by Benjamin Kramer · 12 years ago
  18. 382ed78 X86: Custom lower <2 x i64> eq and ne when SSE41 is not available. by Benjamin Kramer · 12 years ago
  19. 4684858 ASan: initialize callbacks from ASan module pass in a separate function for consistency by Alexey Samsonov · 12 years ago
  20. 59cca13 ASan: move stack poisoning logic into FunctionStackPoisoner struct by Alexey Samsonov · 12 years ago
  21. 08d785b Fix whitespace. No functionality change. by Nick Lewycky · 12 years ago
  22. a4c8a32 VCVTSS2SD requires a strict alignment. Thanks Elena. by Nadav Rotem · 12 years ago
  23. 04de315 Rename LLVMContext diagnostic handler types and functions. by Bob Wilson · 12 years ago
  24. 71f30bf Quiet gcc's -Wparenthesis warning. No functionality change. by Nick Lewycky · 12 years ago
  25. 791dbb3 Use a std::string rather than a dynamically allocated char* buffer. by Benjamin Kramer · 12 years ago
  26. a0be09f Add LLVMContext::emitWarning methods and use them. <rdar://problem/12867368> by Bob Wilson · 12 years ago
  27. 1e1c5f3 CostModel: We have API for checking the costs of known shuffles. This patch adds by Nadav Rotem · 12 years ago
  28. 94d7ab7 Added 6 more value types: v32i1, v64i1, v32i16, v32i8, v64i8, v8f64 by Elena Demikhovsky · 12 years ago
  29. 4b25467 Removed "static" from "__jit_debug_descriptor" because "static" adds C++ mangling prefix to this symbol. by Elena Demikhovsky · 12 years ago
  30. ace0c2f Some x86 instructions can load/store one of the operands to memory. On SSE, this memory needs to be aligned. by Nadav Rotem · 12 years ago
  31. 9e5329d LoopVectorizer: When checking for vectorizable types, also check by Nadav Rotem · 12 years ago
  32. daf7b5c Change the codegen Cost Model API for shuffeles. This patch removes the API for broadcast and adds a more general API that accepts an enum of known shuffles. by Nadav Rotem · 12 years ago
  33. 3a19999 Fix typo in comments by Alexey Samsonov · 12 years ago
  34. 99b7a99 Update the docs of the cost model. by Nadav Rotem · 12 years ago
  35. 470ea9b LoopVectorizer: Fix an endless loop in the code that looks for reductions. by Nadav Rotem · 12 years ago
  36. 6f3d81a CostModel: Change the default target-independent implementation for finding by Nadav Rotem · 12 years ago
  37. a1acf55 LoopVectorize: Fix accidentaly inverted condition. by Benjamin Kramer · 12 years ago
  38. 417872e LoopVectorize: For scalars and void types there is no need to compute vector insert/extract costs. by Benjamin Kramer · 12 years ago
  39. 40b04a4 whitespace by Nadav Rotem · 12 years ago
  40. 677689c Rename a function. by Nadav Rotem · 12 years ago
  41. d54fed2 Loop Vectorizer: Update the cost model of scatter/gather operations and make by Nadav Rotem · 12 years ago
  42. c4265e1 Remove trailing whitespace. by Craig Topper · 12 years ago
  43. 8a8413d Remove trailing whitespace by Craig Topper · 12 years ago
  44. 037435d Remove a special case that doesn't seem necessary any longer. by Jakob Stoklund Olesen · 12 years ago
  45. 021e3b6 Use getNumOperands() instead of Operands.size(). by Jakob Stoklund Olesen · 12 years ago
  46. 2f8a6cd X86: Turn mul of <4 x i32> into pmuludq when no SSE4.1 is available. by Benjamin Kramer · 12 years ago
  47. 1734791 X86: Emit vector sext as shuffle + sra if vpmovsx is not available. by Benjamin Kramer · 12 years ago
  48. 629fb82 Change 'AttrVal' to 'AttrKind' to better reflect that it's a kind of attribute instead of the value of the attribute. by Bill Wendling · 12 years ago
  49. 2b45dd5 Don't call back() on an empty SmallVector. Found by -fsanitize=enum! by Richard Smith · 12 years ago
  50. d0696ef In some cases, due to scheduling constraints we copy the EFLAGS. by Nadav Rotem · 12 years ago
  51. dbf51ee [mips] Refactor subword-swap, EXT/INS, load-effective-address and read-hardware by Akira Hatanaka · 12 years ago
  52. e8bc10b [mips] Refactor SYNC and multiply/divide instructions. by Akira Hatanaka · 12 years ago
  53. aa7c9cd [mips] Refactor BAL instructions. by Akira Hatanaka · 12 years ago
  54. 1892253 [mips] Fix encoding of BAL instruction. Also, fix assembler test case which by Akira Hatanaka · 12 years ago
  55. 6a8309e [mips] Refactor jump, jump register, jump-and-link and nop instructions. by Akira Hatanaka · 12 years ago
  56. 0a57dc1 [mips] Refactor load/store left/right and load-link and store-conditional by Akira Hatanaka · 12 years ago
  57. 1616465 [mips] Refactor load/store instructions. by Akira Hatanaka · 12 years ago
  58. 5f5770b [mips] Remove unnecessary isPseudo parameter. by Akira Hatanaka · 12 years ago
  59. 8e719fa [mips] Refactor LUI instruction. by Akira Hatanaka · 12 years ago
  60. 35242e2 [mips] Refactor count leading zero or one instructions. by Akira Hatanaka · 12 years ago
  61. 8aaed99 [mips] Refactor sign-extension-in-register instructions. by Akira Hatanaka · 12 years ago
  62. 7de001b [mips] Refactor instructions which copy from and to HI/LO registers. by Akira Hatanaka · 12 years ago
  63. 2a732ec [mips] Refactor logical NOR instructions. by Akira Hatanaka · 12 years ago
  64. a8215f4 [mips] Move instruction definitions in MipsInstrInfo.td. by Akira Hatanaka · 12 years ago
  65. b06c540 R600: Coding style - remove empty spaces from the beginning of functions by Tom Stellard · 12 years ago
  66. eef0d5a R600: Fix MAX_UINT definition by Tom Stellard · 12 years ago
  67. fe13e70 R600: Add SHADOWCUBE to TEX_SHADOW pattern by Tom Stellard · 12 years ago
  68. 4e23ebe Cleanup compiler warnings on discarding type qualifiers in casts. Switch to C++ style casts. by Benjamin Kramer · 12 years ago
  69. 2556c6b X86: Match pmin/pmax as a target specific dag combine. This occurs during vectorization. by Benjamin Kramer · 12 years ago
  70. 38b0602 Remove duplicate includes. by Roman Divacky · 12 years ago
  71. 519b456 R600: Expand vec4 INT <-> FP conversions by Tom Stellard · 12 years ago
  72. 739c7a8 X86: Match the SSE/AVX min/max vector ops using a custom node instead of intrinsics by Benjamin Kramer · 12 years ago
  73. 3333e66 [msan] Remove unreachable blocks before instrumenting a function. by Evgeniy Stepanov · 12 years ago
  74. 042a9a2 Add a missing "virtual" keyword. by Nadav Rotem · 12 years ago
  75. ebf395d Enable if-conversion. by Nadav Rotem · 12 years ago
  76. e0f1d71 Add ARM cortex-r5 subtarget. by Quentin Colombet · 12 years ago
  77. b66fc29 Don't skip __DWARF, by Rafael Espindola · 12 years ago
  78. cef81b3 Add a function to get the segment name of a section. by Rafael Espindola · 12 years ago
  79. ab37b2c Add targets to skip running the GC passes. by Evan Cheng · 12 years ago
  80. a16422f Every pass deserves a name, even codegenprep. by Evan Cheng · 12 years ago
  81. f5637c3 Improve the X86 cost model for loads and stores. by Nadav Rotem · 12 years ago
  82. c2a537b BB-Vectorizer: Check the cost of the store pointer type by Nadav Rotem · 12 years ago
  83. a40ba2b Call llvm_unreachable instead of assert. by Reed Kotler · 12 years ago
  84. 55306bd Fix a bug in the code that checks if we can vectorize loops while using dynamic by Nadav Rotem · 12 years ago
  85. 56706db Require the two-argument MI::addOperand(MF, MO) for dangling instructions. by Jakob Stoklund Olesen · 12 years ago
  86. be06aac Add an MF argument to MI::copyImplicitOps(). by Jakob Stoklund Olesen · 12 years ago
  87. 9500e5d Use two-arg addOperand(MF, MO) internally in MachineInstr when possible. by Jakob Stoklund Olesen · 12 years ago
  88. b9efafe MachineInstrBuilderize ARM. by Jakob Stoklund Olesen · 12 years ago
  89. 28d53a2 MachineInstrBuilderize NVPTX. by Jakob Stoklund Olesen · 12 years ago
  90. bc87361 Fix an unitialized member variable that may have caused sporadic failures by Eli Bendersky · 12 years ago
  91. 72c1655 Whitespace and 80-column cleanup. by Eric Christopher · 12 years ago
  92. 2e5d870 Start splitting out the debug string section handling by moving it by Eric Christopher · 12 years ago
  93. 27107f6 Some random comment, naming, and format changes. by Bill Wendling · 12 years ago
  94. 54c1902 Remove two dead functions. by Jakob Stoklund Olesen · 12 years ago
  95. 103b4a5 Revert "Adding support for llvm.arm.neon.vaddl[su].* and" by Bob Wilson · 12 years ago
  96. 8386acd LoopVectorize: Fix a bug in the scalarization of instructions. by Nadav Rotem · 12 years ago
  97. 139e407 On some ARM cpus, flags setting movs with shifter operand, i.e. lsl, lsr, asr, by Evan Cheng · 12 years ago
  98. 4766ef4 Aligned bundling support. Following the discussion here: by Eli Bendersky · 12 years ago
  99. 5d3cfa6 Use MachineInstrBuilder for PHI nodes in SelectionDAGISel. by Jakob Stoklund Olesen · 12 years ago
  100. 7f6ece8 Use MachineInstrBuilder in InstrEmitter. by Jakob Stoklund Olesen · 12 years ago