1. f7d87ee Change ARM scheduling default to list-hybrid if the target supports floating point instructions (and is not using soft float). by Evan Cheng · 15 years ago
  2. 1cc3984 Allow targets more controls on what nodes are scheduled by reg pressure, what for latency in hybrid mode. by Evan Cheng · 15 years ago
  3. 4e7f839 MC/X86: Add movq alias for movabsq, to allow matching 64-bit immediates with movq. by Daniel Dunbar · 15 years ago
  4. 1fe591d X86: Model i64i32imm properly, as a subclass of all immediates. by Daniel Dunbar · 15 years ago
  5. 0306e3d X86: Fix immediate type of FOO64i32 operations. by Daniel Dunbar · 15 years ago
  6. 63b8845 Handle Neon v2f64 and v2i64 vector shuffles as register copies. by Bob Wilson · 15 years ago
  7. 53e1849 Delete MMX_MOVQ64gmr. It was the same as MMX_MOVQ64mr, but it didn't by Dan Gohman · 15 years ago
  8. 5f07d52 The PPC MFCR instruction implicitly uses all 8 of the CR by Dale Johannesen · 15 years ago
  9. e5e4ff9 Fix assembly parsing and encoding of the pushf and popf family of instructions. by Dan Gohman · 15 years ago
  10. 100804f Set neverHasSideEffects on 64-bit pushf and popf, for consistency with by Dan Gohman · 15 years ago
  11. 14aaeac Define the x86 pause instruction. by Dan Gohman · 15 years ago
  12. ee5673b Fix the sfence instruction to use MRM_F8 instead of MRM7r, since it by Dan Gohman · 15 years ago
  13. 211ffa1 Code refactoring: pull SchedPreference enum from TargetLowering.h to TargetMachine.h and put it in its own namespace. by Evan Cheng · 15 years ago
  14. d94406a MC/X86: Add missing entry for TAILJMP_1 to getRelaxedOpcode(). by Daniel Dunbar · 15 years ago
  15. 52322e7 MC/X86: Lower TAILCALLd[64] to JMP_1, to allow relaxation and to avoid same by Daniel Dunbar · 15 years ago
  16. 7d4bd20 MC/X86: Strip spurious operands from TAILJMPr64 as we do for CALL64r and by Daniel Dunbar · 15 years ago
  17. 9085f98 t2LEApcrel and tLEApcrel are re-materializable. This makes it possible to hoist more loads during machine LICM. by Evan Cheng · 15 years ago
  18. 27fa722 Use 'adr' for LEApcrel and LEApcrel. Mark LEApcrel re-materializable. by Evan Cheng · 15 years ago
  19. 597f17d MC/X86: Lower MOV{8,16,32,64}{rm,mr} to fixed-register forms, as appropriate. by Daniel Dunbar · 15 years ago
  20. 5fd1c9b Mark pattern-less mayLoad / mayStore instructions neverHasSideEffects. These do not have other un-modeled side effects. by Evan Cheng · 15 years ago
  21. 3c3195c Target instruction selection should copy memoperands. by Evan Cheng · 15 years ago
  22. 9248b32 MC/X86: Strip spurious operands from CALL64r as we do for CALL64pcrel32, to by Daniel Dunbar · 15 years ago
  23. ea420b2 Mark a few more pattern-less instructions with neverHasSideEffects. This is especially important on instructions like t2LEApcreal which are prime candidate for machine LICM. by Evan Cheng · 15 years ago
  24. 7c2e039 Factor out the code for picking integer arithmetic with immediate by Dan Gohman · 15 years ago
  25. f8c1ef0 Teach mode load folding and unfolding code about CMP32ri8 and friends. by Dan Gohman · 15 years ago
  26. 2abc93d Don't eliminate frame pointers from leaf functions if "--disable-fp-elim" is by Bill Wendling · 15 years ago
  27. e5efbaf When converting a test to a cmp to fold a load, use the cmp that has an by Dan Gohman · 15 years ago
  28. 6db0363 make mcinstlower remove all but the first operand to CALL64pcrel32. by Chris Lattner · 15 years ago
  29. 28dad2a Sink dag combine's post index load / store code that swap base ptr and index into the target hook. Only the target knows whether the swap is safe. In Thumb2 mode, the offset must be an immediate. rdar://7998649 by Evan Cheng · 15 years ago
  30. 3f40b31 MC/X86: Implement custom lowering to make sure we match things like by Daniel Dunbar · 15 years ago
  31. 535af4a ARMBaseRegisterInfo::estimateRSStackSizeLimit() could return prematurely with a by Jakob Stoklund Olesen · 15 years ago
  32. 53f7602 - Set the "HasCalls" flag after instruction selection is finished. by Bill Wendling · 15 years ago
  33. 47006be vmov of immediates are trivially re-materializable. by Evan Cheng · 15 years ago
  34. 9a744e3 MC: Add dyn_cast support to MCSection. by Daniel Dunbar · 15 years ago
  35. 423c9e3 Add some section and constant support for darwin TLS. by Eric Christopher · 15 years ago
  36. 7f43fd8 Fix a regression in 464.h264 for thumb1 and thumb2 nightly tests. by Bob Wilson · 15 years ago
  37. 6206124 Turn on -neon-reg-sequence by default. by Evan Cheng · 15 years ago
  38. 9c207ac No reason not to run the NEON domain croassing fix up pass in thumb2 mode. by Evan Cheng · 15 years ago
  39. f7f5a27 Revert 103911; it broke a test that expects bitconvert by Dale Johannesen · 15 years ago
  40. f9b2242 Make x86-64 64-bit bitconvert work when SSE is not available. by Dale Johannesen · 15 years ago
  41. bd91ea5 Chris said that the comment char should be escaped. Fix all the occurences of "@" in *.td by Anton Korobeynikov · 15 years ago
  42. ded05e3 Add support for thiscall calling convention. by Anton Korobeynikov · 15 years ago
  43. 4878b84 Generalize the ARM DAG combiner of mul with constants to all power-of-two cases. by Anton Korobeynikov · 15 years ago
  44. 8f6de38 Model vst lane instructions with REG_SEQUENCE. by Evan Cheng · 15 years ago
  45. 8d908eb Fix uint64->{float, double} conversion to do rounding correctly in 32-bit. by Dale Johannesen · 15 years ago
  46. a9790d7 Some cheap DAG combine goodness for multiplication with a particular constant. by Anton Korobeynikov · 15 years ago
  47. 418d1d9 "trap" pseudo-op turned out to be apple-local. by Anton Korobeynikov · 15 years ago
  48. 7189fd0 Model 128-bit vld lane with REG_SEQUENCE. by Evan Cheng · 15 years ago
  49. 4782b1e v4i64 and v8i64 are only synthesizable when NEON is available. by Evan Cheng · 15 years ago
  50. 06b666c Allow TargetLowering::getRegClassFor() to be called on illegal types. Also by Evan Cheng · 15 years ago
  51. 7092c2b Model 64-bit lane vld with REG_SEQUENCE. by Evan Cheng · 15 years ago
  52. b990a2f Teach two-address pass to do some coalescing while eliminating REG_SEQUENCE by Evan Cheng · 15 years ago
  53. 12c2469 Model VST*_UPD and VST*oddUPD pair with REG_SEQUENCE. by Evan Cheng · 15 years ago
  54. 23ead99 SystemZ really does mean "has calls" and not just "adjusts stack." Go ahead and by Bill Wendling · 15 years ago
  55. 4ee637c BR is a barrier. by Dan Gohman · 15 years ago
  56. f84d60b Several tail call tests apparently rely upon this being "adjusts stack" instead by Bill Wendling · 15 years ago
  57. 55ed945 This should happen if there are no calls, not if it just doesn't adjust the by Bill Wendling · 15 years ago
  58. 0fc546b Revert r103804. The comment is correct. by Bill Wendling · 15 years ago
  59. d33fa0f Fix comment. by Bill Wendling · 15 years ago
  60. b92187a Rename "HasCalls" in MachineFrameInfo to "AdjustsStack" to better describe what by Bill Wendling · 15 years ago
  61. 71ea4e5 Lowering of atomic instructions can result in operands being by Dan Gohman · 15 years ago
  62. c3ce05c Fix so "int3" is correctly accepted, added "into" and fixed "int" with an by Kevin Enderby · 15 years ago
  63. 5c6aba2 Model VLD*_UPD and VLD*odd_UPD pair with REG_SEQUENCE. by Evan Cheng · 15 years ago
  64. effc8c5 Set isTerminator on TRAP instructions. by Dan Gohman · 15 years ago
  65. c0c32ae Don't use isBarrier for the PowerPC sync instruction. isBarrier is for by Dan Gohman · 15 years ago
  66. 7f357ec Add mayLoad and mayStore flags to instructions which missed them. by Dan Gohman · 15 years ago
  67. 22c687b Added a QQQQ register file to model 4-consecutive Q registers. by Evan Cheng · 15 years ago
  68. 7f68719 Fix comments. by Evan Cheng · 15 years ago
  69. c4ca40e Add comment about the pseudo registers QQ, each of which is a pair of Q registers. by Evan Cheng · 15 years ago
  70. 1190c14 Fix pr7110: For non-Darwin targets UnspilledCS1GPRs may include high registers. by Bob Wilson · 15 years ago
  71. ed36aac CMake: fixes 64 bit Visual Studio IDE build. Fixes bug 4936. by Oscar Fuentes · 15 years ago
  72. 61aeed1 Properly set thread-local flag on globals during cpp emission by Anton Korobeynikov · 15 years ago
  73. 1860e7d Fix -Asserts warning. by Daniel Dunbar · 15 years ago
  74. 69b9f98 Bring back VLD1q and VST1q and use them for reloading / spilling Q registers. This allows folding loads and stores into VMOVQ. by Evan Cheng · 15 years ago
  75. d929f77 Expand VMOVQQ into a pair of VMOVQ. by Evan Cheng · 15 years ago
  76. 020cc1b Mark some pattern-less instructions as neverHasSideEffects. by Evan Cheng · 15 years ago
  77. b5505d0 reapply r103668 with a fix. Never make "minor syntax changes" by Chris Lattner · 15 years ago
  78. 3519f9d revert r103668 for now, it is apparently breaking things. by Chris Lattner · 15 years ago
  79. 0de8e3f moffset forms of moves are x86-32 only, make the parser by Chris Lattner · 15 years ago
  80. 4313007 Fix some potential issues in the pseudo instruction expansion phase: copy implicit operands and memoperands. Also, expand instructions even if their defs are "dead" since they may have implicit kill operands. by Evan Cheng · 15 years ago
  81. 2745f6e fix the encoding of the obscure "moffset" forms of moves, i386 by Chris Lattner · 15 years ago
  82. a4d73d0 Remove a dead fixme. by Evan Cheng · 15 years ago
  83. 18c1021 Add support for movi32 of global values to the new (MC) asm printer. by Rafael Espindola · 15 years ago
  84. 5bdc2aa vst instructions are modeled as this: by Evan Cheng · 15 years ago
  85. 0481449 MC/X86: Extend suffix matching hack to match 'q' suffix. by Daniel Dunbar · 15 years ago
  86. a5f1d57 MC/Mach-O/x86_64: Add a new hook for checking whether a particular section can by Daniel Dunbar · 15 years ago
  87. a6cb641 Add initial kill flag support to FastISel. by Dan Gohman · 15 years ago
  88. 9647f3d Avoid breaking vstd when reg_sequence is not used. by Evan Cheng · 15 years ago
  89. f6d8481 Simplify this logic of creating a default Features object. by Bill Wendling · 15 years ago
  90. 16d8f8b I got tired of VISIBILITY_HIDDEN colliding with the gcc enum. Rename it by Duncan Sands · 15 years ago
  91. 99dca4f Remove the "WantsWholeFile" concept, as it's no longer needed. CBE by Dan Gohman · 15 years ago
  92. ff7a562 Implement a bunch more TargetSelectionDAGInfo infrastructure. by Dan Gohman · 15 years ago
  93. 419e4f9 Remove the TargetLowering::getSubtarget() virtual function, which by Dan Gohman · 15 years ago
  94. 2320a44 Make SPU backend not assert on jump tables. by Kalle Raiskila · 15 years ago
  95. fb3611d Select @llvm.trap to the special B with 1111 condition (i.e. trap) instruction. by Evan Cheng · 15 years ago
  96. 3cbae23 Don't create a StringRef with a NULL value. by Bill Wendling · 15 years ago
  97. 0ce537a Model some vst3 and vst4 with reg_sequence. by Evan Cheng · 15 years ago
  98. 81043ee The getDefaultSubtargetFeatures method of SubtargetFeature did actually return a by Bill Wendling · 15 years ago
  99. e9e2ba0 Model some vld3 instructions with REG_SEQUENCE. by Evan Cheng · 15 years ago
  100. 603afbf Model vld2 / vst2 with reg_sequence. by Evan Cheng · 15 years ago