Gitiles
Code Review Sign In
gerrit-public.fairphone.software / fp2-dev / platform / external / llvm / fc6d3a49867cd38954dc40936a88f1907252c6d2 / utils
  1. d568b3f Revert r134921, 134917, 134908 and 134907. They're causing failures by Eric Christopher · 13 years ago
  2. 5e3cb47 Use get(0 Instead of Create() by David Greene · 13 years ago
  3. 9bcc399 struct Init -> class Init. by Evan Cheng · 13 years ago
  4. 1bb6e28 Fix Build by David Greene · 13 years ago
  5. d4a9066 [AVX] Make Inits Foldable by David Greene · 13 years ago
  6. 7ae0df4 Resynchronize EDInfo.h and EDEmitter.cpp. by Shantonu Sen · 13 years ago
  7. 59ee62d - Eliminate MCCodeEmitter's dependency on TargetMachine. It now uses MCInstrInfo by Evan Cheng · 13 years ago
  8. 6bb5fe3 lit/LitConfig.py: Demote Win32 message "Unable to find 'bash.exe'" from Warning to Note. by NAKAMURA Takumi · 13 years ago
  9. 6043548 Fix dangling pointer. by Eli Friedman · 13 years ago
  10. fbc38d2 Fix a dangling reference. Patch by Dave Abrahams. pr10311 by Evan Cheng · 13 years ago
  11. 86f9adb TableGen'erated MC lowering for simple pseudo-instructions. by Jim Grosbach · 13 years ago
  12. ebdeeab Eliminate asm parser's dependency on TargetMachine: by Evan Cheng · 13 years ago
  13. 0ddff1b Compute feature bits at time of MCSubtargetInfo initialization. by Evan Cheng · 13 years ago
  14. e727d67 Add isCodeGenOnly value to the CodeGenInstruction class. by Jim Grosbach · 13 years ago
  15. 66c9ee7 Typo. by Jim Grosbach · 13 years ago
  16. 806fcc0 Don't require pseudo-instructions to carry encoding information. by Jim Grosbach · 13 years ago
  17. e234cd9 Allow tagless builds and fix debug build configuration. by David Greene · 13 years ago
  18. 68ae5b4 Remove the AsmWriterEmitter (unused) feature that rely on TargetSubtargetInfo. by Evan Cheng · 13 years ago
  19. 2f494b6 Use subprocess.Popen instead of popen2 to stop a deprecation warning when running lit on OS X by Jordy Rose · 13 years ago
  20. 5b1b4489 Rename TargetSubtarget to TargetSubtargetInfo for consistency. by Evan Cheng · 13 years ago
  21. 9421470 - Added MCSubtargetInfo to capture subtarget features and scheduling by Evan Cheng · 13 years ago
  22. 4db3cff Hide the call to InitMCInstrInfo into tblgen generated ctor. by Evan Cheng · 13 years ago
  23. ff97eb0 Pseudo-ize the Thumb tTPsoft instruction. by Jim Grosbach · 13 years ago
  24. 4629d50 Pseudo-ize the Thumb tPOP_RET instruction. by Jim Grosbach · 13 years ago
  25. 276365d Fix the ridiculous SubtargetFeatures API where it implicitly expects CPU name to by Evan Cheng · 13 years ago
  26. f6fd909 Remove redundant Thumb2 ADD/SUB SP instruction definitions. by Jim Grosbach · 13 years ago
  27. ae218de ARM RSCS* don't need explicit TableGen decoder checks. by Jim Grosbach · 13 years ago
  28. 74472b4 Refactor away tSpill and tRestore pseudos in ARM backend. by Jim Grosbach · 13 years ago
  29. 2e10b08 Change AsmName's type from StringRef to std::string. AsmName was pointing to a temporary string object that was destroyed. This is undefined behavior and MSVC didn't like it. by Francois Pichet · 13 years ago
  30. ab8be96 Sink SubtargetFeature and TargetInstrItineraries (renamed MCInstrItineraries) into MC. by Evan Cheng · 13 years ago
  31. d5b03f2 Move CallFrameSetupOpcode and CallFrameDestroyOpcode to TargetInstrInfo. by Evan Cheng · 13 years ago
  32. 6844f7b Hide more details in tablegen generated MCRegisterInfo ctor function. by Evan Cheng · 13 years ago
  33. 94b01f6 Add MCInstrInfo registeration machinery. by Evan Cheng · 13 years ago
  34. 22fee2d Merge XXXGenRegisterNames.inc into XXXGenRegisterInfo.inc by Evan Cheng · 13 years ago
  35. e837dea - Rename TargetInstrDesc, TargetOperandInfo to MCInstrDesc and MCOperandInfo and by Evan Cheng · 13 years ago
  36. 4987033f Alternative name enum should go into the enum portion. by Evan Cheng · 13 years ago
  37. 6b8f1e3 ARM Assembly support for Thumb mov-immediate. by Jim Grosbach · 13 years ago
  38. 4db3748 Remove RCBarriers from TargetInstrDesc. by Evan Cheng · 13 years ago
  39. bea6f61 Add support for alternative register names, useful for instructions whose operands are logically equivalent to existing registers, but happen to be printed specially. For example, an instruciton that prints d0[0] instead of s0. by Owen Anderson · 13 years ago
  40. ebbbfd0 More refactoring. MC doesn't need know about subreg indices. by Evan Cheng · 13 years ago
  41. 73f50d9 Merge XXXGenRegisterDesc.inc XXXGenRegisterNames.inc XXXGenRegisterInfo.h.inc by Evan Cheng · 13 years ago
  42. 025b37b Remove dead typedefs. by Evan Cheng · 13 years ago
  43. 5e6b460 Rename TargetRegisterDesc to MCRegisterDesc by Evan Cheng · 13 years ago
  44. 9c99cfe Revert "Shorten some ARM builtin names by removing unnecessary "neon" prefix." by Bob Wilson · 13 years ago
  45. e9e0e3a Shorten some ARM builtin names by removing unnecessary "neon" prefix. by Bob Wilson · 13 years ago
  46. f5fa52e - Add MCRegisterInfo registration machinery. Also added x86 registration routines. by Evan Cheng · 13 years ago
  47. 5c10b63 Make the generated InitXXXMCRegisterInfo function "static inline", so it doesn't get emitted into multiple object files. by Benjamin Kramer · 13 years ago
  48. a347f85 Starting to refactor Target to separate out code that's needed to fully describe by Evan Cheng · 13 years ago
  49. f2a5842 lit support for REQUIRES: asserts. by Andrew Trick · 13 years ago
  50. a7b1d17 Unbreak the CMake build by Francois Pichet · 13 years ago
  51. 0b6a44a Consolidate some TableGen diagnostic helper functions. by Jim Grosbach · 13 years ago
  52. 9b718e8 Skip fields that don't exist in the Register class. by Jakob Stoklund Olesen · 13 years ago
  53. 4ce25d5 Add a RegisterTuples class to Target.td and TableGen. by Jakob Stoklund Olesen · 13 years ago
  54. b231866 fix the varargs version of StructType::get to not require an LLVMContext, making usage by Chris Lattner · 13 years ago
  55. c6596e2 Use the correct comparator to avoid depending on pointer values. by Jakob Stoklund Olesen · 13 years ago
  56. abdbc84 Store CodeGenRegisters as pointers so they won't be reallocated. by Jakob Stoklund Olesen · 13 years ago
  57. 54c47c1 Remove MethodProtos/MethodBodies and allocation_order_begin/end. by Jakob Stoklund Olesen · 13 years ago
  58. b4c7048 Provide AltOrders for specifying alternative allocation orders. by Jakob Stoklund Olesen · 13 years ago
  59. 23b0766 Fix formatting. by Owen Anderson · 13 years ago
  60. 2559011 Prempt some obnoxious compiler from complaing about signed/unsigned compares. by Jakob Stoklund Olesen · 13 years ago
  61. 0cc0929 Make sure to pass an unsigned to a printf format that is always %u. by Jakob Stoklund Olesen · 13 years ago
  62. 05c087d Add support to lit for build mode requirements. e.g. by Andrew Trick · 13 years ago
  63. 77b4b13 Add a new MVT::untyped. This will be used in future work for modelling ISA features like register pairs and lists with "interesting" constraints (such as ARM NEON contiguous register lists or even-odd paired registers). We need to be able to generate these instructions (often from intrinsics), but don't want to have to assign a legal type to them. Instead, we'll use an "untyped" edge to bypass the type-checking and simply ensure that the register classes match. by Owen Anderson · 13 years ago
  64. f14bacc Update the Clang diagnostic emitter to emit IDs for diagnostic categories. by John McCall · 13 years ago
  65. 3a3465b Add a new function attribute, nonlazybind, which inhibits lazy-loading by John McCall · 13 years ago
  66. 1e56a2a Replace the statically generated hashtables for checking register relationships with just scanning the (typically tiny) static lists. by Owen Anderson · 13 years ago
  67. 59f26aa Use a SetTheory instance to expand register lists in register classes. by Jakob Stoklund Olesen · 13 years ago
  68. ae1920b Give CodeGenRegisterClass a real sorted member set. by Jakob Stoklund Olesen · 13 years ago
  69. 393c404 Improve the heuristic to emit the alias if the number of hard-coded registers by Bill Wendling · 13 years ago
  70. 7b9cafd Move the list of register classes into CodeGenRegBank as well. by Jakob Stoklund Olesen · 13 years ago
  71. 952036d Fix a compile time regression caused by too small hash tables. by Jakob Stoklund Olesen · 13 years ago
  72. 740e5b3 Heuristic: If the number of operands in the alias are more than the number of by Bill Wendling · 13 years ago
  73. b95fd2d Tweak hash function and compress hash tables. by Jakob Stoklund Olesen · 13 years ago
  74. bf710cc Remove now dead code. by Jakob Stoklund Olesen · 13 years ago
  75. 4091b05 Extract the generateHashTable function. by Jakob Stoklund Olesen · 13 years ago
  76. 026dc22 Compute lists of sub-regs, super-regs, and overlapping regs. by Jakob Stoklund Olesen · 13 years ago
  77. b5923db Move the list of registers into CodeGenRegBank. by Jakob Stoklund Olesen · 13 years ago
  78. dc29c44 Move some sub-register index calculations to CodeGenRegisters.cpp by Jakob Stoklund Olesen · 13 years ago
  79. f1e2b23 Move TableGen's register bank classes to their own source file. by Jakob Stoklund Olesen · 13 years ago
  80. e450a00 Add special-case range checking for VCVT_N intrinsic immediate operands. by Bob Wilson · 13 years ago
  81. 36a300a Fixed a few illegal paths with llvm_unreachable. Patch by Cameron McInally. by Chad Rosier · 13 years ago
  82. c017bc1 Drop a RecordKeeper reference that wasn't necessary. by Jakob Stoklund Olesen · 13 years ago
  83. 1023f5a Silence compiler warnings. by Jakob Stoklund Olesen · 13 years ago
  84. 1de9982 Teach TableGen to evaluate DAG expressions as set operations. by Jakob Stoklund Olesen · 13 years ago
  85. b2afe87 Rework the logic to not rely on undefined behaviour (1LL << 64). Also simplify. by Nick Lewycky · 13 years ago
  86. f462e3f Make it possible to have unallocatable register classes. by Jakob Stoklund Olesen · 13 years ago
  87. dd13790 Add new -d option to tblgen. It writes a make(1)-style dependency file. by Joerg Sonnenberger · 13 years ago
  88. 895c1e2 Fix ssat and ssat16 encodings for ARM and Thumb. The bit position value by Bruno Cardoso Lopes · 13 years ago
  89. 6e03294 Use the dwarf->llvm mapping to print register names in the cfi directives. by Rafael Espindola · 13 years ago
  90. 7a067cc Introduce the DwarfRegAlias class for declaring that two registers have the by Rafael Espindola · 13 years ago
  91. bd0fa4c Change how tblgen generates attributes for intrinsics to use a single by John McCall · 13 years ago
  92. 7bf114c Fix the root cause of the bootstrap failure: by Rafael Espindola · 13 years ago
  93. 804cb23 [tablegen] A couple of changes to ClangDiagnosticEmmitter. by Argyrios Kyrtzidis · 13 years ago
  94. f415d8b Use a more efficient data structure for the "operand map". The number of by Bill Wendling · 13 years ago
  95. 3a2d255 Fix PR9947 by placing OPFL_MemRefs on the node using memory operands rather than by Cameron Zwarich · 13 years ago
  96. 2a8eb72 In r131488 I misunderstood how VREV works. It splits the vector in half and splits each half. Therefore, the real problem was that we were using a VREV64 for a 4xi16, when we should have been using a VREV32. by Tanya Lattner · 13 years ago
  97. c81c970 vrev is incorrectly defined in the perfect shuffle table. The ordering is backwards (should be 0x3210 versus 0x1032) which exposed a bug when doing a shuffle on a 4xi16. I've attached a test case. by Tanya Lattner · 13 years ago
  98. 4bfc6fb Downgrade a tablegen warning to an error. by Jakob Stoklund Olesen · 13 years ago
  99. 183c627 Fixed MC encoding for index_align for VLD1/VST1 (single element from one lane) for size 32 by Mon P Wang · 13 years ago
  100. 123cab9 Teach TableGen to automatically generate missing SubRegIndex instances. by Jakob Stoklund Olesen · 13 years ago