- ffde080 Convert VLD1 and VLD2 instructions to use pseudo-instructions until by Bob Wilson · 15 years ago
- d0b69cf Remove NEON vmull, vmlal, and vmlsl intrinsics, replacing them with multiply, by Bob Wilson · 15 years ago
- 973a074 Remove NEON vmovn intrinsic, replacing it with vector truncate operations. by Bob Wilson · 15 years ago
- 04d6c28 Remove NEON vaddl, vaddw, vsubl, and vsubw intrinsics. Instead, use llvm by Bob Wilson · 15 years ago
- e5ce4f6 Use pseudo instructions for VST1 and VST2. by Bob Wilson · 15 years ago
- fd7fd94 We don't need to custom-select VLDMQ and VSTMQ anymore. by Bob Wilson · 15 years ago
- d4bfd54 Change ARM VFP VLDM/VSTM instructions to use addressing mode #4, just like by Bob Wilson · 15 years ago
- 01ba461 Use pseudo instructions for VST3. by Bob Wilson · 15 years ago
- 70e48b2 Use pseudo instructions for VST1d64Q. by Bob Wilson · 15 years ago
- 709d592 Start converting NEON load/stores to use pseudo instructions, beginning here by Bob Wilson · 15 years ago
- b31a11b Replace the arm.neon.vmovls and vmovlu intrinsics with vector sign-extend and by Bob Wilson · 15 years ago
- 425f634 Silence some -Asserts uninitialized variable warnings. by Daniel Dunbar · 15 years ago
- 7e3f0d2 Add support for NEON VMVN immediate instructions. by Bob Wilson · 15 years ago
- 046afdb The bits in the cmode field of 32-bit VMOV immediate instructions all depend by Bob Wilson · 15 years ago
- cba270d Use a target-specific VMOVIMM DAG node instead of BUILD_VECTOR to represent by Bob Wilson · 15 years ago
- 78dfbc3 Also use REG_SEQUENCE for VTBX instructions. by Bob Wilson · 15 years ago
- d491d6e Use REG_SEQUENCE nodes to make the table registers for VTBL instructions be by Bob Wilson · 15 years ago
- 8c605c6 Fix indentation. by Bob Wilson · 15 years ago
- 31ef8e6 Remove a fixme comment that is no longer relevant. by Bob Wilson · 15 years ago
- 827b210 Add basic support for NEON modified immediates besides VMOV. by Bob Wilson · 15 years ago
- d3c4284 Rename functions referring to VMOV immediates to refer to NEON "modified by Bob Wilson · 15 years ago
- 1a913ed Add instruction encoding for the Neon VMOV immediate instruction. This changes by Bob Wilson · 15 years ago
- 53dd245 Further changes for Neon vector shuffles: by Bob Wilson · 15 years ago
- 7bb31e3 Fix a few places that depended on the numeric value of subreg indices. by Jakob Stoklund Olesen · 15 years ago
- 558661d Switch ARMRegisterInfo.td to use SubRegIndex and eliminate the parallel enums by Jakob Stoklund Olesen · 15 years ago
- 5fd1c9b Mark pattern-less mayLoad / mayStore instructions neverHasSideEffects. These do not have other un-modeled side effects. by Evan Cheng · 15 years ago
- 47006be vmov of immediates are trivially re-materializable. by Evan Cheng · 15 years ago
- bd91ea5 Chris said that the comment char should be escaped. Fix all the occurences of "@" in *.td by Anton Korobeynikov · 15 years ago
- 22c687b Added a QQQQ register file to model 4-consecutive Q registers. by Evan Cheng · 15 years ago
- 69b9f98 Bring back VLD1q and VST1q and use them for reloading / spilling Q registers. This allows folding loads and stores into VMOVQ. by Evan Cheng · 15 years ago
- 020cc1b Mark some pattern-less instructions as neverHasSideEffects. by Evan Cheng · 15 years ago
- 435d499 Use VLD2q32 / VST2q32 to reload / spill QQ (pair of Q) registers when stack slot is sufficiently aligned. Use VLDMD / VSTMD otherwise. by Evan Cheng · 15 years ago
- c10b5af Remove VLD1q and VST1q for reloading and spilling Q registers. Just use VLD1q64 / VST1q64 and reference sub-registers. by Evan Cheng · 15 years ago
- b63387a Re-apply 103156 and 103157. 103156 didn't break anything. 10315 exposed a coalescer bug that's fixed by 103170. by Evan Cheng · 15 years ago
- f865cb5 Revert r103156 since it was breaking the build bots. by Eric Christopher · 15 years ago
- 4ffc22a Adding pseudo 256-bit registers QQ0 . . . QQ7 to represent pairs of Q registers. These will be used to model VLD2 / VST2 instructions in order to get substantially better codegen for them. by Evan Cheng · 15 years ago
- ecc6406 More fixes for itins by Anton Korobeynikov · 15 years ago
- 9510207 Fix invalid itins for 32-bit varians of VMLAL and friends by Anton Korobeynikov · 15 years ago
- 0a3e2b5 Fix itins for VABA by Anton Korobeynikov · 15 years ago
- fc2b084 Correct VMVN itinerary: operand is read in the second cycle, not in the first. by Anton Korobeynikov · 15 years ago
- e715b1e More A9 itineraries by Anton Korobeynikov · 15 years ago
- 1c03f24 Correct itinerary class for VPADD by Anton Korobeynikov · 15 years ago
- 4ac0af8 VP{MAX, MIN} are of IIC_VSUBi4D itin class as well. by Anton Korobeynikov · 15 years ago
- f8b5c63 VHADD differs from VHSUB at least on A9 - the former reads both operands in the second cycle, while the latter reads second operand in first cycle. Introduce new itin classes to catch this behavior. Whether this is true for A8 as well is WIP. by Anton Korobeynikov · 15 years ago
- 79c4d82 Add NVTBLFrm to represent A8.6.406 VTBL, VTBX Vector Table Lookup Instructions. by Johnny Chen · 15 years ago
- 0a00ed9 fix integer negates to use the proper type for the zero vectors, by Chris Lattner · 15 years ago
- b26fdcb fix vnot matching to explicitly specify the type of the by Chris Lattner · 15 years ago
- 2cd1a12 Fix indentation. by Bob Wilson · 15 years ago
- 10bc69c Add a format argument to the N3V and N3VX classes, removing the N3Vf class. by Bob Wilson · 15 years ago
- 897dd0c Add NVMulSLFrm to represent "3-register multiply with scalar" operations and set by Johnny Chen · 15 years ago
- 9ee9d7d Remove the duplicate multiclass N3VSh_QHSD and use N3VInt_QHSD which is modified by Johnny Chen · 15 years ago
- 629c25c Add NVExtFrm to represent NEON Vector Extract Instructions, that uses Inst{11-8} by Johnny Chen · 15 years ago
- c6e704d Add N3RegVShFrm to represent 3-Register Vector Shift Instructions, which do not by Johnny Chen · 15 years ago
- 0a3dc10 Add N2RegVShLFrm and N2RegVShRFrm formats so that the disassembler can easily by Johnny Chen · 15 years ago
- fa80bec Add NVCVTFrm (NEON Convert with fractional bits immediate) and modify N2VImm to by Johnny Chen · 15 years ago
- e4614f7 Added a new instruction class NVDupLane to be inherited by VDUPLND and VDUPLNQ, by Johnny Chen · 15 years ago
- 69631b1 Trivial formating change. by Johnny Chen · 15 years ago
- 2fadd6b Reverted r99326 which added NVdVmVCVTFrm, and later renamed to NVCVTFrm. by Johnny Chen · 15 years ago
- 7d85ac0 Reverted r99376. The disassembler will deal with the 2-reg format of these two by Johnny Chen · 15 years ago
- b7ba578 Mark VMOVDneon and VMOVQ as having the N2RegFrm form to help the disassembler. by Johnny Chen · 15 years ago
- c5f413a Renamed NVdVmImmFrm and NVdVmVCVTFrm to the more proper N2RegFrm and NVCVTFrm, by Johnny Chen · 15 years ago
- be7849e Add comment. by Johnny Chen · 15 years ago
- 3ae9a57 Add New NEON Format NVdVmVCVTFrm. by Johnny Chen · 15 years ago
- df9a4f0 Fix VLDMQ and VSTMQ instructions to use the correct encoding and address modes. by Bob Wilson · 15 years ago
- c289a02 Rename some instructions to match the corresponding NEON opcode. by Bob Wilson · 15 years ago
- 11d9899 Change VST1 instructions for loading Q register values to operate on pairs by Bob Wilson · 15 years ago
- 621f195 Change VLD1 instructions for loading Q register values to operate on pairs by Bob Wilson · 15 years ago
- 62ef3c8 Rename one more NEON instruction that I missed earlier. by Bob Wilson · 15 years ago
- 052ba45 Regroup some instructions. No functional change. by Bob Wilson · 15 years ago
- a697975 Rename some VLD1/VST1 instructions to match the implementation, i.e., the by Bob Wilson · 15 years ago
- 58393bc Remove some redundant instruction classes. by Bob Wilson · 15 years ago
- 3984255 Refactor instruction encoding arguments for VLDnLN/VSTnLN classes to by Bob Wilson · 15 years ago
- 226036e Re-commit r98683 ("remove redundant writeback flag from ARM address mode 6") by Bob Wilson · 15 years ago
- d5fadaf Add instruction variants for VST2, VST3, and VST4 "store-lane" operations with by Bob Wilson · 15 years ago
- 4f4f93f Add variants of VST2, VST3 and VST4 with address register writeback, and by Bob Wilson · 15 years ago
- 068b18b Add instructions for double-spaced VST3 and VST4 without address register by Bob Wilson · 15 years ago
- 25eb501 Add VST1 instructions with address register writeback. by Bob Wilson · 15 years ago
- a102364 Add instruction variants for VLD2, VLD3, and VLD4 "load-lane" operations with by Bob Wilson · 15 years ago
- 4131528 Tidy some more comments and whitespace. by Bob Wilson · 15 years ago
- 92cb932 Add variants of VLD2, VLD3 and VLD4 with address register writeback, and by Bob Wilson · 15 years ago
- 667a13e Tidy some comments and whitespace for consistency. by Bob Wilson · 15 years ago
- 95ffecd Rename some instructions for consistency and sanity: use "_UPD" suffix for by Bob Wilson · 15 years ago
- 00bf1d9 Add instructions for double-spaced VLD3 and VLD4 without address register by Bob Wilson · 15 years ago
- 99493b2 Add VLD1 instructions with address register writeback. by Bob Wilson · 15 years ago
- 76a312b Revert this change, since it was causing ARM performance regressions. by Bob Wilson · 15 years ago
- 341ab13 Get rid of target-specific fp <-> int nodes when still I'm here. by Anton Korobeynikov · 15 years ago
- 9580832 Refactor NEON ld/st instructions to hardcode class arguments that are constants. by Bob Wilson · 15 years ago
- 6c8648b Revert 98745 with respect to the addition of NEONFrm subformats for disassembly. by Johnny Chen · 15 years ago
- 9e08876 Added sub-formats to the NeonI/NeonXI instructions to further refine the NEONFrm by Johnny Chen · 15 years ago
- a43e6bf Revert 98683. It is breaking something in the disassembler. by Bob Wilson · 15 years ago
- bb6c77e Remove redundant writeback flag from ARM address mode 6. Also remove the by Bob Wilson · 15 years ago
- 49d9dc4 --- Reverse-merging r98637 into '.': by Bob Wilson · 15 years ago
- d30a98e Initial ARM/Thumb disassembler check-in. It consists of a tablgen backend by Johnny Chen · 15 years ago
- 77144e7 fix an ambiguous pattern, contrary to expectations, scalar_to_vector by Chris Lattner · 15 years ago
- 5027064 Remove obsolete comments. VLDM is implemented in ARMInstrVFP.td. by Bob Wilson · 15 years ago
- d10a53d fix a bunch of partially ambiguous patterns on ARM. As an example, this: by Chris Lattner · 15 years ago
- d883604 Added Vector Swap (VSWPd and VSWPq) instructions for disassembly only. by Johnny Chen · 15 years ago
- 39b0316 Fixed typo of opcodestr, should be "vst1", not "vld1". by Johnny Chen · 15 years ago
- f50e83f Added for disassembly VST1 (multiple single elements) which stores elements to by Johnny Chen · 15 years ago
- d7283d9 Added for disassembly VLD1 (multiple single elements) which loads memory into by Johnny Chen · 15 years ago