| commit | 8f61114907669b2134fbdc1a794926035486e8df | [log] [tgz] |
|---|---|---|
| author | Eric Anholt <eric@anholt.net> | Sun May 23 21:00:13 2010 -0700 |
| committer | Eric Anholt <eric@anholt.net> | Wed May 26 12:13:54 2010 -0700 |
| tree | 1874c6a80dfdd42327cb4ecc44f8f03a4b0ffb0e | |
| parent | 6e2330daa6d7872405485ffabfe613a7c053d890 [diff] |
i965: Don't PIPE_CONTROL instruction cache flush. This is a workaround for Ironlake errata. The emit_mi_flush is used for a few purposes: 1) Flushing write caches for RTT (including blit to texture) 2) Pipe fencing for sync objects 3) Spamming cache flushes to track down cache flush bugs Spamming cache flushes seems less important than following the docs, and we should probably do that with a different mechanism than the one for render cache flushes.