| # XScale 1 events |
| # |
| event:0x00 counters:1,2 um:zero minimum:500 name:IFU_IFETCH_MISS : number of instruction fetch misses |
| event:0x01 counters:1,2 um:zero minimum:500 name:CYCLES_IFU_MEM_STALL : cycles instruction fetch pipe is stalled |
| event:0x02 counters:1,2 um:zero minimum:500 name:CYCLES_DATA_STALL : cycles stall occurs for due to data dependency |
| event:0x03 counters:1,2 um:zero minimum:500 name:ITLB_MISS : number of ITLB misses |
| event:0x04 counters:1,2 um:zero minimum:500 name:DTLB_MISS : number of DTLB misses |
| event:0x05 counters:1,2 um:zero minimum:500 name:BR_INST_EXECUTED : branch instruction executed w/ or w/o program flow change |
| event:0x06 counters:1,2 um:zero minimum:500 name:BR_INST_MISS_PRED : branch mispredicted |
| event:0x07 counters:1,2 um:zero minimum:500 name:INSN_EXECUTED : instruction executed |
| event:0x08 counters:1,2 um:zero minimum:500 name:CYCLES_DCACHE_FULL_STALL : cycles in stall due to full dcache |
| event:0x09 counters:1,1 um:zero minimum:500 name:DCACHE_FULL_STALL_CNT : number of stalls due to dcache full condition |
| event:0x0a counters:1,2 um:zero minimum:500 name:DCACHE_ACCESS : data cache access |
| event:0x0b counters:1,2 um:zero minimum:500 name:DCACHE_MISS : data cache miss |
| event:0x0c counters:1,2 um:zero minimum:500 name:DCACHE_WB : data cache writeback, 1 event for every half cacheline |
| event:0x0d counters:1,2 um:zero minimum:500 name:PC_CHANGE : number of times the program counter was changed without a mode switch |
| event:0xfe counters:0 um:zero minimum:500 name:CPU_CYCLES : clock cycles counter |
| #0x10 through 0x17 Defined by ASSP. See the Intel® XScale" core implementation option section of the ASSP |
| #architecture specification for more details. |