| #Group Default |
| event:0x001 mmcr0:0x0400C000 mmcr1:0x4000000002341E36 mmcra:0x00000001 |
| |
| #Group 9 LSU SRQ and LMQ events |
| event:0x010 mmcr0:0x0400C000 mmcr1:0x010F000A102ACA2A mmcra:0x00000000 |
| event:0x011 mmcr0:0x0400C000 mmcr1:0x010F000A102ACA2A mmcra:0x00000000 |
| event:0x012 mmcr0:0x0400C000 mmcr1:0x010F000A102ACA2A mmcra:0x00000000 |
| event:0x013 mmcr0:0x0400C000 mmcr1:0x010F000A102ACA2A mmcra:0x00000000 |
| event:0x014 mmcr0:0x0400C000 mmcr1:0x010F000A102ACA2A mmcra:0x00000000 |
| event:0x015 mmcr0:0x0400C000 mmcr1:0x010F000A102ACA2A mmcra:0x00000000 |
| |
| #Group 13 Misc prefetch and reject events |
| event:0x01a mmcr0:0x0400C000 mmcr1:0x063E000EC0C8CC86 mmcra:0x00000000 |
| event:0x01b mmcr0:0x0400C000 mmcr1:0x063E000EC0C8CC86 mmcra:0x00000000 |
| event:0x01c mmcr0:0x0400C000 mmcr1:0x063E000EC0C8CC86 mmcra:0x00000000 |
| event:0x01d mmcr0:0x0400C000 mmcr1:0x063E000EC0C8CC86 mmcra:0x00000000 |
| event:0x01e mmcr0:0x0400C000 mmcr1:0x063E000EC0C8CC86 mmcra:0x00000000 |
| event:0x01f mmcr0:0x0400C000 mmcr1:0x063E000EC0C8CC86 mmcra:0x00000000 |
| |
| #Group 14 LSU reject events |
| event:0x020 mmcr0:0x0400C000 mmcr1:0xC22C000E2010C610 mmcra:0x00000001 |
| event:0x021 mmcr0:0x0400C000 mmcr1:0xC22C000E2010C610 mmcra:0x00000001 |
| event:0x022 mmcr0:0x0400C000 mmcr1:0xC22C000E2010C610 mmcra:0x00000001 |
| event:0x023 mmcr0:0x0400C000 mmcr1:0xC22C000E2010C610 mmcra:0x00000001 |
| event:0x024 mmcr0:0x0400C000 mmcr1:0xC22C000E2010C610 mmcra:0x00000001 |
| event:0x025 mmcr0:0x0400C000 mmcr1:0xC22C000E2010C610 mmcra:0x00000001 |
| |
| #Group 43 L1 load and TLB misses |
| event:0x02b mmcr0:0x0400C000 mmcr1:0x00B000008E881020 mmcra:0x00000000 |
| event:0x02c mmcr0:0x0400C000 mmcr1:0x00B000008E881020 mmcra:0x00000000 |
| event:0x02d mmcr0:0x0400C000 mmcr1:0x00B000008E881020 mmcra:0x00000000 |
| event:0x02e mmcr0:0x0400C000 mmcr1:0x00B000008E881020 mmcra:0x00000000 |
| event:0x02f mmcr0:0x0400C000 mmcr1:0x00B000008E881020 mmcra:0x00000000 |
| |
| #Group 44 L1 store and DERAT misses |
| event:0x030 mmcr0:0x0400C000 mmcr1:0x00B300000E202086 mmcra:0x00000000 |
| event:0x031 mmcr0:0x0400C000 mmcr1:0x00B300000E202086 mmcra:0x00000000 |
| event:0x033 mmcr0:0x0400C000 mmcr1:0x00B300000E202086 mmcra:0x00000000 |
| event:0x034 mmcr0:0x0400C000 mmcr1:0x00B300000E202086 mmcra:0x00000000 |
| event:0x035 mmcr0:0x0400C000 mmcr1:0x00B300000E202086 mmcra:0x00000000 |
| |
| #Group 45 L1 load and SLB misses |
| event:0x03a mmcr0:0x0400C000 mmcr1:0x00B000008A82848C mmcra:0x00000000 |
| event:0x03b mmcr0:0x0400C000 mmcr1:0x00B000008A82848C mmcra:0x00000000 |
| event:0x03c mmcr0:0x0400C000 mmcr1:0x00B000008A82848C mmcra:0x00000000 |
| event:0x03d mmcr0:0x0400C000 mmcr1:0x00B000008A82848C mmcra:0x00000000 |
| event:0x03e mmcr0:0x0400C000 mmcr1:0x00B000008A82848C mmcra:0x00000000 |
| event:0x03f mmcr0:0x0400C000 mmcr1:0x00B000008A82848C mmcra:0x00000000 |
| |
| #Group 46 L1 load references and 4k Data TLB references and misses |
| event:0x040 mmcr0:0x0400C000 mmcr1:0x0BF0000084808088 mmcra:0x00000000 |
| event:0x041 mmcr0:0x0400C000 mmcr1:0x0BF0000084808088 mmcra:0x00000000 |
| event:0x042 mmcr0:0x0400C000 mmcr1:0x0BF0000084808088 mmcra:0x00000000 |
| event:0x043 mmcr0:0x0400C000 mmcr1:0x0BF0000084808088 mmcra:0x00000000 |
| event:0x044 mmcr0:0x0400C000 mmcr1:0x0BF0000084808088 mmcra:0x00000000 |
| event:0x045 mmcr0:0x0400C000 mmcr1:0x0BF0000084808088 mmcra:0x00000000 |
| |
| #Group 47 L1 store references and 16M Data TLB references and misses |
| event:0x04a mmcr0:0x0400C000 mmcr1:0x0BF000008C88828A mmcra:0x00000000 |
| event:0x04b mmcr0:0x0400C000 mmcr1:0x0BF000008C88828A mmcra:0x00000000 |
| event:0x04c mmcr0:0x0400C000 mmcr1:0x0BF000008C88828A mmcra:0x00000000 |
| event:0x04d mmcr0:0x0400C000 mmcr1:0x0BF000008C88828A mmcra:0x00000000 |
| event:0x04e mmcr0:0x0400C000 mmcr1:0x0BF000008C88828A mmcra:0x00000000 |
| event:0x04f mmcr0:0x0400C000 mmcr1:0x0BF000008C88828A mmcra:0x00000000 |
| |
| #Group 48 L3 cache and memory data access |
| event:0x050 mmcr0:0x0400C000 mmcr1:0x400300001C0E8E02 mmcra:0x00000000 |
| event:0x051 mmcr0:0x0400C000 mmcr1:0x400300001C0E8E02 mmcra:0x00000000 |
| event:0x052 mmcr0:0x0400C000 mmcr1:0x400300001C0E8E02 mmcra:0x00000000 |
| event:0x053 mmcr0:0x0400C000 mmcr1:0x400300001C0E8E02 mmcra:0x00000000 |
| event:0x054 mmcr0:0x0400C000 mmcr1:0x400300001C0E8E02 mmcra:0x00000000 |
| event:0x055 mmcr0:0x0400C000 mmcr1:0x400300001C0E8E02 mmcra:0x00000000 |
| |
| #Group 49 L3 cacahe and memory data access |
| event:0x05a mmcr0:0x0400C000 mmcr1:0x000300031C0E360E mmcra:0x00000000 |
| event:0x05b mmcr0:0x0400C000 mmcr1:0x000300031C0E360E mmcra:0x00000000 |
| event:0x05c mmcr0:0x0400C000 mmcr1:0x000300031C0E360E mmcra:0x00000000 |
| event:0x05d mmcr0:0x0400C000 mmcr1:0x000300031C0E360E mmcra:0x00000000 |
| event:0x05e mmcr0:0x0400C000 mmcr1:0x000300031C0E360E mmcra:0x00000000 |
| event:0x05f mmcr0:0x0400C000 mmcr1:0x000300031C0E360E mmcra:0x00000000 |
| |
| #Group 50 L2 cache data access |
| event:0x060 mmcr0:0x0400C000 mmcr1:0x000300032E2E2E2E mmcra:0x00000000 |
| event:0x061 mmcr0:0x0400C000 mmcr1:0x000300032E2E2E2E mmcra:0x00000000 |
| event:0x062 mmcr0:0x0400C000 mmcr1:0x000300032E2E2E2E mmcra:0x00000000 |
| event:0x063 mmcr0:0x0400C000 mmcr1:0x000300032E2E2E2E mmcra:0x00000000 |
| event:0x064 mmcr0:0x0400C000 mmcr1:0x000300032E2E2E2E mmcra:0x00000000 |
| event:0x065 mmcr0:0x0400C000 mmcr1:0x000300032E2E2E2E mmcra:0x00000000 |
| |
| #Group 51 L3 cache data access |
| event:0x06a mmcr0:0x0400C000 mmcr1:0x000300033C3C3C3C mmcra:0x00000000 |
| event:0x06b mmcr0:0x0400C000 mmcr1:0x000300033C3C3C3C mmcra:0x00000000 |
| event:0x06c mmcr0:0x0400C000 mmcr1:0x000300033C3C3C3C mmcra:0x00000000 |
| event:0x06d mmcr0:0x0400C000 mmcr1:0x000300033C3C3C3C mmcra:0x00000000 |
| event:0x06e mmcr0:0x0400C000 mmcr1:0x000300033C3C3C3C mmcra:0x00000000 |
| event:0x06f mmcr0:0x0400C000 mmcr1:0x000300033C3C3C3C mmcra:0x00000000 |
| |
| #Group 52 Instruction source information |
| event:0x070 mmcr0:0x0400C000 mmcr1:0x8000000C1A1A1A0C mmcra:0x00000000 |
| event:0x071 mmcr0:0x0400C000 mmcr1:0x8000000C1A1A1A0C mmcra:0x00000000 |
| event:0x072 mmcr0:0x0400C000 mmcr1:0x8000000C1A1A1A0C mmcra:0x00000000 |
| event:0x073 mmcr0:0x0400C000 mmcr1:0x8000000C1A1A1A0C mmcra:0x00000000 |
| event:0x074 mmcr0:0x0400C000 mmcr1:0x8000000C1A1A1A0C mmcra:0x00000000 |
| event:0x075 mmcr0:0x0400C000 mmcr1:0x8000000C1A1A1A0C mmcra:0x00000000 |
| |
| #Group 54 L2 instruction source information |
| event:0x07a mmcr0:0x0400C000 mmcr1:0x8000000C2C2C2C2C mmcra:0x00000000 |
| event:0x07b mmcr0:0x0400C000 mmcr1:0x8000000C2C2C2C2C mmcra:0x00000000 |
| event:0x07c mmcr0:0x0400C000 mmcr1:0x8000000C2C2C2C2C mmcra:0x00000000 |
| event:0x07d mmcr0:0x0400C000 mmcr1:0x8000000C2C2C2C2C mmcra:0x00000000 |
| event:0x07e mmcr0:0x0400C000 mmcr1:0x8000000C2C2C2C2C mmcra:0x00000000 |
| event:0x07f mmcr0:0x0400C000 mmcr1:0x8000000C2C2C2C2C mmcra:0x00000000 |
| |
| #Group 55 L3 instruction source information |
| event:0x080 mmcr0:0x0400C000 mmcr1:0x8000000C3A3A3A3A mmcra:0x00000000 |
| event:0x081 mmcr0:0x0400C000 mmcr1:0x8000000C3A3A3A3A mmcra:0x00000000 |
| event:0x082 mmcr0:0x0400C000 mmcr1:0x8000000C3A3A3A3A mmcra:0x00000000 |
| event:0x083 mmcr0:0x0400C000 mmcr1:0x8000000C3A3A3A3A mmcra:0x00000000 |
| event:0x084 mmcr0:0x0400C000 mmcr1:0x8000000C3A3A3A3A mmcra:0x00000000 |
| event:0x085 mmcr0:0x0400C000 mmcr1:0x8000000C3A3A3A3A mmcra:0x00000000 |
| |
| #Group 123 Marked TLB and SLB misses |
| event:0x08d mmcr0:0x0400C000 mmcr1:0x0CF00000828A8C8E mmcra:0x00000001 |
| event:0x08e mmcr0:0x0400C000 mmcr1:0x0CF00000828A8C8E mmcra:0x00000001 |
| event:0x08f mmcr0:0x0400C000 mmcr1:0x0CF00000828A8C8E mmcra:0x00000001 |
| |
| #Group 126 Mark unaligned load and store flushes |
| event:0x093 mmcr0:0x0400C000 mmcr1:0x0028000406C62020 mmcra:0x00000001 |
| event:0x094 mmcr0:0x0400C000 mmcr1:0x0028000406C62020 mmcra:0x00000001 |
| event:0x095 mmcr0:0x0400C000 mmcr1:0x0028000406C62020 mmcra:0x00000001 |