Sync with oprofile CVS HEAD from Jan 11, 2011.
There have been a few patches to oprofile for newer ARM architectures
since 0.9.6.
Pruned out irrelevant auto-generated files from the previous dump
so this is closer to being a mirror of the actual oprofile repository.
Change-Id: I889053d30aae433a199a0a18585c66b88ff8de14
diff --git a/events/mips/1004K/events b/events/mips/1004K/events
new file mode 100644
index 0000000..698ca89
--- /dev/null
+++ b/events/mips/1004K/events
@@ -0,0 +1,173 @@
+#
+# MIPS 1004K
+#
+
+# The 1004K CPUs have two performance counters.
+#
+# Even/odd counters are distinguished by setting bit 10 in the event
+# mask. The kernel masks this bit out before writing the control
+# register.
+
+#
+# Events specific to both counters
+#
+event:0x0 counters:0,1 um:zero minimum:500 name:CYCLES : 0-0 Cycles
+event:0x1 counters:0,1 um:zero minimum:500 name:INSTRUCTIONS : 1-0 Instructions completed
+event:0xb counters:0,1 um:zero minimum:500 name:DCACHE_MISSES : 11-0 Data cache misses
+
+#
+# Events specific to counter 0
+#
+event:0x2 counters:0 um:zero minimum:500 name:BRANCH_INSNS : 2-0 Branch instructions (whether completed or mispredicted)
+event:0x3 counters:0 um:zero minimum:500 name:JR_31_INSNS : 3-0 JR $31 (return) instructions executed
+event:0x4 counters:0 um:zero minimum:500 name:JR_NON_31_INSNS : 4-0 JR $xx (not $31) instructions executed (at same cost as a mispredict)
+event:0x5 counters:0 um:zero minimum:500 name:ITLB_ACCESSES : 5-0 Instruction micro-TLB accesses
+event:0x6 counters:0 um:zero minimum:500 name:DTLB_ACCESSES : 6-0 Data micro-TLB accesses
+event:0x7 counters:0 um:zero minimum:500 name:JTLB_INSN_ACCESSES : 7-0 Joint TLB instruction accesses
+event:0x8 counters:0 um:zero minimum:500 name:JTLB_DATA_ACCESSES : 8-0 Joint TLB data (non-instruction) accesses
+event:0x9 counters:0 um:zero minimum:500 name:ICACHE_ACCESSES : 9-0 Instruction cache accesses
+event:0xa counters:0 um:zero minimum:500 name:DCACHE_ACCESSES : 10-0 Data cache accesses
+
+event:0xd counters:0 um:zero minimum:500 name:STORE_MISS_INSNS : 13-0 Cacheable stores that miss in the cache
+event:0xe counters:0 um:zero minimum:500 name:INTEGER_INSNS : 14-0 Integer instructions completed
+event:0xf counters:0 um:zero minimum:500 name:LOAD_INSNS : 15-0 Load instructions completed (including FP)
+event:0x10 counters:0 um:zero minimum:500 name:J_JAL_INSNS : 16-0 J/JAL instructions completed
+event:0x11 counters:0 um:zero minimum:500 name:NO_OPS_INSNS : 17-0 no-ops completed, ie instructions writing $0
+event:0x12 counters:0 um:zero minimum:500 name:ALL_STALLS : 18-0 Stall cycles, including ALU and IFU
+event:0x13 counters:0 um:zero minimum:500 name:SC_INSNS : 19-0 SC instructions completed
+event:0x14 counters:0 um:zero minimum:500 name:PREFETCH_INSNS : 20-0 PREFETCH instructions completed
+event:0x15 counters:0 um:zero minimum:500 name:L2_CACHE_WRITEBACKS : 21-0 L2 cache lines written back to memory
+event:0x16 counters:0 um:zero minimum:500 name:L2_CACHE_MISSES : 22-0 L2 cache accesses that missed in the cache
+event:0x17 counters:0 um:zero minimum:500 name:EXCEPTIONS_TAKEN : 23-0 Exceptions taken
+event:0x18 counters:0 um:zero minimum:500 name:CACHE_FIXUP_CYCLES : 24-0 Cache fixup cycles (specific to the 34K family microarchitecture)
+event:0x19 counters:0 um:zero minimum:500 name:IFU_STALLS : 25-0 IFU stall cycles
+event:0x1a counters:0 um:zero minimum:500 name:DSP_INSNS : 26-0 DSP instructions completed
+
+event:0x1c counters:0 um:zero minimum:500 name:POLICY_EVENTS : 28-0 Implementation specific policy manager events
+event:0x1d counters:0 um:zero minimum:500 name:ISPRAM_EVENTS : 29-0 Implementation specific ISPRAM events
+event:0x1e counters:0 um:zero minimum:500 name:COREEXTEND_EVENTS : 30-0 Implementation specific CorExtend events
+event:0x1f counters:0 um:zero minimum:500 name:YIELD_EVENTS : 31-0 Implementation specific yield events
+
+event:0x20 counters:0 um:zero minimum:500 name:ITC_LOADS : 32-0 ITC Loads
+event:0x21 counters:0 um:zero minimum:500 name:UNCACHED_LOAD_INSNS : 33-0 Uncached load instructions
+event:0x22 counters:0 um:zero minimum:500 name:FORK_INSNS : 34-0 Fork instructions completed
+event:0x23 counters:0 um:zero minimum:500 name:CP2_ARITH_INSNS : 35-0 CP2 arithmetic instructions completed
+event:0x24 counters:0 um:zero minimum:500 name:INTERVENTION_STALLS : 36-0 Cache coherence intervention processing stall cycles
+
+#
+# Count number of cycles (most often ``stall cycles'', ie time lost), not just number of events.
+#
+event:0x25 counters:0 um:zero minimum:500 name:ICACHE_MISS_STALLS : 37-0 Stall cycles due to an instruction cache miss
+
+event:0x27 counters:0 um:zero minimum:500 name:DCACHE_MISS_CYCLES : 39-0 Cycles a data cache miss is outstanding, but not necessarily stalling the pipeline
+event:0x28 counters:0 um:zero minimum:500 name:UNCACHED_STALLS : 40-0 Uncached stall cycles
+event:0x29 counters:0 um:zero minimum:500 name:MDU_STALLS : 41-0 MDU stall cycles
+event:0x2a counters:0 um:zero minimum:500 name:CP2_STALLS : 42-0 CP2 stall cycles
+event:0x2b counters:0 um:zero minimum:500 name:ISPRAM_STALLS : 43-0 ISPRAM stall cycles
+event:0x2c counters:0 um:zero minimum:500 name:CACHE_INSN_STALLS : 44-0 Stall cycless due to CACHE instructions
+event:0x2d counters:0 um:zero minimum:500 name:LOAD_USE_STALLS : 45-0 Load to use stall cycles
+event:0x2e counters:0 um:zero minimum:500 name:INTERLOCK_STALLS : 46-0 Stall cycles due to return data from MFC0, RDHWR, and MFTR instructions
+event:0x2f counters:0 um:zero minimum:500 name:RELAX_STALLS : 47-0 Low power stall cycles (operations) as requested by the policy manager
+
+event:0x30 counters:0 um:zero minimum:500 name:IFU_FB_FULL_REFETCHES : 48-0 Refetches due to cache misses while both fill buffers already allocated
+event:0x31 counters:0 um:zero minimum:500 name:EJTAG_INSN_TRIGGERS : 49-0 EJTAG instruction triggerpoints
+
+#
+#
+# Monitor the state of various FIFO queues in the load/store unit:
+# FSB (``fill/store buffer'')
+# LDQ (``load queue'')
+# WBB (``write-back buffer'')
+# Some count events, others count stall cycles.
+#
+event:0x32 counters:0 um:zero minimum:500 name:FSB_LESS_25_FULL : 50-0 FSB < 25% full
+event:0x33 counters:0 um:zero minimum:500 name:FSB_OVER_50_FULL : 51-0 FSB > 50% full
+event:0x34 counters:0 um:zero minimum:500 name:LDQ_LESS_25_FULL : 52-0 LDQ < 25% full
+event:0x35 counters:0 um:zero minimum:500 name:LDQ_OVER_50_FULL : 53-0 LDQ > 50% full
+event:0x36 counters:0 um:zero minimum:500 name:WBB_LESS_25_FULL : 54-0 WBB < 25% full
+event:0x37 counters:0 um:zero minimum:500 name:WBB_OVER_50_FULL : 55-0 WBB > 50% full
+
+event:0x38 counters:0 um:zero minimum:500 name:INTERVENTION_HIT_COUNT : 56-0 External interventions that hit in the cache
+event:0x39 counters:0 um:zero minimum:500 name:INVALIDATE_INTERVENTION_COUNT : 57-0 External invalidate (i.e. leaving a cache line in the invalid state) interventions
+event:0x3a counters:0 um:zero minimum:500 name:EVICTION_COUNT : 58-0 Cache lines written back due to cache replacement or non-coherent cache operation
+event:0x3b counters:0 um:zero minimum:500 name:MESI_INVAL_COUNT : 59-0 MESI protocol transitions into invalid state
+event:0x3c counters:0 um:zero minimum:500 name:MESI_MODIFIED_COUNT : 60-0 MESI protocol transitions into modified state
+event:0x3d counters:0 um:zero minimum:500 name:SELF_INTERVENTION_LATENCY : 61-0 Latency from miss detection to self intervention
+event:0x3e counters:0 um:zero minimum:500 name:READ_RESPONSE_LATENCY : 62-0 Read latency from miss detection until critical dword of response is returned
+
+#
+# Events specific to counter 1
+#
+event:0x402 counters:1 um:zero minimum:500 name:MISPREDICTED_BRANCH_INSNS : 2-1 Branch mispredictions
+event:0x403 counters:1 um:zero minimum:500 name:JR_31_MISPREDICTIONS : 3-1 JR $31 mispredictions
+event:0x404 counters:1 um:zero minimum:500 name:JR_31_NO_PREDICTIONS : 4-1 JR $31 not predicted (stack mismatch).
+event:0x405 counters:1 um:zero minimum:500 name:ITLB_MISSES : 5-1 Instruction micro-TLB misses
+event:0x406 counters:1 um:zero minimum:500 name:DTLB_MISSES : 6-1 Data micro-TLB misses
+event:0x407 counters:1 um:zero minimum:500 name:JTLB_INSN_MISSES : 7-1 Joint TLB instruction misses
+event:0x408 counters:1 um:zero minimum:500 name:JTLB_DATA_MISSES : 8-1 Joint TLB data (non-instruction) misses
+event:0x409 counters:1 um:zero minimum:500 name:ICACHE_MISSES : 9-1 Instruction cache misses
+event:0x40a counters:1 um:zero minimum:500 name:DCACHE_WRITEBACKS : 10-1 Data cache lines written back to memory
+
+event:0x40d counters:1 um:zero minimum:500 name:LOAD_MISS_INSNS : 13-1 Cacheable load instructions that miss in the cache
+event:0x40e counters:1 um:zero minimum:500 name:FPU_INSNS : 14-1 FPU instructions completed (not including loads/stores)
+event:0x40f counters:1 um:zero minimum:500 name:STORE_INSNS : 15-1 Stores completed (including FP)
+event:0x410 counters:1 um:zero minimum:500 name:MIPS16_INSNS : 16-1 MIPS16 instructions completed
+event:0x411 counters:1 um:zero minimum:500 name:INT_MUL_DIV_INSNS : 17-1 Integer multiply/divide instructions completed
+event:0x412 counters:1 um:zero minimum:500 name:REPLAYED_INSNS : 18-1 Replayed instructions
+event:0x413 counters:1 um:zero minimum:500 name:SC_INSNS_FAILED : 19-1 SC instructions completed, but store failed (because the link bit had been cleared)
+event:0x414 counters:1 um:zero minimum:500 name:CACHE_HIT_PREFETCH_INSNS : 20-1 PREFETCH instructions completed with cache hit
+event:0x415 counters:1 um:zero minimum:500 name:L2_CACHE_ACCESSES : 21-1 Accesses to the L2 cache
+event:0x416 counters:1 um:zero minimum:500 name:L2_CACHE_SINGLE_BIT_ERRORS : 22-1 Single bit errors corrected in L2
+event:0x417 counters:1 um:zero minimum:500 name:SINGLE_THREADED_CYCLES : 23-1 Cycles while one and only one TC is eligible for scheduling
+event:0x418 counters:1 um:zero minimum:500 name:REFETCHED_INSNS : 24-1 Replayed instructions sent back to IFU to be refetched
+event:0x419 counters:1 um:zero minimum:500 name:ALU_STALLS : 25-1 ALU stall cycles
+event:0x41a counters:1 um:zero minimum:500 name:ALU_DSP_SATURATION_INSNS : 26-1 ALU-DSP saturation instructions
+event:0x41b counters:1 um:zero minimum:500 name:MDU_DSP_SATURATION_INSNS : 27-1 MDU-DSP saturation instructions
+
+event:0x41c counters:1 um:zero minimum:500 name:CP2_EVENTS : 28-1 Implementation specific CP2 events
+event:0x41d counters:1 um:zero minimum:500 name:DSPRAM_EVENTS : 29-1 Implementation specific DSPRAM events
+
+event:0x41f counters:1 um:zero minimum:500 name:ITC_EVENT : 31-1 Implementation specific yield event
+
+event:0x421 counters:1 um:zero minimum:500 name:UNCACHED_STORE_INSNS : 33-1 Uncached store instructions
+event:0x423 counters:1 um:zero minimum:500 name:CP2_TO_FROM_INSNS : 35-1 CP2 to/from instructions (moves, control, loads, stores)
+event:0x424 counters:1 um:zero minimum:500 name:INTERVENTION_MISS_STALLS : 36-1 Cache coherence intervention processing stall cycles due to an earlier miss
+
+#
+# Count number of cycles (most often ``stall cycles'', ie time lost), not just number of events.
+#
+event:0x425 counters:1 um:zero minimum:500 name:DCACHE_MISS_STALLS : 37-1 Stall cycles due to a data cache miss
+event:0x426 counters:1 um:zero minimum:500 name:FSB_INDEX_CONFLICT_STALLS : 38-1 FSB (fill/store buffer) index conflict stall cycles
+event:0x427 counters:1 um:zero minimum:500 name:L2_CACHE_MISS_CYCLES : 39-1 Cycles a L2 miss is outstanding, but not necessarily stalling the pipeline
+event:0x428 counters:1 um:zero minimum:500 name:ITC_STALLS : 40-1 ITC stall cycles
+event:0x429 counters:1 um:zero minimum:500 name:FPU_STALLS : 41-1 FPU stall cycles
+event:0x42a counters:1 um:zero minimum:500 name:COREEXTEND_STALLS : 42-1 CorExtend stall cycles
+event:0x42b counters:1 um:zero minimum:500 name:DSPRAM_STALLS : 43-1 DSPRAM stall cycles
+
+event:0x42d counters:1 um:zero minimum:500 name:ALU_TO_AGEN_STALLS : 45-1 ALU to AGEN stall cycles
+event:0x42e counters:1 um:zero minimum:500 name:MISPREDICTION_STALLS : 46-1 Branch mispredict stall cycles
+
+event:0x430 counters:1 um:zero minimum:500 name:FB_ENTRY_ALLOCATED_CYCLES : 48-1 Cycles while at least one IFU fill buffer is allocated
+event:0x431 counters:1 um:zero minimum:500 name:EJTAG_DATA_TRIGGERS : 49-1 EJTAG Data triggerpoints
+
+#
+# Monitor the state of various FIFO queues in the load/store unit:
+# FSB (``fill/store buffer'')
+# LDQ (``load queue'')
+# WBB (``write-back buffer'')
+# Some count events, others count stall cycles.
+#
+event:0x432 counters:1 um:zero minimum:500 name:FSB_25_50_FULL : 50-1 FSB 25-50% full
+event:0x433 counters:1 um:zero minimum:500 name:FSB_FULL_STALLS : 51-1 FSB full pipeline stall cycles
+event:0x434 counters:1 um:zero minimum:500 name:LDQ_25_50_FULL : 52-1 LDQ 25-50% full
+event:0x435 counters:1 um:zero minimum:500 name:LDQ_FULL_STALLS : 53-1 LDQ full pipeline stall cycles
+event:0x436 counters:1 um:zero minimum:500 name:WBB_25_50_FULL : 54-1 WBB 25-50% full
+event:0x437 counters:1 um:zero minimum:500 name:WBB_FULL_STALLS : 55-1 WBB full pipeline stall cycles
+
+event:0x438 counters:1 um:zero minimum:500 name:INTERVENTION_COUNT : 56-1 External interventions
+event:0x439 counters:1 um:zero minimum:500 name:INVALIDATE_INTERVENTION_HIT_COUNT : 57-1 External invalidate interventions that hit in the cache
+event:0x43a counters:1 um:zero minimum:500 name:WRITEBACK_COUNT : 58-1 Cache lines written back due to cache replacement or any cache operation (non-coherent, self, or external coherent)
+event:0x43b counters:1 um:zero minimum:500 name:MESI_EXCLUSIVE_COUNT : 59-1 MESI protocol transitions into exclusive state
+event:0x43c counters:1 um:zero minimum:500 name:MESI_SHARED_COUNT : 60-1 MESI protocol transitions into shared state
+event:0x43d counters:1 um:zero minimum:500 name:SELF_INTERVENTION_COUNT : 61-1 Self intervention requests on miss detection
+event:0x43e counters:1 um:zero minimum:500 name:READ_RESPONSE_COUNT : 62-1 Read requests on miss detection
diff --git a/events/mips/1004K/unit_masks b/events/mips/1004K/unit_masks
new file mode 100644
index 0000000..cbba0f9
--- /dev/null
+++ b/events/mips/1004K/unit_masks
@@ -0,0 +1,5 @@
+#
+# MIPS 1004K possible unit masks
+#
+name:zero type:mandatory default:0x0
+ 0x0 No unit mask
diff --git a/events/mips/20K/events b/events/mips/20K/events
new file mode 100644
index 0000000..25428e9
--- /dev/null
+++ b/events/mips/20K/events
@@ -0,0 +1,21 @@
+#
+# MIPS 20K
+#
+# The 20K supports only one performance counter.
+#
+event:0x0 counters:0 um:zero minimum:500 name:CYCLES : CPU cycles
+event:0x1 counters:0 um:zero minimum:500 name:INSN_ISSUED : Dispatched/issued instructions
+event:0x2 counters:0 um:zero minimum:500 name:FETCH_GROUPS : Fetch groups entering CPU execution pipes
+event:0x3 counters:0 um:zero minimum:500 name:FP_INSNS_COMPLETED : Instructions completed in FPU datapath (computational event:instructions only)
+event:0x4 counters:0 um:zero minimum:500 name:TLB_REFILLS_TAKEN : Taken TLB refill exceptions
+event:0x5 counters:0 um:zero minimum:500 name:BRANCHES_MISSPREDICTED : Branches that mispredicted before completing execution
+event:0x6 counters:0 um:zero minimum:500 name:BRANCHES_COMPLETED : Branches that completed execution
+event:0x7 counters:0 um:zero minimum:500 name:JTLB_EXCEPTIONS : Taken Joint-TLB exceptions
+event:0x8 counters:0 um:zero minimum:500 name:REPLAY_DUE_TO_LOAD_DEPENDENT_SPEC_DISPATCH : Replays due to load-dependent speculative dispatch
+event:0x9 counters:0 um:zero minimum:500 name:INSN_REQ_FROM_IFU_TO_BIU : Instruction requests from the IFU to the BIU
+event:0xa counters:0 um:zero minimum:500 name:FPU_EXCEPTIONS_TAKEN : Taken FPU exceptions
+event:0xb counters:0 um:zero minimum:500 name:REPLAYS : Total number of LSU requested replays, Load-dependent speculative dispatch or FPU exception prediction replays.
+event:0xc counters:0 um:zero minimum:500 name:RPS_MISSPREDICTS : JR instructions that mispredicted using the Return Prediction Stack (RPS)
+event:0xd counters:0 um:zero minimum:500 name:JR_INSNS_COMPLETED : JR instruction that completed execution
+event:0xe counters:0 um:zero minimum:500 name:LSU_REPLAYS : LSU requested replays
+event:0xf counters:0 um:zero minimum:500 name:INSNS_COMPLETED : Instruction that completed execution (with or without exception)
diff --git a/events/mips/20K/unit_masks b/events/mips/20K/unit_masks
new file mode 100644
index 0000000..7571a6b
--- /dev/null
+++ b/events/mips/20K/unit_masks
@@ -0,0 +1,5 @@
+#
+# MIPS 20Kc possible unit masks
+#
+name:zero type:mandatory default:0x0
+ 0x0 No unit mask
diff --git a/events/mips/24K/events b/events/mips/24K/events
new file mode 100644
index 0000000..58b0e17
--- /dev/null
+++ b/events/mips/24K/events
@@ -0,0 +1,144 @@
+#
+# MIPS 24K
+#
+
+# The 24K CPUs have two performance counters.
+#
+# Even/odd counters are distinguished by setting bit 10 in the event
+# mask. The kernel masks this bit out before writing the control
+# register.
+
+#
+# Events specific to both counters
+#
+event:0x0 counters:0,1 um:zero minimum:500 name:CYCLES : 0-0 Cycles
+event:0x1 counters:0,1 um:zero minimum:500 name:INSTRUCTIONS : 1-0 Instructions completed
+event:0xb counters:0,1 um:zero minimum:500 name:DCACHE_MISSES : 11-0 Data cache misses
+
+#
+# Events specific to counter 0
+#
+event:0x2 counters:0 um:zero minimum:500 name:BRANCH_INSNS : 2-0 Branch instructions (whether completed or mispredicted)
+event:0x3 counters:0 um:zero minimum:500 name:JR_31_INSNS : 3-0 JR $31 (return) instructions executed
+event:0x4 counters:0 um:zero minimum:500 name:JR_NON_31_INSNS : 4-0 JR $xx (not $31) instructions executed (at same cost as a mispredict)
+event:0x5 counters:0 um:zero minimum:500 name:ITLB_ACCESSES : 5-0 Instruction micro-TLB accesses
+event:0x6 counters:0 um:zero minimum:500 name:DTLB_ACCESSES : 6-0 Data micro-TLB accesses
+event:0x7 counters:0 um:zero minimum:500 name:JTLB_INSN_ACCESSES : 7-0 Joint TLB instruction accesses
+event:0x8 counters:0 um:zero minimum:500 name:JTLB_DATA_ACCESSES : 8-0 Joint TLB data (non-instruction) accesses
+event:0x9 counters:0 um:zero minimum:500 name:ICACHE_ACCESSES : 9-0 Instruction cache accesses
+event:0xa counters:0 um:zero minimum:500 name:DCACHE_ACCESSES : 10-0 Data cache accesses
+
+event:0xd counters:0 um:zero minimum:500 name:STORE_MISS_INSNS : 13-0 Cacheable stores that miss in the cache
+event:0xe counters:0 um:zero minimum:500 name:INTEGER_INSNS : 14-0 Integer instructions completed
+event:0xf counters:0 um:zero minimum:500 name:LOAD_INSNS : 15-0 Load instructions completed (including FP)
+event:0x10 counters:0 um:zero minimum:500 name:J_JAL_INSNS : 16-0 J/JAL instructions completed
+event:0x11 counters:0 um:zero minimum:500 name:NO_OPS_INSNS : 17-0 no-ops completed, ie instructions writing $0
+event:0x12 counters:0 um:zero minimum:500 name:ALL_STALLS : 18-0 Stall cycles, including ALU and IFU
+event:0x13 counters:0 um:zero minimum:500 name:SC_INSNS : 19-0 SC instructions completed
+event:0x14 counters:0 um:zero minimum:500 name:PREFETCH_INSNS : 20-0 PREFETCH instructions completed
+event:0x15 counters:0 um:zero minimum:500 name:L2_CACHE_WRITEBACKS : 21-0 L2 cache lines written back to memory
+event:0x16 counters:0 um:zero minimum:500 name:L2_CACHE_MISSES : 22-0 L2 cache accesses that missed in the cache
+event:0x17 counters:0 um:zero minimum:500 name:EXCEPTIONS_TAKEN : 23-0 Exceptions taken
+event:0x18 counters:0 um:zero minimum:500 name:CACHE_FIXUP_CYCLES : 24-0 Cache fixup cycles (specific to the 24K family microarchitecture)
+event:0x19 counters:0 um:zero minimum:500 name:IFU_STALLS : 25-0 IFU stall cycles
+event:0x1a counters:0 um:zero minimum:500 name:DSP_INSNS : 26-0 DSP instructions completed
+
+event:0x1d counters:0 um:zero minimum:500 name:ISPRAM_EVENTS : 29-0 Implementation specific ISPRAM events
+event:0x1e counters:0 um:zero minimum:500 name:COREEXTEND_EVENTS : 30-0 Implementation specific CorExtend events
+
+event:0x21 counters:0 um:zero minimum:500 name:UNCACHED_LOAD_INSNS : 33-0 Uncached load instructions
+event:0x23 counters:0 um:zero minimum:500 name:CP2_ARITH_INSNS : 35-0 CP2 arithmetic instructions completed
+
+#
+# Count number of cycles (most often ``stall cycles'', ie time lost), not just number of events.
+#
+event:0x25 counters:0 um:zero minimum:500 name:ICACHE_MISS_STALLS : 37-0 Stall cycles due to an instruction cache miss
+event:0x26 counters:0 um:zero minimum:500 name:SYNC_STALLS : 38-0 SYNC stall cycles
+event:0x27 counters:0 um:zero minimum:500 name:DCACHE_MISS_CYCLES : 39-0 Cycles a data cache miss is outstanding, but not necessarily stalling the pipeline
+event:0x28 counters:0 um:zero minimum:500 name:UNCACHED_STALLS : 40-0 Uncached stall cycles
+event:0x29 counters:0 um:zero minimum:500 name:MDU_STALLS : 41-0 MDU stall cycles
+event:0x2a counters:0 um:zero minimum:500 name:CP2_STALLS : 42-0 CP2 stall cycles
+event:0x2b counters:0 um:zero minimum:500 name:ISPRAM_STALLS : 43-0 ISPRAM stall cycles
+event:0x2c counters:0 um:zero minimum:500 name:CACHE_INSN_STALLS : 44-0 Stall cycless due to CACHE instructions
+event:0x2d counters:0 um:zero minimum:500 name:LOAD_USE_STALLS : 45-0 Load to use stall cycles
+event:0x2e counters:0 um:zero minimum:500 name:INTERLOCK_STALLS : 46-0 Stall cycles due to return data from MFC0 and RDHWR instructions
+
+event:0x30 counters:0 um:zero minimum:500 name:IFU_FB_FULL_REFETCHES : 48-0 Refetches due to cache misses while both fill buffers already allocated
+event:0x31 counters:0 um:zero minimum:500 name:EJTAG_INSN_TRIGGERS : 49-0 EJTAG instruction triggerpoints
+
+#
+#
+# Monitor the state of various FIFO queues in the load/store unit:
+# FSB (``fill/store buffer'')
+# LDQ (``load queue'')
+# WBB (``write-back buffer'')
+#
+event:0x32 counters:0 um:zero minimum:500 name:FSB_LESS_25_FULL : 50-0 FSB < 25% full
+event:0x33 counters:0 um:zero minimum:500 name:FSB_OVER_50_FULL : 51-0 FSB > 50% full
+event:0x34 counters:0 um:zero minimum:500 name:LDQ_LESS_25_FULL : 52-0 LDQ < 25% full
+event:0x35 counters:0 um:zero minimum:500 name:LDQ_OVER_50_FULL : 53-0 LDQ > 50% full
+event:0x36 counters:0 um:zero minimum:500 name:WBB_LESS_25_FULL : 54-0 WBB < 25% full
+event:0x37 counters:0 um:zero minimum:500 name:WBB_OVER_50_FULL : 55-0 WBB > 50% full
+
+#
+# Events specific to counter 1
+#
+event:0x402 counters:1 um:zero minimum:500 name:MISPREDICTED_BRANCH_INSNS : 2-1 Branch mispredictions
+event:0x403 counters:1 um:zero minimum:500 name:JR_31_MISPREDICTIONS : 3-1 JR $31 mispredictions
+event:0x404 counters:1 um:zero minimum:500 name:JR_31_NO_PREDICTIONS : 4-1 JR $31 not predicted (stack mismatch).
+event:0x405 counters:1 um:zero minimum:500 name:ITLB_MISSES : 5-1 Instruction micro-TLB misses
+event:0x406 counters:1 um:zero minimum:500 name:DTLB_MISSES : 6-1 Data micro-TLB misses
+event:0x407 counters:1 um:zero minimum:500 name:JTLB_INSN_MISSES : 7-1 Joint TLB instruction misses
+event:0x408 counters:1 um:zero minimum:500 name:JTLB_DATA_MISSES : 8-1 Joint TLB data (non-instruction) misses
+event:0x409 counters:1 um:zero minimum:500 name:ICACHE_MISSES : 9-1 Instruction cache misses
+event:0x40a counters:1 um:zero minimum:500 name:DCACHE_WRITEBACKS : 10-1 Data cache lines written back to memory
+event:0x40d counters:1 um:zero minimum:500 name:LOAD_MISS_INSNS : 13-1 Cacheable load instructions that miss in the cache
+event:0x40e counters:1 um:zero minimum:500 name:FPU_INSNS : 14-1 FPU instructions completed (not including loads/stores)
+event:0x40f counters:1 um:zero minimum:500 name:STORE_INSNS : 15-1 Stores completed (including FP)
+event:0x410 counters:1 um:zero minimum:500 name:MIPS16_INSNS : 16-1 MIPS16 instructions completed
+event:0x411 counters:1 um:zero minimum:500 name:INT_MUL_DIV_INSNS : 17-1 Integer multiply/divide instructions completed
+event:0x412 counters:1 um:zero minimum:500 name:REPLAYED_INSNS : 18-1 Replayed instructions
+event:0x413 counters:1 um:zero minimum:500 name:SC_INSNS_FAILED : 19-1 SC instructions completed, but store failed (because the link bit had been cleared)
+event:0x414 counters:1 um:zero minimum:500 name:CACHE_HIT_PREFETCH_INSNS : 20-1 PREFETCH instructions completed with cache hit
+event:0x415 counters:1 um:zero minimum:500 name:L2_CACHE_ACCESSES : 21-1 Accesses to the L2 cache
+event:0x416 counters:1 um:zero minimum:500 name:L2_CACHE_SINGLE_BIT_ERRORS : 22-1 Single bit errors corrected in L2
+
+event:0x419 counters:1 um:zero minimum:500 name:ALU_STALLS : 25-1 ALU stall cycles
+event:0x41a counters:1 um:zero minimum:500 name:ALU_DSP_SATURATION_INSNS : 26-1 ALU-DSP saturation instructions
+event:0x41b counters:1 um:zero minimum:500 name:MDU_DSP_SATURATION_INSNS : 27-1 MDU-DSP saturation instructions
+
+event:0x41c counters:1 um:zero minimum:500 name:CP2_EVENTS : 28-1 Implementation specific CP2 events
+event:0x41d counters:1 um:zero minimum:500 name:DSPRAM_EVENTS : 29-1 Implementation specific DSPRAM events
+
+event:0x421 counters:1 um:zero minimum:500 name:UNCACHED_STORE_INSNS : 33-1 Uncached store instructions
+event:0x423 counters:1 um:zero minimum:500 name:CP2_TO_FROM_INSNS : 35-1 CP2 to/from instructions (moves, control, loads, stores)
+
+#
+# Count number of cycles (most often ``stall cycles'', ie time lost), not just number of events.
+#
+event:0x425 counters:1 um:zero minimum:500 name:DCACHE_MISS_STALLS : 37-1 Stall cycles due to a data cache miss
+event:0x426 counters:1 um:zero minimum:500 name:FSB_INDEX_CONFLICT_STALLS : 38-1 FSB (fill/store buffer) index conflict stall cycles
+event:0x427 counters:1 um:zero minimum:500 name:L2_CACHE_MISS_CYCLES : 39-1 Cycles a L2 miss is outstanding, but not necessarily stalling the pipeline
+event:0x429 counters:1 um:zero minimum:500 name:FPU_STALLS : 41-1 FPU stall cycles
+event:0x42a counters:1 um:zero minimum:500 name:COREEXTEND_STALLS : 42-1 CorExtend stall cycles
+event:0x42b counters:1 um:zero minimum:500 name:DSPRAM_STALLS : 43-1 DSPRAM stall cycles
+
+event:0x42d counters:1 um:zero minimum:500 name:ALU_TO_AGEN_STALLS : 45-1 ALU to AGEN stall cycles
+event:0x42e counters:1 um:zero minimum:500 name:MISPREDICTION_STALLS : 46-1 Branch mispredict stall cycles
+
+event:0x430 counters:1 um:zero minimum:500 name:FB_ENTRY_ALLOCATED_CYCLES : 48-1 Cycles while at least one IFU fill buffer is allocated
+event:0x431 counters:1 um:zero minimum:500 name:EJTAG_DATA_TRIGGERS : 49-1 EJTAG Data triggerpoints
+
+#
+# Monitor the state of various FIFO queues in the load/store unit:
+# FSB (``fill/store buffer'')
+# LDQ (``load queue'')
+# WBB (``write-back buffer'')
+# Some count events, others count stall cycles.
+#
+event:0x432 counters:1 um:zero minimum:500 name:FSB_25_50_FULL : 50-1 FSB 25-50% full
+event:0x433 counters:1 um:zero minimum:500 name:FSB_FULL_STALLS : 51-1 FSB full pipeline stall cycles
+event:0x434 counters:1 um:zero minimum:500 name:LDQ_25_50_FULL : 52-1 LDQ 25-50% full
+event:0x435 counters:1 um:zero minimum:500 name:LDQ_FULL_STALLS : 53-1 LDQ full pipeline stall cycles
+event:0x436 counters:1 um:zero minimum:500 name:WBB_25_50_FULL : 54-1 WBB 25-50% full
+event:0x437 counters:1 um:zero minimum:500 name:WBB_FULL_STALLS : 55-1 WBB full pipeline stall cycles
diff --git a/events/mips/24K/unit_masks b/events/mips/24K/unit_masks
new file mode 100644
index 0000000..70d028a
--- /dev/null
+++ b/events/mips/24K/unit_masks
@@ -0,0 +1,5 @@
+#
+# MIPS 24K possible unit masks
+#
+name:zero type:mandatory default:0x0
+ 0x0 No unit mask
diff --git a/events/mips/25K/events b/events/mips/25K/events
new file mode 100644
index 0000000..4000678
--- /dev/null
+++ b/events/mips/25K/events
@@ -0,0 +1,81 @@
+#
+# MIPS 25Kf
+#
+# The 25Kf has two performance counters
+#
+event:0x0 counters:0,1 um:zero minimum:500 name:CYCLES : CPU cycles
+event:0x1 counters:0,1 um:zero minimum:500 name:INSN_ISSUED : Dispatched/issued instructions
+event:0x2 counters:0,1 um:zero minimum:500 name:FP_INSNS_ISSUED : FPU instructions issued
+event:0x3 counters:0,1 um:zero minimum:500 name:INT_INSNS_ISSUED : Integer instructions issued
+event:0x4 counters:0,1 um:zero minimum:500 name:LOAD_INSNS_ISSUED : Load instructions issued
+event:0x5 counters:0,1 um:zero minimum:500 name:STORE_INSNS_ISSUED : Store instructions issued
+event:0x6 counters:0,1 um:zero minimum:500 name:BRANCHES_JUMPS_ISSUED : Branch/Jump instructions issued
+event:0x7 counters:0,1 um:zero minimum:500 name:DUAL_ISSUED_PAIRS : Dual-issued pairs
+event:0x8 counters:0,1 um:zero minimum:500 name:INSNS_COMPLETE : Instruction that completed execution (with or without exception)
+event:0x9 counters:0,1 um:zero minimum:500 name:FETCH_GROUPS_IN_PIPE : Fetch groups entering CPU execution pipes
+
+#
+# FPU:
+#
+event:0xa counters:0,1 um:zero minimum:500 name:INSN_FP_DATAPATH_COMPLETED : Instructions completed in FPU datapath (computational instructions only)
+event:0xb counters:0,1 um:zero minimum:500 name:FP_EXCEPTIONS_TAKEN : Taken FPU exceptions
+event:0xc counters:0,1 um:zero minimum:500 name:FP_EXCEPTION_PREDICTED : Predicted FPU exceptions
+
+#
+# Branch/Jump Prediction:
+#
+event:0xd counters:0,1 um:zero minimum:500 name:BRANCHES_MISSPREDICTED : Branches that mispredicted before completing execution
+event:0xe counters:0,1 um:zero minimum:500 name:BRANCHES_COMPLETED : Branches that completed execution
+event:0xf counters:0,1 um:zero minimum:500 name:JR_RPD_MISSPREDICTED : JR instructions that mispredicted using the Return Prediction Stack
+event:0x10 counters:0,1 um:zero minimum:500 name:JR_COMPLETED : JR instruction that completed execution
+
+#
+# Memory Management:
+#
+event:0x11 counters:0,1 um:zero minimum:500 name:UTLB_MISSES : U-TLB misses
+event:0x12 counters:0,1 um:zero minimum:500 name:JTLB_MISSES_IFETCH : Raw count of Joint-TLB misses for instruction fetch
+event:0x13 counters:0,1 um:zero minimum:500 name:JTLB_MISSES_LOADS_STORES : Raw count of Joint-TLB misses for loads/stores
+event:0x14 counters:0,1 um:zero minimum:500 name:JTLB_EXCEPTIONS : Refill, Invalid and Modified TLB exceptions
+
+#
+# Machine Check
+#
+event:0x15 counters:0,1 um:zero minimum:500 name:JTLB_IFETCH_REFILL_EXCEPTIONS : Joint-TLB refill exceptions due to instruction fetch
+event:0x16 counters:0,1 um:zero minimum:500 name:JTLB_DATA_ACCESS_REFILL_EXCEPTIONS : Joint-TLB refill exceptions due to data access
+event:0x17 counters:0,1 um:zero minimum:500 name:JTLB_REFILL_EXCEPTIONS : total Joint-TLB Instruction exceptions (refill)
+
+#
+# I-Cache Efficiency:
+#
+event:0x18 counters:0,1 um:zero minimum:500 name:INSNS_FETCHED_FROM_ICACHE : Total number of instructions fetched from the I-Cache
+event:0x19 counters:0,1 um:zero minimum:500 name:INSN_REQ_FROM_IFU_BIU : instruction requests from the IFU to the BIU
+event:0x1a counters:0,1 um:zero minimum:500 name:ICACHE_MISSES : I-Cache miss
+
+#
+# D-Cache Efficiency:
+#
+event:0x1b counters:0,1 um:zero minimum:500 name:DCACHE_MISSES : D-Cache miss
+event:0x1c counters:0,1 um:zero minimum:500 name:DCACHE_WRITEBACKS : D-Cache number of write-backs
+event:0x1d counters:0,1 um:zero minimum:500 name:CACHEABLE_DCACHE_REQUEST : number of cacheable requests to D-Cache
+
+#
+# Level 2 Cache Efficiency:
+#
+event:0x1e counters:0,1 um:zero minimum:500 name:L2_MISSES : L2 Cache miss
+event:0x1f counters:0,1 um:zero minimum:500 name:L2_WBACKS : L2 Cache number of write-backs
+event:0x20 counters:0,1 um:zero minimum:500 name:CACHEABLE_L2_REQS : Number of cacheable requests to L2
+
+#
+# Replays:
+#
+event:0x21 counters:0,1 um:zero minimum:500 name:REPLAYS_LSU_LOAD_DEP_FPU : LSU requested replays, load-dependent speculative dispatch, FPU exception prediction
+event:0x22 counters:0,1 um:zero minimum:500 name:LSU_REQ_REPLAYS : LSU requested replays
+event:0x23 counters:0,1 um:zero minimum:500 name:REPLAYS_LOAD_DEP_DISPATCH : replays due to load-dependent speculative dispatch
+event:0x24 counters:0,1 um:zero minimum:500 name:REPLAYS_WBB_FULL : replays due to WBB full
+event:0x25 counters:0,1 um:zero minimum:500 name:FSB_FULL_REPLAYS : replays due to FSB full
+
+#
+# Misc:
+#
+event:0x26 counters:0,1 um:zero minimum:500 name:ICACHE_PSEUDO_HITS : I-Cache pseudo-hits
+event:0x27 counters:0,1 um:zero minimum:500 name:LOAD_STORE_ISSUED : Load/store instructions issued
diff --git a/events/mips/25K/unit_masks b/events/mips/25K/unit_masks
new file mode 100644
index 0000000..0854781
--- /dev/null
+++ b/events/mips/25K/unit_masks
@@ -0,0 +1,5 @@
+#
+# MIPS 25Kf possible unit masks
+#
+name:zero type:mandatory default:0x0
+ 0x0 No unit mask
diff --git a/events/mips/34K/events b/events/mips/34K/events
new file mode 100644
index 0000000..d161556
--- /dev/null
+++ b/events/mips/34K/events
@@ -0,0 +1,158 @@
+#
+# MIPS 34K
+#
+
+# The 34K CPUs have two performance counters.
+#
+# Even/odd counters are distinguished by setting bit 10 in the event
+# mask. The kernel masks this bit out before writing the control
+# register.
+
+#
+# Events specific to both counters
+#
+event:0x0 counters:0,1 um:zero minimum:500 name:CYCLES : 0-0 Cycles
+event:0x1 counters:0,1 um:zero minimum:500 name:INSTRUCTIONS : 1-0 Instructions completed
+event:0xb counters:0,1 um:zero minimum:500 name:DCACHE_MISSES : 11-0 Data cache misses
+
+#
+# Events specific to counter 0
+#
+event:0x2 counters:0 um:zero minimum:500 name:BRANCH_INSNS : 2-0 Branch instructions (whether completed or mispredicted)
+event:0x3 counters:0 um:zero minimum:500 name:JR_31_INSNS : 3-0 JR $31 (return) instructions executed
+event:0x4 counters:0 um:zero minimum:500 name:JR_NON_31_INSNS : 4-0 JR $xx (not $31) instructions executed (at same cost as a mispredict)
+event:0x5 counters:0 um:zero minimum:500 name:ITLB_ACCESSES : 5-0 Instruction micro-TLB accesses
+event:0x6 counters:0 um:zero minimum:500 name:DTLB_ACCESSES : 6-0 Data micro-TLB accesses
+event:0x7 counters:0 um:zero minimum:500 name:JTLB_INSN_ACCESSES : 7-0 Joint TLB instruction accesses
+event:0x8 counters:0 um:zero minimum:500 name:JTLB_DATA_ACCESSES : 8-0 Joint TLB data (non-instruction) accesses
+event:0x9 counters:0 um:zero minimum:500 name:ICACHE_ACCESSES : 9-0 Instruction cache accesses
+event:0xa counters:0 um:zero minimum:500 name:DCACHE_ACCESSES : 10-0 Data cache accesses
+
+event:0xd counters:0 um:zero minimum:500 name:STORE_MISS_INSNS : 13-0 Cacheable stores that miss in the cache
+event:0xe counters:0 um:zero minimum:500 name:INTEGER_INSNS : 14-0 Integer instructions completed
+event:0xf counters:0 um:zero minimum:500 name:LOAD_INSNS : 15-0 Load instructions completed (including FP)
+event:0x10 counters:0 um:zero minimum:500 name:J_JAL_INSNS : 16-0 J/JAL instructions completed
+event:0x11 counters:0 um:zero minimum:500 name:NO_OPS_INSNS : 17-0 no-ops completed, ie instructions writing $0
+event:0x12 counters:0 um:zero minimum:500 name:ALL_STALLS : 18-0 Stall cycles, including ALU and IFU
+event:0x13 counters:0 um:zero minimum:500 name:SC_INSNS : 19-0 SC instructions completed
+event:0x14 counters:0 um:zero minimum:500 name:PREFETCH_INSNS : 20-0 PREFETCH instructions completed
+event:0x15 counters:0 um:zero minimum:500 name:L2_CACHE_WRITEBACKS : 21-0 L2 cache lines written back to memory
+event:0x16 counters:0 um:zero minimum:500 name:L2_CACHE_MISSES : 22-0 L2 cache accesses that missed in the cache
+event:0x17 counters:0 um:zero minimum:500 name:EXCEPTIONS_TAKEN : 23-0 Exceptions taken
+event:0x18 counters:0 um:zero minimum:500 name:CACHE_FIXUP_CYCLES : 24-0 Cache fixup cycles (specific to the 34K family microarchitecture)
+event:0x19 counters:0 um:zero minimum:500 name:IFU_STALLS : 25-0 IFU stall cycles
+event:0x1a counters:0 um:zero minimum:500 name:DSP_INSNS : 26-0 DSP instructions completed
+
+event:0x1c counters:0 um:zero minimum:500 name:POLICY_EVENTS : 28-0 Implementation specific policy manager events
+event:0x1d counters:0 um:zero minimum:500 name:ISPRAM_EVENTS : 29-0 Implementation specific ISPRAM events
+event:0x1e counters:0 um:zero minimum:500 name:COREEXTEND_EVENTS : 30-0 Implementation specific CorExtend events
+event:0x1f counters:0 um:zero minimum:500 name:YIELD_EVENTS : 31-0 Implementation specific yield events
+
+event:0x20 counters:0 um:zero minimum:500 name:ITC_LOADS : 32-0 ITC Loads
+event:0x21 counters:0 um:zero minimum:500 name:UNCACHED_LOAD_INSNS : 33-0 Uncached load instructions
+event:0x22 counters:0 um:zero minimum:500 name:FORK_INSNS : 34-0 Fork instructions completed
+event:0x23 counters:0 um:zero minimum:500 name:CP2_ARITH_INSNS : 35-0 CP2 arithmetic instructions completed
+
+#
+# Count number of cycles (most often ``stall cycles'', ie time lost), not just number of events.
+#
+event:0x25 counters:0 um:zero minimum:500 name:ICACHE_MISS_STALLS : 37-0 Stall cycles due to an instruction cache miss
+
+event:0x27 counters:0 um:zero minimum:500 name:DCACHE_MISS_CYCLES : 39-0 Cycles a data cache miss is outstanding, but not necessarily stalling the pipeline
+event:0x28 counters:0 um:zero minimum:500 name:UNCACHED_STALLS : 40-0 Uncached stall cycles
+event:0x29 counters:0 um:zero minimum:500 name:MDU_STALLS : 41-0 MDU stall cycles
+event:0x2a counters:0 um:zero minimum:500 name:CP2_STALLS : 42-0 CP2 stall cycles
+event:0x2b counters:0 um:zero minimum:500 name:ISPRAM_STALLS : 43-0 ISPRAM stall cycles
+event:0x2c counters:0 um:zero minimum:500 name:CACHE_INSN_STALLS : 44-0 Stall cycless due to CACHE instructions
+event:0x2d counters:0 um:zero minimum:500 name:LOAD_USE_STALLS : 45-0 Load to use stall cycles
+event:0x2e counters:0 um:zero minimum:500 name:INTERLOCK_STALLS : 46-0 Stall cycles due to return data from MFC0, RDHWR, and MFTR instructions
+event:0x2f counters:0 um:zero minimum:500 name:RELAX_STALLS : 47-0 Low power stall cycles (operations) as requested by the policy manager
+
+event:0x30 counters:0 um:zero minimum:500 name:IFU_FB_FULL_REFETCHES : 48-0 Refetches due to cache misses while both fill buffers already allocated
+event:0x31 counters:0 um:zero minimum:500 name:EJTAG_INSN_TRIGGERS : 49-0 EJTAG instruction triggerpoints
+
+#
+#
+# Monitor the state of various FIFO queues in the load/store unit:
+# FSB (``fill/store buffer'')
+# LDQ (``load queue'')
+# WBB (``write-back buffer'')
+#
+event:0x32 counters:0 um:zero minimum:500 name:FSB_LESS_25_FULL : 50-0 FSB < 25% full
+event:0x33 counters:0 um:zero minimum:500 name:FSB_OVER_50_FULL : 51-0 FSB > 50% full
+event:0x34 counters:0 um:zero minimum:500 name:LDQ_LESS_25_FULL : 52-0 LDQ < 25% full
+event:0x35 counters:0 um:zero minimum:500 name:LDQ_OVER_50_FULL : 53-0 LDQ > 50% full
+event:0x36 counters:0 um:zero minimum:500 name:WBB_LESS_25_FULL : 54-0 WBB < 25% full
+event:0x37 counters:0 um:zero minimum:500 name:WBB_OVER_50_FULL : 55-0 WBB > 50% full
+
+event:0x3e counters:0 um:zero minimum:500 name:READ_RESPONSE_LATENCY : 62-0 Read latency from miss detection until critical dword of response is returned
+
+#
+# Events specific to counter 1
+#
+event:0x402 counters:1 um:zero minimum:500 name:MISPREDICTED_BRANCH_INSNS : 2-1 Branch mispredictions
+event:0x403 counters:1 um:zero minimum:500 name:JR_31_MISPREDICTIONS : 3-1 JR $31 mispredictions
+event:0x404 counters:1 um:zero minimum:500 name:JR_31_NO_PREDICTIONS : 4-1 JR $31 not predicted (stack mismatch).
+event:0x405 counters:1 um:zero minimum:500 name:ITLB_MISSES : 5-1 Instruction micro-TLB misses
+event:0x406 counters:1 um:zero minimum:500 name:DTLB_MISSES : 6-1 Data micro-TLB misses
+event:0x407 counters:1 um:zero minimum:500 name:JTLB_INSN_MISSES : 7-1 Joint TLB instruction misses
+event:0x408 counters:1 um:zero minimum:500 name:JTLB_DATA_MISSES : 8-1 Joint TLB data (non-instruction) misses
+event:0x409 counters:1 um:zero minimum:500 name:ICACHE_MISSES : 9-1 Instruction cache misses
+event:0x40a counters:1 um:zero minimum:500 name:DCACHE_WRITEBACKS : 10-1 Data cache lines written back to memory
+
+event:0x40d counters:1 um:zero minimum:500 name:LOAD_MISS_INSNS : 13-1 Cacheable load instructions that miss in the cache
+event:0x40e counters:1 um:zero minimum:500 name:FPU_INSNS : 14-1 FPU instructions completed (not including loads/stores)
+event:0x40f counters:1 um:zero minimum:500 name:STORE_INSNS : 15-1 Stores completed (including FP)
+event:0x410 counters:1 um:zero minimum:500 name:MIPS16_INSNS : 16-1 MIPS16 instructions completed
+event:0x411 counters:1 um:zero minimum:500 name:INT_MUL_DIV_INSNS : 17-1 Integer multiply/divide instructions completed
+event:0x412 counters:1 um:zero minimum:500 name:REPLAYED_INSNS : 18-1 Replayed instructions
+event:0x413 counters:1 um:zero minimum:500 name:SC_INSNS_FAILED : 19-1 SC instructions completed, but store failed (because the link bit had been cleared)
+event:0x414 counters:1 um:zero minimum:500 name:CACHE_HIT_PREFETCH_INSNS : 20-1 PREFETCH instructions completed with cache hit
+event:0x415 counters:1 um:zero minimum:500 name:L2_CACHE_ACCESSES : 21-1 Accesses to the L2 cache
+event:0x416 counters:1 um:zero minimum:500 name:L2_CACHE_SINGLE_BIT_ERRORS : 22-1 Single bit errors corrected in L2
+event:0x417 counters:1 um:zero minimum:500 name:SINGLE_THREADED_CYCLES : 23-1 Cycles while one and only one TC is eligible for scheduling
+event:0x418 counters:1 um:zero minimum:500 name:REFETCHED_INSNS : 24-1 Replayed instructions sent back to IFU to be refetched
+event:0x419 counters:1 um:zero minimum:500 name:ALU_STALLS : 25-1 ALU stall cycles
+event:0x41a counters:1 um:zero minimum:500 name:ALU_DSP_SATURATION_INSNS : 26-1 ALU-DSP saturation instructions
+event:0x41b counters:1 um:zero minimum:500 name:MDU_DSP_SATURATION_INSNS : 27-1 MDU-DSP saturation instructions
+
+event:0x41c counters:1 um:zero minimum:500 name:CP2_EVENTS : 28-1 Implementation specific CP2 events
+event:0x41d counters:1 um:zero minimum:500 name:DSPRAM_EVENTS : 29-1 Implementation specific DSPRAM events
+
+event:0x41f counters:1 um:zero minimum:500 name:ITC_EVENT : 31-1 Implementation specific yield event
+
+event:0x421 counters:1 um:zero minimum:500 name:UNCACHED_STORE_INSNS : 33-1 Uncached store instructions
+event:0x423 counters:1 um:zero minimum:500 name:CP2_TO_FROM_INSNS : 35-1 CP2 to/from instructions (moves, control, loads, stores)
+
+#
+# Count number of cycles (most often ``stall cycles'', ie time lost), not just number of events.
+#
+event:0x425 counters:1 um:zero minimum:500 name:DCACHE_MISS_STALLS : 37-1 Stall cycles due to a data cache miss
+
+event:0x427 counters:1 um:zero minimum:500 name:L2_CACHE_MISS_CYCLES : 39-1 Cycles a L2 miss is outstanding, but not necessarily stalling the pipeline
+event:0x428 counters:1 um:zero minimum:500 name:ITC_STALLS : 40-1 ITC stall cycles
+event:0x429 counters:1 um:zero minimum:500 name:FPU_STALLS : 41-1 FPU stall cycles
+event:0x42a counters:1 um:zero minimum:500 name:COREEXTEND_STALLS : 42-1 CorExtend stall cycles
+event:0x42b counters:1 um:zero minimum:500 name:DSPRAM_STALLS : 43-1 DSPRAM stall cycles
+
+event:0x42d counters:1 um:zero minimum:500 name:ALU_TO_AGEN_STALLS : 45-1 ALU to AGEN stall cycles
+event:0x42e counters:1 um:zero minimum:500 name:MISPREDICTION_STALLS : 46-1 Branch mispredict stall cycles
+
+event:0x430 counters:1 um:zero minimum:500 name:FB_ENTRY_ALLOCATED_CYCLES : 48-1 Cycles while at least one IFU fill buffer is allocated
+event:0x431 counters:1 um:zero minimum:500 name:EJTAG_DATA_TRIGGERS : 49-1 EJTAG Data triggerpoints
+
+#
+# Monitor the state of various FIFO queues in the load/store unit:
+# FSB (``fill/store buffer'')
+# LDQ (``load queue'')
+# WBB (``write-back buffer'')
+# Some count events, others count stall cycles.
+#
+event:0x432 counters:1 um:zero minimum:500 name:FSB_25_50_FULL : 50-1 FSB 25-50% full
+event:0x433 counters:1 um:zero minimum:500 name:FSB_FULL_STALLS : 51-1 FSB full pipeline stall cycles
+event:0x434 counters:1 um:zero minimum:500 name:LDQ_25_50_FULL : 52-1 LDQ 25-50% full
+event:0x435 counters:1 um:zero minimum:500 name:LDQ_FULL_STALLS : 53-1 LDQ full pipeline stall cycles
+event:0x436 counters:1 um:zero minimum:500 name:WBB_25_50_FULL : 54-1 WBB 25-50% full
+event:0x437 counters:1 um:zero minimum:500 name:WBB_FULL_STALLS : 55-1 WBB full pipeline stall cycles
+
+event:0x43e counters:1 um:zero minimum:500 name:READ_RESPONSE_COUNT : 62-1 Read requests on miss detection
diff --git a/events/mips/34K/unit_masks b/events/mips/34K/unit_masks
new file mode 100644
index 0000000..6431af8
--- /dev/null
+++ b/events/mips/34K/unit_masks
@@ -0,0 +1,5 @@
+#
+# MIPS 34K possible unit masks
+#
+name:zero type:mandatory default:0x0
+ 0x0 No unit mask
diff --git a/events/mips/5K/events b/events/mips/5K/events
new file mode 100644
index 0000000..05874fd
--- /dev/null
+++ b/events/mips/5K/events
@@ -0,0 +1,36 @@
+#
+# MIPS 5K
+#
+# As standard the CPU supports 2 performance counters. Event 0, 2, 3 and 4
+# are available on both counters; the INSNS_EXECED is available on counter 0
+# as event 0 and on counter 1 as event 1; the remaining are counter-specific.
+#
+event:0x0 counters:0,1 um:zero minimum:500 name:CYCLES : Cycles
+event:0x2 counters:0,1 um:zero minimum:500 name:LOADS_EXECED : Load/pref(x)/sync/cache-ops executed
+event:0x3 counters:0,1 um:zero minimum:500 name:STORES_EXECED : Stores (including conditional stores) executed
+event:0x4 counters:0,1 um:zero minimum:500 name:COND_STORES_EXECED : Conditional stores executed
+
+#
+# Events specific to counter 0
+#
+event:0x1 counters:0 um:zero minimum:500 name:INSN_FETCHED : Instructions fetched
+event:0x5 counters:0 um:zero minimum:500 name:FAILED_COND_STORES : Failed conditional stores
+event:0x6 counters:0 um:zero minimum:500 name:BRANCHES_EXECED : Branches executed
+event:0x7 counters:0 um:zero minimum:500 name:ITLB_MISSES : ITLB miss
+event:0x8 counters:0 um:zero minimum:500 name:DTLB_MISSES : DTLB miss
+event:0x9 counters:0 um:zero minimum:500 name:ICACHE_MISS : Instruction cache miss
+event:0xa counters:0 um:zero minimum:500 name:INSN_SCHEDULED : Instruction scheduled
+event:0xe counters:0 um:zero minimum:500 name:DUAL_ISSUED_INSNS : Dual issued instructions executed
+event:0xf counters:0 um:zero minimum:500 name:INSNS_EXECED : Instructions executed
+
+#
+# Events specific to counter 1
+#
+event:0x1 counters:1 um:zero minimum:500 name:INSNS_EXECED : Instructions executed
+event:0x5 counters:1 um:zero minimum:500 name:FP_INSNS_EXECED : Floating-point instructions executed
+event:0x6 counters:1 um:zero minimum:500 name:DCACHE_LINE_EVICTED : Data cache line evicted
+event:0x7 counters:1 um:zero minimum:500 name:TLB_MISS_EXCEPTIONS : TLB miss exceptions
+event:0x8 counters:1 um:zero minimum:500 name:BRANCHES_MISSPREDICTED : Branch mispredicted
+event:0x9 counters:1 um:zero minimum:500 name:DCACHE_MISS : Data cache miss
+event:0xa counters:1 um:zero minimum:500 name:CONFLICT_STALL_M_STAGE : Instruction stall in M stage due to scheduling conflicts
+event:0xf counters:1 um:zero minimum:500 name:COP2_INSNS_EXECED : COP2 instructions executed
diff --git a/events/mips/5K/unit_masks b/events/mips/5K/unit_masks
new file mode 100644
index 0000000..a3f26e4
--- /dev/null
+++ b/events/mips/5K/unit_masks
@@ -0,0 +1,5 @@
+#
+# MIPS 5K possible unit masks
+#
+name:zero type:mandatory default:0x0
+ 0x0 No unit mask
diff --git a/events/mips/74K/events b/events/mips/74K/events
new file mode 100644
index 0000000..81700f8
--- /dev/null
+++ b/events/mips/74K/events
@@ -0,0 +1,159 @@
+#
+# MIPS 74K
+#
+
+# The 74K CPUs have four performance counters.
+#
+# Even/odd counters are distinguished by setting bit 10 in the event
+# mask. The kernel masks this bit out before writing the control
+# register.
+
+#
+# Events specific to all counters
+#
+event:0x0 counters:0,1,2,3 um:zero minimum:500 name:CYCLES : 0-0 Cycles
+event:0x1 counters:0,1,2,3 um:zero minimum:500 name:INSTRUCTIONS : 1-0 Instructions graduated
+
+#
+# Events specific to counters 0 and 2
+#
+event:0x2 counters:0,2 um:zero minimum:500 name:PREDICTED_JR_31 : 2-0 JR $31 (return) instructions predicted including speculative instructions
+event:0x3 counters:0,2 um:zero minimum:500 name:REDIRECT_STALLS : 3-0 Stall cycles due to register indirect jumps (including non-predicted JR $31), ERET/WAIT instructions, and IFU determined exception
+event:0x4 counters:0,2 um:zero minimum:500 name:ITLB_ACCESSES : 4-0 Instruction micro-TLB accesses
+
+event:0x6 counters:0,2 um:zero minimum:500 name:ICACHE_ACCESSES : 6-0 Instruction cache accesses including speculative instructions
+event:0x7 counters:0,2 um:zero minimum:500 name:ICACHE_MISS_STALLS : 7-0 Instruction cache miss stall cycles
+event:0x8 counters:0,2 um:zero minimum:500 name:UNCACHED_IFETCH_STALLS : 8-0 Uncached instruction fetch stall cycles
+event:0x9 counters:0,2 um:zero minimum:500 name:IFU_REPLAYS : 9-0 Replays within the IFU due to full Instruction Buffer
+
+event:0xb counters:0,2 um:zero minimum:500 name:IFU_IDU_MISS_PRED_UPSTREAM_CYCLES : 11-0 Cycles IFU-IDU gate is closed (to prevent upstream from getting ahead) due to mispredicted branch
+event:0xc counters:0,2 um:zero minimum:500 name:IFU_IDU_CLOGED_DOWNSTREAM_CYCLES : 12-0 Cycles IFU-IDU gate is closed (waiting for downstream to unclog) due to MTC0/MFC0 sequence in pipe, EHB, or blocked DD, DR, or DS
+event:0xd counters:0,2 um:zero minimum:500 name:DDQ0_FULL_DR_STALLS : 13-0 DR stage stall cycles due to DDQ0 (ALU out-of-order dispatch queue) full
+event:0xe counters:0,2 um:zero minimum:500 name:ALCB_FULL_DR_STALLS : 14-0 DR stage stall cycles due to ALCB (ALU completion buffers) full
+event:0xf counters:0,2 um:zero minimum:500 name:CLDQ_FULL_DR_STALLS : 15-0 DR stage stall cycles due to CLDQ (data comming back from FPU) full
+event:0x10 counters:0,2 um:zero minimum:500 name:ALU_EMPTY_CYCLES : 16-0 DDQ0 (ALU out-of-order dispatch queue) empty cycles
+event:0x11 counters:0,2 um:zero minimum:500 name:ALU_OPERANDS_NOT_READY_CYCLES : 17-0 DDQ0 (ALU out-of-order dispatch queue) no issue cycles with valid instructions but operands not ready
+event:0x12 counters:0,2 um:zero minimum:500 name:ALU_NO_ISSUES_CYCLES : 18-0 DDQ0 (ALU out-of-order dispatch queue) no issue cycles with valid instructions due to operand(s) not available, MDU busy, or CorExt resource busy
+event:0x13 counters:0,2 um:zero minimum:500 name:ALU_BUBBLE_CYCLES : 19-0 DDQ0 (ALU out-of-order dispatch queue) bubbles due to MFC1 data write
+event:0x14 counters:0,2 um:zero minimum:500 name:SINGLE_ISSUE_CYCLES : 20-0 Either DDQ0 (ALU out-of-order dispatch queue) or DDQ1 (AGEN out-of-order dispatch queue) valid instruction issue cycles
+event:0x15 counters:0,2 um:zero minimum:500 name:OOO_ALU_ISSUE_CYCLES : 21-0 Out-of-order ALU issue cycles (issued instruction is not the oldest in the pool)
+event:0x16 counters:0,2 um:zero minimum:500 name:JALR_JALR_HB_INSNS : 22-0 Graduated JALR/JALR.HB instructions
+event:0x17 counters:0,2 um:zero minimum:500 name:DCACHE_LOAD_ACCESSES : 23-0 Counts all accesses to the data cache caused by load instructions
+event:0x18 counters:0,2 um:zero minimum:500 name:DCACHE_WRITEBACKS : 24-0 Data cache writebacks
+event:0x19 counters:0,2 um:zero minimum:500 name:JTLB_DATA_ACCESSES : 25-0 Joint TLB data (non-instruction) accesses
+event:0x1a counters:0,2 um:zero minimum:500 name:LOAD_STORE_REPLAYS : 26-0 Load/store generated replays - load/store follows too closely a matching CACHEOP
+event:0x1b counters:0,2 um:zero minimum:500 name:LOAD_STORE_BLOCKED_CYCLES : 27-0 Load/store graduation blocked cycles due to CP1/2 store data not ready, SYNC/SYNCI/SC/CACHEOP at the head, or FSB/LDQ/WBB/ITU FIFO full
+event:0x1c counters:0,2 um:zero minimum:500 name:L2_CACHE_WRITEBACKS : 28-0 L2 Cache Writebacks
+event:0x1d counters:0,2 um:zero minimum:500 name:L2_CACHE_MISSES : 29-0 L2 Cache Misses
+event:0x1e counters:0,2 um:zero minimum:500 name:FSB_FULL_STALLS : 30-0 Pipe stall cycles due to FSB full
+event:0x1f counters:0,2 um:zero minimum:500 name:LDQ_FULL_STALLS : 31-0 Pipe stall cycles due to LDQ full
+event:0x20 counters:0,2 um:zero minimum:500 name:WBB_FULL_STALLS : 32-0 Pipe stall cycles due to WBB full
+
+event:0x23 counters:0,2 um:zero minimum:500 name:LOAD_MISS_CONSUMER_REPLAYS : 35-0 Replays following optimistic issue of instruction dependent on load which missed, counted only when the dependent instruction graduates
+event:0x24 counters:0,2 um:zero minimum:500 name:JR_NON_31_INSNS : 36-0 jr $xx (not $31) instructions graduated (at same cost as a mispredict)
+event:0x25 counters:0,2 um:zero minimum:500 name:BRANCH_INSNS : 37-0 Branch instructions graduated, excluding CP1/CP2 conditional branches
+event:0x26 counters:0,2 um:zero minimum:500 name:BRANCH_LIKELY_INSNS : 38-0 Branch likely instructions graduated including CP1 and CP2 branch likely instructions
+event:0x27 counters:0,2 um:zero minimum:500 name:COND_BRANCH_INSNS : 39-0 Conditional branches graduated
+event:0x28 counters:0,2 um:zero minimum:500 name:INTEGER_INSNS : 40-0 Integer instructions graduated including NOP, SSNOP, MOVCI, and EHB
+event:0x29 counters:0,2 um:zero minimum:500 name:LOAD_INSNS : 41-0 Loads graduated including CP1 ans CP2 loads
+event:0x2a counters:0,2 um:zero minimum:500 name:J_JAL_INSNS : 42-0 J/JAL graduated
+event:0x2b counters:0,2 um:zero minimum:500 name:NOP_INSNS : 43-0 NOP instructions graduated - SLL 0, NOP, SSNOP, and EHB
+event:0x2c counters:0,2 um:zero minimum:500 name:DSP_INSNS : 44-0 DSP instructions graduated
+event:0x2d counters:0,2 um:zero minimum:500 name:DSP_BRANCH_INSNS : 45-0 DSP branch instructions graduated
+event:0x2e counters:0,2 um:zero minimum:500 name:UNCACHED_LOAD_INSNS : 46-0 Uncached loads graduated
+
+event:0x31 counters:0,2 um:zero minimum:500 name:EJTAG_INSN_TRIGGERS : 49-0 EJTAG instruction triggerpoints
+event:0x32 counters:0,2 um:zero minimum:500 name:CP1_BRANCH_MISPREDICTIONS : 50-0 CP1 branches mispredicted
+event:0x33 counters:0,2 um:zero minimum:500 name:SC_INSNS : 51-0 SC instructions graduated
+event:0x34 counters:0,2 um:zero minimum:500 name:PREFETCH_INSNS : 52-0 Prefetch instructions graduated
+event:0x35 counters:0,2 um:zero minimum:500 name:NO_INSN_CYCLES : 53-0 No instructions graduated cycles
+event:0x36 counters:0,2 um:zero minimum:500 name:ONE_INSN_CYCLES : 54-0 One instruction graduated cycles
+event:0x37 counters:0,2 um:zero minimum:500 name:GFIFO_BLOCKED_CYCLES : 55-0 GFIFO blocked cycles
+event:0x38 counters:0,2 um:zero minimum:500 name:MISPREDICTION_STALLS : 56-0 Cycles from the time of a pipe kill due to mispredict until the first new instruction graduates
+event:0x39 counters:0,2 um:zero minimum:500 name:MISPREDICTED_BRANCH_INSNS_CYCLES : 57-0 Mispredicted branch instruction graduation cycles without the delay slot
+event:0x3a counters:0,2 um:zero minimum:500 name:EXCEPTIONS_TAKEN : 58-0 Exceptions taken
+event:0x3b counters:0,2 um:zero minimum:500 name:COREEXTEND_EVENTS : 59-0 Implementation specific CorExtend events
+
+event:0x3e counters:0,2 um:zero minimum:500 name:ISPRAM_EVENTS : 62-0 Implementation specific ISPRAM events
+event:0x3f counters:0,2 um:zero minimum:500 name:L2_CACHE_SINGLE_BIT_ERRORS : 63-0 Single bit errors corrected in L2
+event:0x40 counters:0,2 um:zero minimum:500 name:SYSTEM_EVENT_0 : 64-0 Implementation specific system event 0
+event:0x41 counters:0,2 um:zero minimum:500 name:SYSTEM_EVENT_2 : 65-0 Implementation specific system event 2
+event:0x42 counters:0,2 um:zero minimum:500 name:SYSTEM_EVENT_4 : 66-0 Implementation specific system event 4
+event:0x43 counters:0,2 um:zero minimum:500 name:SYSTEM_EVENT_6 : 67-0 Implementation specific system event 6
+event:0x44 counters:0,2 um:zero minimum:500 name:OCP_ALL_REQUESTS : 68-0 All OCP requests accepted
+event:0x45 counters:0,2 um:zero minimum:500 name:OCP_READ_REQUESTS : 69-0 OCP read requests accepted
+event:0x46 counters:0,2 um:zero minimum:500 name:OCP_WRITE_REQUESTS : 70-0 OCP write requests accepted
+
+event:0x4a counters:0,2 um:zero minimum:500 name:FSB_LESS_25_FULL : 74-0 FSB < 25% full
+event:0x4b counters:0,2 um:zero minimum:500 name:LDQ_LESS_25_FULL : 75-0 LDQ < 25% full
+event:0x4c counters:0,2 um:zero minimum:500 name:WBB_LESS_25_FULL : 76-0 WBB < 25% full
+
+
+#
+# Events specific to counters 1 and 3
+#
+
+event:0x402 counters:1,3 um:zero minimum:500 name:JR_31_MISPREDICTIONS : 2-1 JR $31 (return) instructions mispredicted
+event:0x403 counters:1,3 um:zero minimum:500 name:JR_31_NO_PREDICTIONS : 3-1 JR $31 (return) instructions not predicted
+event:0x404 counters:1,3 um:zero minimum:500 name:ITLB_MISSES : 4-1 Instruction micro-TLB misses
+event:0x405 counters:1,3 um:zero minimum:500 name:JTLB_INSN_MISSES : 5-1 Joint TLB instruction misses
+event:0x406 counters:1,3 um:zero minimum:500 name:ICACHE_MISSES : 6-1 Instruction cache misses, includes misses from fetch-ahead and speculation
+
+event:0x408 counters:1,3 um:zero minimum:500 name:PDTRACE_BACK_STALLS : 8-1 PDtrace back stalls
+event:0x409 counters:1,3 um:zero minimum:500 name:KILLED_FETCH_SLOTS : 9-1 Valid fetch slots killed due to taken branches/jumps or stalling instructions
+
+event:0x40b counters:1,3 um:zero minimum:500 name:IFU_IDU_NO_FETCH_CYCLES : 11-1 Cycles IFU-IDU gate open but no instructions fetched by IFU
+
+event:0x40d counters:1,3 um:zero minimum:500 name:DDQ1_FULL_DR_STALLS : 13-1 DR stage stall cycles due to DDQ1 (AGEN out-of-order dispatch queue) full
+event:0x40e counters:1,3 um:zero minimum:500 name:AGCB_FULL_DR_STALLS : 14-1 DR stage stall cycles due to AGCB (AGEN completion buffers) full
+event:0x40f counters:1,3 um:zero minimum:500 name:IODQ_FULL_DR_STALLS : 15-1 DR stage stall cycles due to IODQ (data comming back from IO) full
+event:0x410 counters:1,3 um:zero minimum:500 name:AGEN_EMPTY_CYCLES : 16-1 DDQ1 (AGEN out-of-order dispatch queue) empty cycles
+event:0x411 counters:1,3 um:zero minimum:500 name:AGEN_OPERANDS_NOT_READY_CYCLES : 17-1 DDQ1 (AGEN out-of-order dispatch queue) no issue cycles with valid instructions but operands not ready
+event:0x412 counters:1,3 um:zero minimum:500 name:AGEN_NO_ISSUES_CYCLES : 18-1 DDQ1 (AGEN out-of-order dispatch queue) no issue cycles with valid instructions due to operand(s) not available, non-issued stores blocking ready to issue loads, or non-issued CACHEOPs blocking ready to issue loads
+event:0x413 counters:1,3 um:zero minimum:500 name:AGEN_BUBBLE_CYCLES : 19-1 DDQ1 (AGEN out-of-order dispatch queue) bubbles due to MFC2 data write or cache access from FSB
+event:0x414 counters:1,3 um:zero minimum:500 name:DUAL_ISSUE_CYCLES : 20-1 Both DDQ0 (ALU out-of-order dispatch queue) and DDQ1 (AGEN out-of-order dispatch queue) valid instruction issue cycles
+event:0x415 counters:1,3 um:zero minimum:500 name:OOO_AGEN_ISSUE_CYCLES : 21-1 Out-of-order AGEN issue cycles (issued instruction is not the oldest in the pool)
+event:0x416 counters:1,3 um:zero minimum:500 name:DCACHE_LINE_REFILL_REQUESTS : 22-1 Data cache line loads (line refill requests)
+event:0x417 counters:1,3 um:zero minimum:500 name:DCACHE_ACCESSES : 23-1 Data cache accesses
+event:0x418 counters:1,3 um:zero minimum:500 name:DCACHE_MISSES : 24-1 Data cache misses
+event:0x419 counters:1,3 um:zero minimum:500 name:JTLB_DATA_MISSES : 25-1 Joint TLB data (non-instruction) misses
+event:0x41a counters:1,3 um:zero minimum:500 name:VA_TRANSALTION_CORNER_CASES : 26-1 Virtual memory address translation synonyms, homonyms, and aliases (loads/stores treated as miss in the cache)
+event:0x41b counters:1,3 um:zero minimum:500 name:LOAD_STORE_NO_FILL_REQUESTS : 27-1 Load/store graduations not resulting in a bus request because misses at integer pipe graduation turn into hit or merge with outstanding fill request
+event:0x41c counters:1,3 um:zero minimum:500 name:L2_CACHE_ACCESSES : 28-1 Accesses to the L2 cache
+event:0x41d counters:1,3 um:zero minimum:500 name:L2_CACHE_MISS_CYCLES : 29-1 Cycles a L2 miss is outstanding, but not necessarily stalling the pipeline
+event:0x41e counters:1,3 um:zero minimum:500 name:FSB_OVER_50_FULL : 30-1 FSB > 50% full
+event:0x41f counters:1,3 um:zero minimum:500 name:LDQ_OVER_50_FULL : 31-1 LDQ > 50% full
+event:0x420 counters:1,3 um:zero minimum:500 name:WBB_OVER_50_FULL : 32-1 WBB > 50% full
+
+event:0x423 counters:1,3 um:zero minimum:500 name:CP1_CP2_LOAD_INSNS : 35-1 CP1/CP2 load instructions graduated
+event:0x424 counters:1,3 um:zero minimum:500 name:MISPREDICTED_JR_31_INSNS : 36-1 jr $31 instructions graduated after mispredict
+event:0x425 counters:1,3 um:zero minimum:500 name:CP1_CP2_COND_BRANCH_INSNS : 37-1 CP1/CP2 conditional branch instructions graduated
+event:0x426 counters:1,3 um:zero minimum:500 name:MISPREDICTED_BRANCH_LIKELY_INSNS : 38-1 Mispredicted branch likely instructions graduated
+event:0x427 counters:1,3 um:zero minimum:500 name:MISPREDICTED_BRANCH_INSNS : 39-1 Mispredicted branches graduated
+event:0x428 counters:1,3 um:zero minimum:500 name:FPU_INSNS : 40-1 FPU instructions graduated
+event:0x429 counters:1,3 um:zero minimum:500 name:STORE_INSNS : 41-1 Store instructions graduated including CP1 ans CP2 stores
+event:0x42a counters:1,3 um:zero minimum:500 name:MIPS16_INSNS : 42-1 MIPS16 instructions graduated
+event:0x42b counters:1,3 um:zero minimum:500 name:NT_MUL_DIV_INSNS : 43-1 Integer multiply/divide instructions graduated
+event:0x42c counters:1,3 um:zero minimum:500 name:ALU_DSP_SATURATION_INSNS : 44-1 ALU-DSP graduated, result was saturated
+event:0x42d counters:1,3 um:zero minimum:500 name:MDU_DSP_SATURATION_INSNS : 45-1 MDU-DSP graduated, result was saturated
+event:0x42e counters:1,3 um:zero minimum:500 name:UNCACHED_STORE_INSNS : 46-1 Uncached stores graduated
+
+event:0x433 counters:1,3 um:zero minimum:500 name:FAILED_SC_INSNS : 51-1 SC instructions failed
+event:0x434 counters:1,3 um:zero minimum:500 name:CACHE_HIT_PREFETCH_INSNS : 52-1 PREFETCH instructions which did nothing, because they hit in the cache
+event:0x435 counters:1,3 um:zero minimum:500 name:LOAD_MISS_INSNS : 53-1 Cacheable load instructions that miss in the cache graduated
+event:0x436 counters:1,3 um:zero minimum:500 name:TWO_INSNS_CYCLES : 54-1 Two instructions graduated cycles
+event:0x437 counters:1,3 um:zero minimum:500 name:CP1_CP2_STORE_INSNS : 55-1 CP1/CP2 Store graduated
+event:0x43a counters:1,3 um:zero minimum:500 name:GRADUATION_REPLAYS : 58-1 Replays initiated from graduation
+event:0x43e counters:1,3 um:zero minimum:500 name:DSPRAM_EVENTS : 62-1 Implementation specific events from the DSPRAM block
+
+event:0x440 counters:0,2 um:zero minimum:500 name:SYSTEM_EVENT_1 : 64-1 Implementation specific system event 1
+event:0x441 counters:0,2 um:zero minimum:500 name:SYSTEM_EVENT_3 : 65-1 Implementation specific system event 3
+event:0x442 counters:0,2 um:zero minimum:500 name:SYSTEM_EVENT_5 : 66-1 Implementation specific system event 5
+event:0x443 counters:0,2 um:zero minimum:500 name:SYSTEM_EVENT_7 : 67-1 Implementation specific system event 7
+event:0x444 counters:0,2 um:zero minimum:500 name:OCP_ALL_CACHEABLE_REQUESTS : 68-1 All OCP cacheable requests accepted
+event:0x445 counters:0,2 um:zero minimum:500 name:OCP_READ_CACHEABLE_REQUESTS : 69-1 OCP cacheable read request accepted
+event:0x446 counters:0,2 um:zero minimum:500 name:OCP_WRITE_CACHEABLE_REQUESTS : 70-1 OCP cacheable write request accepted
+
+event:0x44a counters:0,2 um:zero minimum:500 name:FSB_25_50_FULL : 74-1 FSB 25-50% full
+event:0x44b counters:0,2 um:zero minimum:500 name:LDQ_25_50_FULL : 75-1 LDQ 25-50% full
+event:0x44c counters:0,2 um:zero minimum:500 name:WBB_25_50_FULL : 76-1 WBB 25-50% full
diff --git a/events/mips/74K/unit_masks b/events/mips/74K/unit_masks
new file mode 100644
index 0000000..d379dcf
--- /dev/null
+++ b/events/mips/74K/unit_masks
@@ -0,0 +1,5 @@
+#
+# MIPS 74K possible unit masks
+#
+name:zero type:mandatory default:0x0
+ 0x0 No unit mask
diff --git a/events/mips/loongson2/events b/events/mips/loongson2/events
new file mode 100644
index 0000000..68a472b
--- /dev/null
+++ b/events/mips/loongson2/events
@@ -0,0 +1,34 @@
+# loongson2 Events
+#
+event:0x00 counters:0 um:zero minimum:10000 name:CPU_CLK_UNHALTED : Cycles outside of haltstate
+event:0x01 counters:0 um:zero minimum:5000 name:BRANCH_INSTRUCTIONS : Branch instructions
+event:0x02 counters:0 um:zero minimum:400 name:JUMP_INSTRUCTIONS : JR instructions
+event:0x03 counters:0 um:zero minimum:500 name:JR31_INSTRUCTIONS : JR(rs=31) instructions
+event:0x04 counters:0 um:zero minimum:500 name:ICACHE_MISSES : Instruction cache misses
+event:0x05 counters:0 um:zero minimum:500 name:ALU1_ISSUED : ALU1 operation issued
+event:0x06 counters:0 um:zero minimum:8000 name:MEM_ISSUED : Memory read/write issued
+event:0x07 counters:0 um:zero minimum:300 name:FALU1_ISSUED : Float ALU1 operation issued
+event:0x08 counters:0 um:zero minimum:200 name:BHT_BRANCH_INSTRUCTIONS : BHT prediction instructions
+event:0x09 counters:0 um:zero minimum:200 name:MEM_READ : Read from primary memory
+event:0x0a counters:0 um:zero minimum:300 name:FQUEUE_FULL : Fix queue full
+event:0x0b counters:0 um:zero minimum:300 name:ROQ_FULL : Reorder queue full
+event:0x0c counters:0 um:zero minimum:300 name:CP0_QUEUE_FULL : CP0 queue full
+event:0x0d counters:0 um:zero minimum:300 name:TLB_REFILL : TLB refill exception
+event:0x0e counters:0 um:zero minimum:5 name:EXCEPTION : Exceptions
+event:0x0f counters:0 um:zero minimum:300 name:INTERNAL_EXCEPTION : Internal exceptions
+event:0x10 counters:1 um:zero minimum:5000 name:INSTRUCTION_COMMITTED : Instruction committed
+event:0x11 counters:1 um:zero minimum:500 name:BRANCHES_MISPREDICTED : Branch mispredicted
+event:0x12 counters:1 um:zero minimum:200 name:JR_MISPREDICTED : JR mispredicted
+event:0x13 counters:1 um:zero minimum:200 name:JR31_MISPREDICTED : JR31 mispredicted
+event:0x14 counters:1 um:zero minimum:500 name:DCACHE_MISSES : Data cache misses
+event:0x15 counters:1 um:zero minimum:500 name:ALU2_ISSUED : ALU2 operation issued
+event:0x16 counters:1 um:zero minimum:500 name:FALU2_ISSUED : FALU2 operation issued
+event:0x17 counters:1 um:zero minimum:500 name:UNCACHED_ACCESS : Uncached accesses
+event:0x18 counters:1 um:zero minimum:500 name:BHT_MISPREDICTED : Branch history table mispredicted
+event:0x19 counters:1 um:zero minimum:5000 name:MEM_WRITE : Write to memory
+event:0x1a counters:1 um:zero minimum:500 name:FTQ_FULL : Float queue full
+event:0x1b counters:1 um:zero minimum:500 name:BRANCH_QUEUE_FULL : Branch queue full
+event:0x1c counters:1 um:zero minimum:500 name:ITLB_MISSES : Instruction TLB misses
+event:0x1d counters:1 um:zero minimum:500 name:TOTAL_EXCEPTIONS : Total exceptions
+event:0x1e counters:1 um:zero minimum:500 name:LOAD_SPECULATION_MISSES : Load speculation misses
+event:0x1f counters:1 um:zero minimum:500 name:CP0Q_FORWARD_VALID : CP0 queue forward valid
diff --git a/events/mips/loongson2/unit_masks b/events/mips/loongson2/unit_masks
new file mode 100644
index 0000000..0d4ce5b
--- /dev/null
+++ b/events/mips/loongson2/unit_masks
@@ -0,0 +1,4 @@
+# loongson2 possible unit masks
+#
+name:zero type:mandatory default:0x0
+ 0x0 No unit mask
diff --git a/events/mips/r10000/events b/events/mips/r10000/events
new file mode 100644
index 0000000..237cc06
--- /dev/null
+++ b/events/mips/r10000/events
@@ -0,0 +1,36 @@
+#
+# R10000 events
+#
+# The same event numbers mean different things on the two counters
+#
+event:0x00 counters:0,1 um:zero minimum:500 name:CYCLES : Cycles
+event:0x01 counters:0 um:zero minimum:500 name:INSTRUCTIONS_ISSUED : Instructions issued
+event:0x01 counters:1 um:zero minimum:500 name:INSTRUCTIONS_GRADUATED : Instructions graduated
+event:0x02 counters:0 um:zero minimum:500 name:LOAD_PREFETC_SYNC_CACHEOP_ISSUED : Load / prefetch / sync / CacheOp issued
+event:0x02 counters:1 um:zero minimum:500 name:LOAD_PREFETC_SYNC_CACHEOP_GRADUATED : Load / prefetch / sync / CacheOp graduated
+event:0x03 counters:0 um:zero minimum:500 name:STORES_ISSUED : Stores issued
+event:0x03 counters:1 um:zero minimum:500 name:STORES_GRADUATED : Stores graduated
+event:0x04 counters:0 um:zero minimum:500 name:STORE_COND_ISSUED : Store conditional issued
+event:0x04 counters:1 um:zero minimum:500 name:STORE_COND_GRADUATED : Store conditional graduated
+event:0x05 counters:0 um:zero minimum:500 name:FAILED_STORE_CONDITIONAL : Failed store conditional
+event:0x05 counters:1 um:zero minimum:500 name:FP_INSTRUCTON_GRADUATED : Floating-point instructions graduated
+event:0x06 counters:0 um:zero minimum:500 name:BRANCHES_RESOLVED : Branches resolved
+event:0x06 counters:1 um:zero minimum:500 name:QUADWORDS_WB_FROM_PRIMARY_DCACHE : Quadwords written back from primary data cache
+event:0x07 counters:0 um:zero minimum:500 name:QUADWORDS_WB_FROM_SCACHE : Quadwords written back from secondary cache
+event:0x07 counters:1 um:zero minimum:500 name:TLB_REFILL_EXCEPTIONS : TLB refill exceptions
+event:0x08 counters:0 um:zero minimum:500 name:CORRECTABLE_ECC_ERRORS_SCACHE : Correctable ECC errors on secondary cache data
+event:0x08 counters:1 um:zero minimum:500 name:BRANCHES_MISPREDICTED : Branches mispredicted
+event:0x09 counters:0 um:zero minimum:500 name:INSTRUCTION_CACHE_MISSES : Instruction cache misses
+event:0x09 counters:1 um:zero minimum:500 name:SCACHE_LOAD_STORE_CACHEOP_OPERATIONS : Secondary cache load / store and cache-ops operations
+event:0x0a counters:0 um:zero minimum:500 name:SCACHE_MISSES_INSTRUCTION : Secondary cache misses (instruction)
+event:0x0a counters:1 um:zero minimum:500 name:SCACHE_MISSES_DATA : Secondary cache misses (data)
+event:0x0b counters:0 um:zero minimum:500 name:SCACHE_WAY_MISPREDICTED_INSN : Secondary cache way mispredicted (instruction)
+event:0x0b counters:1 um:zero minimum:500 name:SCACHE_WAY_MISPREDICTED_DATA : Secondary cache way mispredicted (data)
+event:0x0c counters:0 um:zero minimum:500 name:EXTERNAL_INTERVENTION_RQ : External intervention requests
+event:0x0c counters:1 um:zero minimum:500 name:EXTERNAL_INTERVENTION_RQ_HITS_SCACHE : External intervention request is determined to have hit in secondary cache
+event:0x0d counters:0 um:zero minimum:500 name:EXTERNAL_INVALIDATE_RQ : External invalidate requests
+event:0x0d counters:1 um:zero minimum:500 name:EXTERNAL_INVALIDATE_RQ_HITS_SCACHE : External invalidate request is determined to have hit in secondary cache
+event:0x0e counters:0 um:zero minimum:500 name:FUNCTIONAL_UNIT_COMPLETION_CYCLES : Functional unit completion cycles
+event:0x0e counters:1 um:zero minimum:500 name:STORES_OR_STORE_PREF_TO_CLEANEXCLUSIVE_SCACHE_BLOCKS : Stores or prefetches with store hint to CleanExclusive secondary cache blocks
+event:0x0f counters:0 um:zero minimum:500 name:INSTRUCTION_GRADUATED : Instructions graduated
+event:0x0f counters:1 um:zero minimum:500 name:STORES_OR_STORE_PREF_TO_SHD_SCACHE_BLOCKS : Stores or prefetches with store hint to Shared secondary cache blocks
diff --git a/events/mips/r10000/unit_masks b/events/mips/r10000/unit_masks
new file mode 100644
index 0000000..fab7d83
--- /dev/null
+++ b/events/mips/r10000/unit_masks
@@ -0,0 +1,5 @@
+#
+# MIPS R10000 possible unit masks
+#
+name:zero type:mandatory default:0x0
+ 0x0 No unit mask
diff --git a/events/mips/r12000/events b/events/mips/r12000/events
new file mode 100644
index 0000000..1fa6779
--- /dev/null
+++ b/events/mips/r12000/events
@@ -0,0 +1,35 @@
+#
+# R12000 events
+#
+event:0x0 counters:0,1,2,3 um:zero minimum:500 name:CYCLES : Cycles
+event:0x1 counters:0,1,2,3 um:zero minimum:500 name:DECODED_INSTRUCTIONS : Decoded instructions
+event:0x2 counters:0,1,2,3 um:zero minimum:500 name:DECODED_LOADS : Decoded loads
+event:0x3 counters:0,1,2,3 um:zero minimum:500 name:DECODED_STORES : Decoded stores
+event:0x4 counters:0,1,2,3 um:zero minimum:500 name:MISS_TABLE_OCCUPANCY : Miss Handling Table Occupancy
+event:0x5 counters:0,1,2,3 um:zero minimum:500 name:FAILED_STORE_CONDITIONAL : Failed store conditional
+event:0x6 counters:0,1,2,3 um:zero minimum:500 name:RESOLVED_BRANCH_CONDITIONAL : Resolved conditional branches
+event:0x7 counters:0,1,2,3 um:zero minimum:500 name:QUADWORRDS_WRITEBACK_FROM_SC : Quadwords written back from secondary cache
+event:0x8 counters:0,1,2,3 um:zero minimum:500 name:CORRECTABLE_ECC_ERRORS : Correctable ECC errors on secondary cache data
+event:0x9 counters:0,1,2,3 um:zero minimum:500 name:ICACHE_MISSES : Instruction cache misses
+event:0xa counters:0,1,2,3 um:zero minimum:500 name:INSTRUCTION_SECONDARY_CACHE_MISSES : Secondary cache misses (instruction)
+event:0xb counters:0,1,2,3 um:zero minimum:500 name:SECONDARY_CACHE_WAY_MISSPREDICTED : Secondary cache way mispredicted (instruction)
+event:0xc counters:0,1,2,3 um:zero minimum:500 name:INTERVENTION_REQUESTS : External intervention requests
+event:0xd counters:0,1,2,3 um:zero minimum:500 name:EXTERNAL_REQUESTS : External invalidate requests
+
+event:0xf counters:0,1,2,3 um:zero minimum:500 name:INSTRUCTIONS_GRADUATED : Instructions graduated
+event:0x10 counters:0,1,2,3 um:zero minimum:500 name:PREFETCH_INSTRUCTIONS_EXECUTED : Executed prefetch instructions
+event:0x11 counters:0,1,2,3 um:zero minimum:500 name:PREFETCH_MISSES_IN_DCACHE : Primary data cache misses by prefetch instructions
+event:0x12 counters:0,1,2,3 um:zero minimum:500 name:GRADUATED_LOADS : Graduated loads
+event:0x13 counters:0,1,2,3 um:zero minimum:500 name:GRADUATED_STORES : Graduated stores
+event:0x14 counters:0,1,2,3 um:zero minimum:500 name:GRADUATED_STORE_CONDITIONALS : Graduated store conditionals
+event:0x15 counters:0,1,2,3 um:zero minimum:500 name:GRADUATED_FP_INSTRUCTIONS : Graduated floating point instructions
+event:0x16 counters:0,1,2,3 um:zero minimum:500 name:QUADWORDS : Quadwords written back from primary data cache
+event:0x17 counters:0,1,2,3 um:zero minimum:500 name:TLB_MISSES : TLB misses
+event:0x18 counters:0,1,2,3 um:zero minimum:500 name:MISPREDICTED_BRANCHES : Mispredicted branches
+event:0x19 counters:0,1,2,3 um:zero minimum:500 name:DCACHE_MISSES : Primary data cache misses
+event:0x1a counters:0,1,2,3 um:zero minimum:500 name:SCACHE_MISSES : Secondary cache misses (data)
+event:0x1b counters:0,1,2,3 um:zero minimum:500 name:SCACHE_WAY_MISPREDICTION : Misprediction from scache way prediction table (data)
+event:0x1c counters:0,1,2,3 um:zero minimum:500 name:STATE_OF_SCACHE_INTERVENTION_HIT : State of external intervention hit in secondary cache
+event:0x1d counters:0,1,2,3 um:zero minimum:500 name:STATE_OF_EXTERNAL_INVALIDATION_HIT : State of external invalidation hits in secondary cache
+event:0x1e counters:0,1,2,3 um:zero minimum:500 name:STORE_PREFETCH_EXCLUSIVE_TO_CLEAN_SC_BLOCK : Store/prefetch exclusive to clean block in secondary cache
+event:0x1f counters:0,1,2,3 um:zero minimum:500 name:STORE_PREFETCH_EXCLUSIVE_SHARED_SC_BLOCK : Store/prefetch exclusive to shared block in secondary
diff --git a/events/mips/r12000/unit_masks b/events/mips/r12000/unit_masks
new file mode 100644
index 0000000..20c8250
--- /dev/null
+++ b/events/mips/r12000/unit_masks
@@ -0,0 +1,7 @@
+#
+# MIPS R12000 possible unit masks
+#
+# We don't support the R12000 conditional count feature yet.
+#
+name:zero type:mandatory default:0x0
+ 0x0 No unit mask
diff --git a/events/mips/rm7000/events b/events/mips/rm7000/events
new file mode 100644
index 0000000..bfcde7a
--- /dev/null
+++ b/events/mips/rm7000/events
@@ -0,0 +1,34 @@
+#
+# RM7000 events
+#
+event:0x00 counters:0,1 um:zero minimum:500 name:CYCLES : Clock cycles
+event:0x01 counters:0,1 um:zero minimum:500 name:INSTRUCTIONS_ISSUED : Total instructions issued
+event:0x02 counters:0,1 um:zero minimum:500 name:FP_INSTRUCTIONS_ISSUED : Floating-point instructions issued
+event:0x03 counters:0,1 um:zero minimum:500 name:INTEGER_INSTRUCTIONS_ISSUED : Integer instructions issued
+event:0x04 counters:0,1 um:zero minimum:500 name:LOAD_INSTRUCTIONS_ISSUED : Load instructions issued
+event:0x05 counters:0,1 um:zero minimum:500 name:STORE_INSTRUCTIONS_ISSUED : Store instructions issued
+event:0x06 counters:0,1 um:zero minimum:500 name:DUAL_ISSUED_PAIRS : Dual issued pairs
+event:0x07 counters:0,1 um:zero minimum:500 name:BRANCH_PREFETCHES : Branch prefetches
+event:0x08 counters:0,1 um:zero minimum:500 name:EXTERNAL_CACHE_MISSES : External Cache Misses
+event:0x09 counters:0,1 um:zero minimum:500 name:STALL_CYCLES : Stall cycles
+event:0x0a counters:0,1 um:zero minimum:500 name:SCACHE_MISSES : Secondary cache misses
+event:0x0b counters:0,1 um:zero minimum:500 name:ICACHE_MISSES : Instruction cache misses
+event:0x0c counters:0,1 um:zero minimum:500 name:DCACHE_MISSES : Data cache misses
+event:0x0d counters:0,1 um:zero minimum:500 name:DTLB_MISSES : Data TLB misses
+event:0x0e counters:0,1 um:zero minimum:500 name:ITLB_MISSES : Instruction TLB misses
+event:0x0f counters:0,1 um:zero minimum:500 name:JTLB_INSTRUCTION_MISSES : Joint TLB instruction misses
+event:0x10 counters:0,1 um:zero minimum:500 name:JTLB_DATA_MISSES : Joint TLB data misses
+event:0x11 counters:0,1 um:zero minimum:500 name:BRANCHES_TAKEN : Branches taken
+event:0x12 counters:0,1 um:zero minimum:500 name:BRANCHES_ISSUED : Branches issued
+event:0x13 counters:0,1 um:zero minimum:500 name:SCACHE_WRITEBACKS : Secondary cache writebacks
+event:0x14 counters:0,1 um:zero minimum:500 name:PCACHE_WRITEBACKS : Primary cache writebacks
+event:0x15 counters:0,1 um:zero minimum:500 name:DCACHE_MISS_STALL_CYCLES : Dcache miss stall cycles (cycles where both cache miss tokens taken and a third try is requested)
+event:0x16 counters:0,1 um:zero minimum:500 name:CACHE_MISSES : Cache misses
+event:0x17 counters:0,1 um:zero minimum:500 name:FP_EXCEPTION_STALL_CYCLES : FP possible exception cycles
+event:0x18 counters:0,1 um:zero minimum:500 name:SLIP_CYCLES_DUE_MULTIPLIER_BUSY : Slip Cycles due to multiplier busy
+event:0x19 counters:0,1 um:zero minimum:500 name:COP0_SLIP_CYCLES : Coprocessor 0 slip cycles
+event:0x1a counters:0,1 um:zero minimum:500 name:SLIP_CYCLES_PENDING_NON_BLKING_LOAD : Slip cycles due to pending non-blocking loads
+event:0x1c counters:0,1 um:zero minimum:500 name:WRITE_BUFFER_FULL_STALL_CYCLES : Write buffer full stall cycles
+event:0x1d counters:0,1 um:zero minimum:500 name:CACHE_INSTRUCTION_STALL_CYCLES : Cache instruction stall cycles
+event:0x1e counters:0,1 um:zero minimum:500 name:MULTIPLIER_STALL_CYCLES : Multiplier stall cycles
+event:0x1f counters:0,1 um:zero minimum:500 name:STALL_CYCLES_PENDING_NON_BLKING_LOAD : Stall cycles due to pending non-blocking loads - stall start of exception
diff --git a/events/mips/rm7000/unit_masks b/events/mips/rm7000/unit_masks
new file mode 100644
index 0000000..cb11b7c
--- /dev/null
+++ b/events/mips/rm7000/unit_masks
@@ -0,0 +1,5 @@
+#
+# MIPS RM7000 possible unit masks
+#
+name:zero type:mandatory default:0x0
+ 0x0 No unit mask
diff --git a/events/mips/rm9000/events b/events/mips/rm9000/events
new file mode 100644
index 0000000..71d8491
--- /dev/null
+++ b/events/mips/rm9000/events
@@ -0,0 +1,32 @@
+#
+# RM9000 events
+#
+event:0x00 counters:0,1 um:zero minimum:500 name:CYCLES : Processor clock cycles
+event:0x01 counters:0,1 um:zero minimum:500 name:INSTRUCTIONS_ISSUED : Instructions issued
+event:0x02 counters:0,1 um:zero minimum:500 name:FP_INSTRUCTIONS_ISSUED : Floating-point instructions issued
+event:0x03 counters:0,1 um:zero minimum:500 name:INT_INSTRUCTIONS_ISSUED : Integer instructions issued
+event:0x04 counters:0,1 um:zero minimum:500 name:LOAD_INSTRUCTIONS_ISSUED : Load instructions issued
+event:0x05 counters:0,1 um:zero minimum:500 name:STORE_INSTRUCTIONS_ISSUED : Store instructions issued
+event:0x06 counters:0,1 um:zero minimum:500 name:INSTRUCTIONS_DUAL_ISSUED : Dual-issued instruction pairs
+event:0x07 counters:0,1 um:zero minimum:500 name:BRANCH_MISSPREDICTS : Branch mispredictions
+event:0x09 counters:0,1 um:zero minimum:500 name:STALL_CYCLES : Stall cycles
+event:0x0a counters:0,1 um:zero minimum:500 name:L2_CACHE_MISSES : L2 cache misses
+event:0x0b counters:0,1 um:zero minimum:500 name:ICACHE_MISSES : Icache misses
+event:0x0c counters:0,1 um:zero minimum:500 name:DCACHE_MISSES : Dcache misses
+event:0x0d counters:0,1 um:zero minimum:500 name:DTLB_MISSES : Data TLB misses
+event:0x0e counters:0,1 um:zero minimum:500 name:ITLB_MISSES : Instruction TLB misses
+event:0x0f counters:0,1 um:zero minimum:500 name:JTLB_INSTRUCTION_MISSES : Joint TLB instruction misses
+event:0x10 counters:0,1 um:zero minimum:500 name:JTLB_DATA_MISSES : Joint TLB data misses
+event:0x11 counters:0,1 um:zero minimum:500 name:BRANCHES_TAKEN : Branches taken
+event:0x12 counters:0,1 um:zero minimum:500 name:BRANCHES_ISSUED : Branch instructions issued
+event:0x13 counters:0,1 um:zero minimum:500 name:L2_WRITEBACKS : L2 cache writebacks
+event:0x14 counters:0,1 um:zero minimum:500 name:DCACHE_WRITEBACKS : Dcache writebacks
+event:0x15 counters:0,1 um:zero minimum:500 name:DCACHE_MISS_STALL_CYCLES : Dcache-miss stall cycles
+event:0x16 counters:0,1 um:zero minimum:500 name:CACHE_REMISSES : Cache remisses
+event:0x17 counters:0,1 um:zero minimum:500 name:FP_POSSIBLE_EXCEPTION_CYCLES : Floating-point possible exception cycles
+event:0x18 counters:0,1 um:zero minimum:500 name:MULTIPLIER_BUSY_SLIP_CYCLES : Slip cycles due to busy multiplier
+event:0x19 counters:0,1 um:zero minimum:500 name:COP0_SLIP_CYCLES : Co-processor 0 slip cycles
+event:0x1a counters:0,1 um:zero minimum:500 name:NONBLOCKING_LOAD_SLIP_CYCLES : Slip cycles due to pending non-blocking loads
+event:0x1b counters:0,1 um:zero minimum:500 name:WRITE_BUFFER_FULL_STALL_CYCLES : Stall cycles due to a full write buffer
+event:0x1c counters:0,1 um:zero minimum:500 name:CACHE_INSN_STALL_CYCLES : Stall cycles due to cache instructions
+event:0x1e counters:0,1 um:zero minimum:500 name:NONBLOCKING_LOAD_PENDING_EXCEPTION_STALL_CYCLES : Stall cycles due to pending non-blocking loads - stall start of exception
diff --git a/events/mips/rm9000/unit_masks b/events/mips/rm9000/unit_masks
new file mode 100644
index 0000000..63ba9da
--- /dev/null
+++ b/events/mips/rm9000/unit_masks
@@ -0,0 +1,5 @@
+#
+# MIPS RM9000 possible unit masks
+#
+name:zero type:mandatory default:0x0
+ 0x0 No unit mask
diff --git a/events/mips/sb1/events b/events/mips/sb1/events
new file mode 100644
index 0000000..efc28ce
--- /dev/null
+++ b/events/mips/sb1/events
@@ -0,0 +1,73 @@
+#
+# Sibyte SB1 events
+#
+
+event:0x10 counters:0,1,2,3 um:zero minimum:500 name:CYCLES :Elapsed cycles
+
+# Execution Counts and Instruction Slotting
+event:0x28 counters:1,2,3 um:zero minimum:500 name:ISSUE_L0 :Issue to L0
+event:0x29 counters:1,2,3 um:zero minimum:500 name:ISSUE_L1 :Issue to L0
+event:0x2a counters:1,2,3 um:zero minimum:500 name:ISSUE_E0 :Issue to E0
+event:0x2b counters:1,2,3 um:zero minimum:500 name:ISSUE_E1 :Issue to E1
+
+# Explaining Sub-Peak Performance: Pipeline Traps
+event:0x2f counters:1,2,3 um:zero minimum:500 name:BRANCH_MISSPREDICTS :Branch mispredicts
+event:0x1d counters:1,2,3 um:zero minimum:500 name:MBOX_REPLAY :MBOX replay
+event:0x1c counters:1,2,3 um:zero minimum:500 name:DCFIFO :DCFIFO
+event:0x1e counters:1,2,3 um:zero minimum:500 name:DATA_DEPENDENCY_REPLAY :Data dependency replay
+event:0x1b counters:1,2,3 um:zero minimum:500 name:DCACHE_FILL_REPLAY :Dcache fill replay
+event:0x1f counters:1,2,3 um:zero minimum:500 name:ANY_REPLAY :Any replay except mispredict
+
+
+# Explaining Sub-Peak Performance: static and dynamic stalls
+event:0x20 counters:1,2,3 um:zero minimum:500 name:MAX_ISSUE :Max issue
+event:0x21 counters:1,2,3 um:zero minimum:500 name:NO_VALID_INSN :No valid instr to issue
+event:0x22 counters:1,2,3 um:zero minimum:500 name:CONSUMER_WAITING_FOR_LOAD :load consumer waiting for dfill
+event:0x23 counters:1,2,3 um:zero minimum:500 name:NOT_DATA_READY :Not data ready
+event:0x24 counters:1,2,3 um:zero minimum:500 name:RESOURCE_CONSTRAINT :Resource (L0/1 E0/1) constraint
+event:0x25 counters:1,2,3 um:zero minimum:500 name:ISSUE_CONFLICT_DUE_IMISS :issue conflict due to imiss using LS0
+event:0x26 counters:1,2,3 um:zero minimum:500 name:ISSUE_CONFLICT_DUE_DFILL :issue conflict due to dfill using LS0/1
+
+# Grouping Co-issued Instructions
+event:0x27 counters:1,2,3 um:zero minimum:500 name:INSN_STAGE4 :One or more instructions survives stage 4
+
+# Branch information
+event:0x2c counters:1,2,3 um:zero minimum:500 name:BRANCH_STAGE4 :Branch survived stage 4
+event:0x2d counters:1,2,3 um:zero minimum:500 name:BRANCH_REALLY_TAKEN :Conditional branch was really taken
+event:0x2e counters:1,2,3 um:zero minimum:500 name:BRANCH_PREDICTED_TAKEN :Predicted taken conditional branch
+
+# Cache access
+event:0x1 counters:1,2,3 um:zero minimum:500 name:RQ_LENGTH :Read queue length
+event:0x2 counters:1,2,3 um:zero minimum:500 name:UNCACHED_RQ_LENGTH :Number of valid uncached entries in read queue
+event:0x3 counters:1,2,3 um:zero minimum:500 name:DCACHE_READ_MISS :Dcache read results in a miss
+
+event:0xa counters:1,2,3 um:zero minimum:500 name:DCACHE_FILLED_SHD_NONC_EXC :Dcache is filled (shared, nonc, exclusive)
+event:0xb counters:1,2,3 um:zero minimum:500 name:DCACHE_FILL_SHARED_LINE :Dcache is filled with shared line
+event:0xc counters:1,2,3 um:zero minimum:500 name:DCACHE_READ_MISS :Dcache read results in a miss
+event:0xf counters:1,2,3 um:zero minimum:500 name:WRITEBACK_RETURNS :Number of instruction returns
+event:0xd counters:1,2,3 um:zero minimum:500 name:VICTIM_WRITEBACK :A writeback occurs due to replacement
+event:0x7 counters:1,2,3 um:zero minimum:500 name:UPGRADE_SHARED_TO_EXCLUSIVE :A line is upgraded from shared to exclusive
+event:0x6 counters:1,2,3 um:zero minimum:500 name:LD_ST_HITS_PREFETCH_IN_QUEUE :Load/store hits prefetch in read queue
+event:0x5 counters:1,2,3 um:zero minimum:500 name:PREFETCH_HITS_CACHE_OR_READ_Q :Prefetch hits in cache or read queue
+event:0x4 counters:1,2,3 um:zero minimum:500 name:READ_HITS_READ_Q :Read hits in read queue
+
+# BIU
+
+event:0x11 counters:1,2,3 um:zero minimum:500 name:BIU_STALLS_ON_ZB_ADDR_BUS :BIU stalls on ZB addr bus
+event:0x12 counters:1,2,3 um:zero minimum:500 name:BIU_STALLS_ON_ZB_DATA_BUS :BIU stalls on ZB data bus
+event:0x13 counters:1,2,3 um:zero minimum:500 name:READ_RQ_SENT_TO_ABUS :Requests sent to ZB Abus
+event:0x14 counters:1,2,3 um:zero minimum:500 name:READ_RQ_NOPS_SENT_TO_ABUS :Read requests and NOPs sent to ZB Abus
+event:0x15 counters:1,2,3 um:zero minimum:500 name:READ_RQ_SENT_TO_ABUS :Read requests sent to ZB Abus
+event:0x16 counters:1,2,3 um:zero minimum:500 name:MBOX_RQ_WHEN_BIU_BUSY :MBOX requests to BIU when BIU busy
+
+# Multiprocessor
+event:0x1a counters:1,2,3 um:zero minimum:500 name:STORE_COND_FAILED :Failed store conditional
+event:0x16 counters:1,2,3 um:zero minimum:500 name:SNOOP_RQ_HITS :Snoop request hits anywhere
+event:0x17 counters:1,2,3 um:zero minimum:500 name:SNOOP_ADDR_Q_FULL :Snoop address queue is full
+event:0x18 counters:1,2,3 um:zero minimum:500 name:R_RESP_OTHER_CORE :Read response comes from the other core
+event:0x19 counters:1,2,3 um:zero minimum:500 name:R_RESP_OTHER_CORE_D_MOD :Read response comes from the other core with D_MOD set
+
+# Instruction Counts
+event:0x8 counters:1,2,3 um:zero minimum:500 name:LOAD_SURVIVED_STAGE4 :Load survived stage 4
+event:0x9 counters:1,2,3 um:zero minimum:500 name:STORE_SURVIVED_STAGE4 :Store survived stage 4
+event:0x0 counters:1,2,3 um:zero minimum:500 name:INSN_SURVIVED_STAGE7 :Instruction survived stage 7
diff --git a/events/mips/sb1/unit_masks b/events/mips/sb1/unit_masks
new file mode 100644
index 0000000..7fd41fb
--- /dev/null
+++ b/events/mips/sb1/unit_masks
@@ -0,0 +1,5 @@
+#
+# Sibyte SB1 possible unit masks
+#
+name:zero type:mandatory default:0x0
+ 0x0 No unit mask
diff --git a/events/mips/vr5432/events b/events/mips/vr5432/events
new file mode 100644
index 0000000..31bd827
--- /dev/null
+++ b/events/mips/vr5432/events
@@ -0,0 +1,14 @@
+#
+# VR5432 events
+#
+event:0x0 counters:0,1 um:zero minimum:500 name:CYCLES : Processor cycles (PClock)
+event:0x1 counters:0,1 um:zero minimum:500 name:INSTRUCTIONS_EXECUTED : (Instructions executed)/2 and truncated
+event:0x2 counters:0,1 um:zero minimum:500 name:LOAD_PREF_CACHE_INSTRUCTIONS : Load, prefetch/CacheOps execution (no sync)
+event:0x3 counters:0,1 um:zero minimum:500 name:STORES : Store execution
+event:0x4 counters:0,1 um:zero minimum:500 name:BRANCHES : Branch execution (no jumps or jump registers)
+event:0x5 counters:0,1 um:zero minimum:500 name:FP_INSTRUCTIONS : (FP instruction execution) / 2 and truncated excluding cp1 loads and stores
+event:0x6 counters:0,1 um:zero minimum:500 name:DOUBLEWORDS_FLUSHED : Doublewords flushed to main memory (no uncached stores)
+event:0x7 counters:0,1 um:zero minimum:500 name:JTLB_REFILLS : JTLB refills
+event:0x8 counters:0,1 um:zero minimum:500 name:DCACHE_MISSES : Data cache misses (no I-cache misses)
+event:0x9 counters:0,1 um:zero minimum:500 name:ICACHE_MISSES : Instruction cache misses (no D-cache misses)
+event:0xa counters:0,1 um:zero minimum:500 name:BRANCHES_MISPREDICTED : Branches mispredicted
diff --git a/events/mips/vr5432/unit_masks b/events/mips/vr5432/unit_masks
new file mode 100644
index 0000000..2239d12
--- /dev/null
+++ b/events/mips/vr5432/unit_masks
@@ -0,0 +1,5 @@
+#
+# MIPS VR5432 possible unit masks
+#
+name:zero type:mandatory default:0x0
+ 0x0 No unit mask
diff --git a/events/mips/vr5500/events b/events/mips/vr5500/events
new file mode 100644
index 0000000..c540176
--- /dev/null
+++ b/events/mips/vr5500/events
@@ -0,0 +1,16 @@
+#
+# VR5500, VR5532 and VR7701 events
+#
+# Very similar to what the VR5432 provides.
+#
+event:0x0 counters:0,1 um:zero minimum:500 name:CYCLES : Processor clock cycles
+event:0x1 counters:0,1 um:zero minimum:500 name:INSTRUCTIONS_EXECUTED : Instructions executed
+event:0x2 counters:0,1 um:zero minimum:500 name:LOAD_PREF_CACHE_INSTRUCTIONS : Execution of load/prefetch/cache instruction
+event:0x3 counters:0,1 um:zero minimum:500 name:STORES : Execution of store instruction
+event:0x4 counters:0,1 um:zero minimum:500 name:BRANCHES : Execution of branch instruction
+event:0x5 counters:0,1 um:zero minimum:500 name:FP_INSTRUCTIONS : Execution of floating-point instruction
+event:0x6 counters:0,1 um:zero minimum:500 name:DOUBLEWORDS_FLUSHED : Doubleword flush to main memory
+event:0x7 counters:0,1 um:zero minimum:500 name:JTLB_REFILLS : TLB refill
+event:0x8 counters:0,1 um:zero minimum:500 name:DCACHE_MISSES : Data cache miss
+event:0x9 counters:0,1 um:zero minimum:500 name:ICACHE_MISSES : Instruction cache miss
+event:0xa counters:0,1 um:zero minimum:500 name:BRANCHES_MISPREDICTED : Branch prediction miss
diff --git a/events/mips/vr5500/unit_masks b/events/mips/vr5500/unit_masks
new file mode 100644
index 0000000..ef69a7a
--- /dev/null
+++ b/events/mips/vr5500/unit_masks
@@ -0,0 +1,5 @@
+#
+# MIPS VR5500 possible unit masks
+#
+name:zero type:mandatory default:0x0
+ 0x0 No unit mask