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# VR5432 events
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event:0 counters:0,1 um:zero minimum:500 name:CYCLES : Processor cycles (PClock)
event:1 counters:0,1 um:zero minimum:500 name:INSTRUCTIONS_EXECUTED : (Instructions executed)/2 and truncated
event:2 counters:0,1 um:zero minimum:500 name:LOAD_PREF_CACHE_INSTRUCTIONS : Load, prefetch/CacheOps execution (no sync)
event:3 counters:0,1 um:zero minimum:500 name:STORES : Store execution
event:4 counters:0,1 um:zero minimum:500 name:BRANCHES : Branch execution (no jumps or jump registers)
event:5 counters:0,1 um:zero minimum:500 name:FP_INSTRUCTIONS : (FP instruction execution) / 2 and truncated excluding cp1 loads and stores
event:6 counters:0,1 um:zero minimum:500 name:DOUBLEWORDS_FLUSHED : Doublewords flushed to main memory (no uncached stores)
event:7 counters:0,1 um:zero minimum:500 name:JTLB_REFILLS : JTLB refills
event:8 counters:0,1 um:zero minimum:500 name:DCACHE_MISSES : Data cache misses (no I-cache misses)
event:9 counters:0,1 um:zero minimum:500 name:ICACHE_MISSES : Instruction cache misses (no D-cache misses)
event:10 counters:0,1 um:zero minimum:500 name:BRANCHES_MISPREDICTED : Branches mispredicted