include/exec: Mist minor integrations.
Change-Id: I4b775eac3ef81f466cebd52ecbaab2c94494944f
diff --git a/cpu-exec.c b/cpu-exec.c
index d658576..a3a13e9 100644
--- a/cpu-exec.c
+++ b/cpu-exec.c
@@ -56,10 +56,10 @@
return cpu_has_work(env);
}
-void cpu_loop_exit(void)
+void cpu_loop_exit(CPUArchState* env1)
{
- env->current_tb = NULL;
- longjmp(env->jmp_env, 1);
+ env1->current_tb = NULL;
+ longjmp(env1->jmp_env, 1);
}
/* exit the current TB from a signal handler. The host registers are
@@ -394,7 +394,7 @@
if (interrupt_request & CPU_INTERRUPT_DEBUG) {
env->interrupt_request &= ~CPU_INTERRUPT_DEBUG;
env->exception_index = EXCP_DEBUG;
- cpu_loop_exit();
+ cpu_loop_exit(env);
}
#if defined(TARGET_ARM) || defined(TARGET_SPARC) || defined(TARGET_MIPS) || \
defined(TARGET_PPC) || defined(TARGET_ALPHA) || defined(TARGET_CRIS) || \
@@ -403,7 +403,7 @@
env->interrupt_request &= ~CPU_INTERRUPT_HALT;
env->halted = 1;
env->exception_index = EXCP_HLT;
- cpu_loop_exit();
+ cpu_loop_exit(env);
}
#endif
#if defined(TARGET_I386)
@@ -411,7 +411,7 @@
svm_check_intercept(SVM_EXIT_INIT);
do_cpu_init(env);
env->exception_index = EXCP_HALTED;
- cpu_loop_exit();
+ cpu_loop_exit(env);
} else if (interrupt_request & CPU_INTERRUPT_SIPI) {
do_cpu_sipi(env);
} else if (env->hflags2 & HF2_GIF_MASK) {
@@ -604,7 +604,7 @@
if (unlikely(env->exit_request)) {
env->exit_request = 0;
env->exception_index = EXCP_INTERRUPT;
- cpu_loop_exit();
+ cpu_loop_exit(env);
}
#if defined(DEBUG_DISAS) || defined(CONFIG_DEBUG_EXEC)
if (qemu_loglevel_mask(CPU_LOG_TB_CPU)) {
@@ -687,14 +687,14 @@
}
env->exception_index = EXCP_INTERRUPT;
next_tb = 0;
- cpu_loop_exit();
+ cpu_loop_exit(env);
}
}
}
env->current_tb = NULL;
#ifdef CONFIG_HAX
if (hax_enabled() && hax_stop_emulation(env))
- cpu_loop_exit();
+ cpu_loop_exit(env);
#endif
/* reset soft MMU for next block (it can currently
only be set by a memory fault) */
@@ -799,7 +799,7 @@
#if defined(TARGET_I386)
#define EXCEPTION_ACTION raise_exception_err(env->exception_index, env->error_code)
#else
-#define EXCEPTION_ACTION cpu_loop_exit()
+#define EXCEPTION_ACTION cpu_loop_exit(env)
#endif
/* 'pc' is the host PC at which the exception was raised. 'address' is
diff --git a/exec.c b/exec.c
index 609c4c7..2f44aa4 100644
--- a/exec.c
+++ b/exec.c
@@ -749,7 +749,7 @@
tb_set_jmp_target(tb, n, (unsigned long)(tb->tc_ptr + tb->tb_next_offset[n]));
}
-void tb_phys_invalidate(TranslationBlock *tb, target_ulong page_addr)
+void tb_phys_invalidate(TranslationBlock *tb, tb_page_addr_t page_addr)
{
CPUArchState *env;
PageDesc *p;
@@ -1326,6 +1326,18 @@
}
#endif
+#if defined(CONFIG_USER_ONLY)
+void cpu_watchpoint_remove_all(CPUArchState *env, int mask)
+
+{
+}
+
+int cpu_watchpoint_insert(CPUArchState *env, target_ulong addr, target_ulong len,
+ int flags, CPUWatchpoint **watchpoint)
+{
+ return -ENOSYS;
+}
+#else
/* Add a watchpoint. */
int cpu_watchpoint_insert(CPUArchState *env, target_ulong addr, target_ulong len,
int flags, CPUWatchpoint **watchpoint)
@@ -1334,7 +1346,8 @@
CPUWatchpoint *wp;
/* sanity checks: allow power-of-2 lengths, deny unaligned watchpoints */
- if ((len != 1 && len != 2 && len != 4 && len != 8) || (addr & ~len_mask)) {
+ if ((len & (len - 1)) || (addr & ~len_mask) ||
+ len == 0 || len > TARGET_PAGE_SIZE) {
fprintf(stderr, "qemu: tried to set invalid watchpoint at "
TARGET_FMT_lx ", len=" TARGET_FMT_lu "\n", addr, len);
return -EINVAL;
@@ -1395,6 +1408,7 @@
cpu_watchpoint_remove_by_ref(env, wp);
}
}
+#endif
/* Add a breakpoint. */
int cpu_breakpoint_insert(CPUArchState *env, target_ulong pc, int flags,
@@ -1409,15 +1423,17 @@
bp->flags = flags;
/* keep all GDB-injected breakpoints in front */
- if (flags & BP_GDB)
+ if (flags & BP_GDB) {
QTAILQ_INSERT_HEAD(&env->breakpoints, bp, entry);
- else
+ } else {
QTAILQ_INSERT_TAIL(&env->breakpoints, bp, entry);
+ }
breakpoint_invalidate(env, pc);
- if (breakpoint)
+ if (breakpoint) {
*breakpoint = bp;
+ }
return 0;
#else
return -ENOSYS;
@@ -1586,7 +1602,7 @@
cpu_unlink_tb(env);
}
-void cpu_abort(CPUOldState *env, const char *fmt, ...)
+void cpu_abort(CPUArchState *env, const char *fmt, ...)
{
va_list ap;
va_list ap2;
@@ -1911,7 +1927,7 @@
/* called from signal handler: invalidate the code and unprotect the
page. Return TRUE if the fault was successfully handled. */
-int page_unprotect(target_ulong address, unsigned long pc, void *puc)
+int page_unprotect(target_ulong address, uintptr_t pc, void *puc)
{
unsigned int page_index, prot, pindex;
PageDesc *p, *p1;
@@ -2567,7 +2583,7 @@
/* Generate a debug exception if a watchpoint has been hit. */
static void check_watchpoint(int offset, int len_mask, int flags)
{
- CPUOldState *env = cpu_single_env;
+ CPUArchState *env = cpu_single_env;
target_ulong pc, cs_base;
TranslationBlock *tb;
target_ulong vaddr;
@@ -2597,11 +2613,12 @@
tb_phys_invalidate(tb, -1);
if (wp->flags & BP_STOP_BEFORE_ACCESS) {
env->exception_index = EXCP_DEBUG;
+ cpu_loop_exit(env);
} else {
cpu_get_tb_cpu_state(env, &pc, &cs_base, &cpu_flags);
tb_gen_code(env, pc, cs_base, cpu_flags, 1);
+ cpu_resume_from_signal(env, NULL);
}
- cpu_resume_from_signal(env, NULL);
}
} else {
wp->flags &= ~BP_WATCHPOINT_HIT;
@@ -3468,20 +3485,20 @@
/* in deterministic execution mode, instructions doing device I/Os
must be at the end of the TB */
-void cpu_io_recompile(CPUArchState *env, void *retaddr)
+void cpu_io_recompile(CPUArchState *env, uintptr_t retaddr)
{
TranslationBlock *tb;
uint32_t n, cflags;
target_ulong pc, cs_base;
uint64_t flags;
- tb = tb_find_pc((unsigned long)retaddr);
+ tb = tb_find_pc(retaddr);
if (!tb) {
cpu_abort(env, "cpu_io_recompile: could not find TB for pc=%p",
- retaddr);
+ (void*)retaddr);
}
n = env->icount_decr.u16.low + tb->icount;
- cpu_restore_state(tb, env, (unsigned long)retaddr);
+ cpu_restore_state(tb, env, retaddr);
/* Calculate how many instructions had been executed before the fault
occurred. */
n = n - env->icount_decr.u16.low;
diff --git a/hw/android/goldfish/trace.c b/hw/android/goldfish/trace.c
index 7cc4347..d9f550f 100644
--- a/hw/android/goldfish/trace.c
+++ b/hw/android/goldfish/trace.c
@@ -43,7 +43,7 @@
// TODO(digit): Re-enable tracing some day?
#define tracing 0
-extern void cpu_loop_exit(void);
+extern void cpu_loop_exit(CPUArchState* env);
extern const char *trace_filename;
@@ -255,7 +255,7 @@
cpu_single_env->exception_index = EXCP_HLT;
cpu_single_env->halted = 1;
qemu_system_shutdown_request();
- cpu_loop_exit();
+ cpu_loop_exit(cpu_single_env);
break;
case TRACE_DEV_REG_ENABLE: // tracing enable: 0 = stop, 1 = start
diff --git a/include/exec/exec-all.h b/include/exec/exec-all.h
index 6822d44..5de8255 100644
--- a/include/exec/exec-all.h
+++ b/include/exec/exec-all.h
@@ -79,16 +79,16 @@
void cpu_gen_init(void);
int cpu_gen_code(CPUArchState *env, struct TranslationBlock *tb,
int *gen_code_size_ptr);
-int cpu_restore_state(struct TranslationBlock *tb,
- CPUArchState *env, unsigned long searched_pc);
+bool cpu_restore_state(struct TranslationBlock *tb,
+ CPUArchState *env, uintptr_t searched_pc);
void QEMU_NORETURN cpu_resume_from_signal(CPUArchState *env1, void *puc);
-void QEMU_NORETURN cpu_io_recompile(CPUArchState *env, void *retaddr);
+void QEMU_NORETURN cpu_io_recompile(CPUArchState *env, uintptr_t retaddr);
TranslationBlock *tb_gen_code(CPUArchState *env,
target_ulong pc, target_ulong cs_base, int flags,
int cflags);
void cpu_exec_init(CPUArchState *env);
-void QEMU_NORETURN cpu_loop_exit(void);
-int page_unprotect(target_ulong address, unsigned long pc, void *puc);
+void QEMU_NORETURN cpu_loop_exit(CPUArchState *env1);
+int page_unprotect(target_ulong address, uintptr_t pc, void *puc);
void tb_invalidate_phys_page_range(hwaddr start, hwaddr end,
int is_cpu_write_access);
void tb_invalidate_page_range(target_ulong start, target_ulong end);
@@ -150,7 +150,7 @@
/* first and second physical page containing code. The lower bit
of the pointer tells the index in page_next[] */
struct TranslationBlock *page_next[2];
- target_ulong page_addr[2];
+ tb_page_addr_t page_addr[2];
/* the following data are used to directly call another TB from
the code of this one. */
@@ -158,7 +158,7 @@
#ifdef USE_DIRECT_JUMP
uint16_t tb_jmp_offset[4]; /* offset of jump instruction */
#else
- unsigned long tb_next[2]; /* address of jump generated code */
+ uintptr_t tb_next[2]; /* address of jump generated code */
#endif
/* list of TBs jumping to this one. This is a circular list using
the two least significant bits of the pointers to tell what is
@@ -196,7 +196,7 @@
| (tmp & TB_JMP_ADDR_MASK));
}
-static inline unsigned int tb_phys_hash_func(unsigned long pc)
+static inline unsigned int tb_phys_hash_func(tb_page_addr_t pc)
{
return (pc >> 2) & (CODE_GEN_PHYS_HASH_SIZE - 1);
}
@@ -260,7 +260,7 @@
void tb_flush(CPUArchState *env);
void tb_link_phys(TranslationBlock *tb,
target_ulong phys_pc, target_ulong phys_page2);
-void tb_phys_invalidate(TranslationBlock *tb, target_ulong page_addr);
+void tb_phys_invalidate(TranslationBlock *tb, tb_page_addr_t page_addr);
extern TranslationBlock *tb_phys_hash[CODE_GEN_PHYS_HASH_SIZE];
extern uint8_t *code_gen_ptr;
@@ -268,22 +268,30 @@
#if defined(USE_DIRECT_JUMP)
-#if defined(_ARCH_PPC)
-extern void ppc_tb_set_jmp_target(unsigned long jmp_addr, unsigned long addr);
-#define tb_set_jmp_target1 ppc_tb_set_jmp_target
-#elif defined(__i386__) || defined(__x86_64__)
-static inline void tb_set_jmp_target1(unsigned long jmp_addr, unsigned long addr)
+#if defined(CONFIG_TCG_INTERPRETER)
+static inline void tb_set_jmp_target1(uintptr_t jmp_addr, uintptr_t addr)
{
/* patch the branch destination */
*(uint32_t *)jmp_addr = addr - (jmp_addr + 4);
/* no need to flush icache explicitly */
}
-#elif defined(__arm__)
-static inline void tb_set_jmp_target1(unsigned long jmp_addr, unsigned long addr)
+#elif defined(_ARCH_PPC)
+void ppc_tb_set_jmp_target(unsigned long jmp_addr, unsigned long addr);
+#define tb_set_jmp_target1 ppc_tb_set_jmp_target
+#elif defined(__i386__) || defined(__x86_64__)
+static inline void tb_set_jmp_target1(uintptr_t jmp_addr, uintptr_t addr)
{
-#if QEMU_GNUC_PREREQ(4, 1)
- void __clear_cache(char *beg, char *end);
-#else
+ /* patch the branch destination */
+ *(uint32_t *)jmp_addr = addr - (jmp_addr + 4);
+ /* no need to flush icache explicitly */
+}
+#elif defined(__aarch64__)
+void aarch64_tb_set_jmp_target(uintptr_t jmp_addr, uintptr_t addr);
+#define tb_set_jmp_target1 aarch64_tb_set_jmp_target
+#elif defined(__arm__)
+static inline void tb_set_jmp_target1(uintptr_t jmp_addr, uintptr_t addr)
+{
+#if !QEMU_GNUC_PREREQ(4, 1)
register unsigned long _beg __asm ("a1");
register unsigned long _end __asm ("a2");
register unsigned long _flg __asm ("a3");
@@ -295,7 +303,7 @@
| (((addr - (jmp_addr + 8)) >> 2) & 0xffffff);
#if QEMU_GNUC_PREREQ(4, 1)
- __clear_cache((char *) jmp_addr, (char *) jmp_addr + 4);
+ __builtin___clear_cache((char *) jmp_addr, (char *) jmp_addr + 4);
#else
/* flush icache */
_beg = jmp_addr;
@@ -304,25 +312,27 @@
__asm __volatile__ ("swi 0x9f0002" : : "r" (_beg), "r" (_end), "r" (_flg));
#endif
}
+#elif defined(__sparc__)
+void tb_set_jmp_target1(uintptr_t jmp_addr, uintptr_t addr);
+#else
+#error tb_set_jmp_target1 is missing
#endif
static inline void tb_set_jmp_target(TranslationBlock *tb,
- int n, unsigned long addr)
+ int n, uintptr_t addr)
{
- unsigned long offset;
-
- offset = tb->tb_jmp_offset[n];
- tb_set_jmp_target1((unsigned long)(tb->tc_ptr + offset), addr);
+ uint16_t offset = tb->tb_jmp_offset[n];
+ tb_set_jmp_target1((uintptr_t)(tb->tc_ptr + offset), addr);
offset = tb->tb_jmp_offset[n + 2];
if (offset != 0xffff)
- tb_set_jmp_target1((unsigned long)(tb->tc_ptr + offset), addr);
+ tb_set_jmp_target1((uintptr_t)(tb->tc_ptr + offset), addr);
}
#else
/* set the jump target */
static inline void tb_set_jmp_target(TranslationBlock *tb,
- int n, unsigned long addr)
+ int n, uintptr_t addr)
{
tb->tb_next[n] = addr;
}
@@ -335,11 +345,11 @@
/* NOTE: this test is only needed for thread safety */
if (!tb->jmp_next[n]) {
/* patch the native jump address */
- tb_set_jmp_target(tb, n, (unsigned long)tb_next->tc_ptr);
+ tb_set_jmp_target(tb, n, (uintptr_t)tb_next->tc_ptr);
/* add in TB jmp circular list */
tb->jmp_next[n] = tb_next->jmp_first;
- tb_next->jmp_first = (TranslationBlock *)((long)(tb) | (n));
+ tb_next->jmp_first = (TranslationBlock *)((uintptr_t)(tb) | (n));
}
}
@@ -429,13 +439,13 @@
instruction of a TB so that interrupts take effect immediately. */
static inline int can_do_io(CPUArchState *env)
{
- if (!use_icount)
+ if (!use_icount) {
return 1;
-
+ }
/* If not executing code then assume we are ok. */
- if (!env->current_tb)
+ if (!env->current_tb) {
return 1;
-
+ }
return env->can_do_io != 0;
}
diff --git a/include/exec/gdbstub.h b/include/exec/gdbstub.h
index dd96c6c..79c637d 100644
--- a/include/exec/gdbstub.h
+++ b/include/exec/gdbstub.h
@@ -23,11 +23,11 @@
#ifdef CONFIG_USER_ONLY
int gdb_queuesig (void);
int gdb_handlesig (CPUOldState *, int);
-void gdb_signalled(CPUOldState *, int);
-void gdbserver_fork(CPUOldState *);
+void gdb_signalled(CPUArchState *, int);
+void gdbserver_fork(CPUArchState *);
#endif
/* Get or set a register. Returns the size of the register. */
-typedef int (*gdb_reg_cb)(CPUOldState *env, uint8_t *buf, int reg);
+typedef int (*gdb_reg_cb)(CPUArchState *env, uint8_t *buf, int reg);
void gdb_register_coprocessor(CPUOldState *env,
gdb_reg_cb get_reg, gdb_reg_cb set_reg,
int num_regs, const char *xml, int g_pos);
diff --git a/include/exec/gen-icount.h b/include/exec/gen-icount.h
index 14e0200..fd62e69 100644
--- a/include/exec/gen-icount.h
+++ b/include/exec/gen-icount.h
@@ -1,3 +1,6 @@
+#ifndef GEN_ICOUNT_H
+#define GEN_ICOUNT_H 1
+
#include "qemu/timer.h"
/* Helpers for instruction counting code generation. */
@@ -29,7 +32,7 @@
if (use_icount) {
*icount_arg = num_insns;
gen_set_label(icount_label);
- tcg_gen_exit_tb((tcg_target_long)tb + 2);
+ tcg_gen_exit_tb((uintptr_t)tb + 2);
}
}
@@ -46,3 +49,5 @@
tcg_gen_st_i32(tmp, cpu_env, offsetof(CPUArchState, can_do_io));
tcg_temp_free_i32(tmp);
}
+
+#endif
diff --git a/include/exec/softmmu-semi.h b/include/exec/softmmu-semi.h
index 73f09aa..7d484ca 100644
--- a/include/exec/softmmu-semi.h
+++ b/include/exec/softmmu-semi.h
@@ -4,17 +4,19 @@
*
* Copyright (c) 2007 CodeSourcery.
*
- * This code is licenced under the GPL
+ * This code is licensed under the GPL
*/
+#ifndef SOFTMMU_SEMI_H
+#define SOFTMMU_SEMI_H 1
-static inline uint32_t softmmu_tget32(CPUOldState *env, uint32_t addr)
+static inline uint32_t softmmu_tget32(CPUArchState *env, uint32_t addr)
{
uint32_t val;
cpu_memory_rw_debug(env, addr, (uint8_t *)&val, 4, 0);
return tswap32(val);
}
-static inline uint32_t softmmu_tget8(CPUOldState *env, uint32_t addr)
+static inline uint32_t softmmu_tget8(CPUArchState *env, uint32_t addr)
{
uint8_t val;
@@ -26,7 +28,7 @@
#define get_user_u8(arg, p) ({ arg = softmmu_tget8(env, p) ; 0; })
#define get_user_ual(arg, p) get_user_u32(arg, p)
-static inline void softmmu_tput32(CPUOldState *env, uint32_t addr, uint32_t val)
+static inline void softmmu_tput32(CPUArchState *env, uint32_t addr, uint32_t val)
{
val = tswap32(val);
cpu_memory_rw_debug(env, addr, (uint8_t *)&val, 4, 1);
@@ -34,24 +36,28 @@
#define put_user_u32(arg, p) ({ softmmu_tput32(env, p, arg) ; 0; })
#define put_user_ual(arg, p) put_user_u32(arg, p)
-static void *softmmu_lock_user(CPUOldState *env, uint32_t addr, uint32_t len,
+static void *softmmu_lock_user(CPUArchState *env, uint32_t addr, uint32_t len,
int copy)
{
uint8_t *p;
/* TODO: Make this something that isn't fixed size. */
p = malloc(len);
- if (copy)
+ if (p && copy) {
cpu_memory_rw_debug(env, addr, p, len, 0);
+ }
return p;
}
#define lock_user(type, p, len, copy) softmmu_lock_user(env, p, len, copy)
-static char *softmmu_lock_user_string(CPUOldState *env, uint32_t addr)
+static char *softmmu_lock_user_string(CPUArchState *env, uint32_t addr)
{
char *p;
char *s;
uint8_t c;
/* TODO: Make this something that isn't fixed size. */
s = p = malloc(1024);
+ if (!s) {
+ return NULL;
+ }
do {
cpu_memory_rw_debug(env, addr, &c, 1, 0);
addr++;
@@ -60,11 +66,14 @@
return s;
}
#define lock_user_string(p) softmmu_lock_user_string(env, p)
-static void softmmu_unlock_user(CPUOldState *env, void *p, target_ulong addr,
+static void softmmu_unlock_user(CPUArchState *env, void *p, target_ulong addr,
target_ulong len)
{
- if (len)
+ if (len) {
cpu_memory_rw_debug(env, addr, p, len, 1);
+ }
free(p);
}
#define unlock_user(s, args, len) softmmu_unlock_user(env, s, args, len)
+
+#endif
diff --git a/include/exec/softmmu_header.h b/include/exec/softmmu_header.h
index 0b6082d..82916bd 100644
--- a/include/exec/softmmu_header.h
+++ b/include/exec/softmmu_header.h
@@ -1,6 +1,15 @@
/*
* Software MMU support
*
+ * Generate inline load/store functions for one MMU mode and data
+ * size.
+ *
+ * Generate a store function as well as signed and unsigned loads. For
+ * 32 and 64 bit cases, also generate floating point functions with
+ * the same size.
+ *
+ * Not used directly but included from softmmu_exec.h and exec-all.h.
+ *
* Copyright (c) 2003 Fabrice Bellard
*
* This library is free software; you can redistribute it and/or
diff --git a/include/exec/softmmu_template.h b/include/exec/softmmu_template.h
index c3a88a5..66f2844 100644
--- a/include/exec/softmmu_template.h
+++ b/include/exec/softmmu_template.h
@@ -1,6 +1,11 @@
/*
* Software MMU support
*
+ * Generate helpers used by TCG for qemu_ld/st ops and code load
+ * functions.
+ *
+ * Included from target op helpers and exec.c.
+ *
* Copyright (c) 2003 Fabrice Bellard
*
* This library is free software; you can redistribute it and/or
@@ -76,7 +81,7 @@
env->mem_io_pc = (unsigned long)retaddr;
if (index > (IO_MEM_NOTDIRTY >> IO_MEM_SHIFT)
&& !can_do_io(env)) {
- cpu_io_recompile(env, retaddr);
+ cpu_io_recompile(env, (uintptr_t)retaddr);
}
env->mem_io_vaddr = addr;
@@ -254,7 +259,7 @@
physaddr = (physaddr & TARGET_PAGE_MASK) + addr;
if (index > (IO_MEM_NOTDIRTY >> IO_MEM_SHIFT)
&& !can_do_io(env)) {
- cpu_io_recompile(env, retaddr);
+ cpu_io_recompile(env, (uintptr_t)retaddr);
}
env->mem_io_vaddr = addr;
diff --git a/target-arm/op_helper.c b/target-arm/op_helper.c
index 2f17894..168edd1 100644
--- a/target-arm/op_helper.c
+++ b/target-arm/op_helper.c
@@ -25,7 +25,7 @@
void raise_exception(int tt)
{
env->exception_index = tt;
- cpu_loop_exit();
+ cpu_loop_exit(env);
}
uint32_t HELPER(neon_tbl)(uint32_t ireg, uint32_t def,
@@ -276,13 +276,13 @@
{
env->exception_index = EXCP_HLT;
env->halted = 1;
- cpu_loop_exit();
+ cpu_loop_exit(env);
}
void HELPER(exception)(uint32_t excp)
{
env->exception_index = excp;
- cpu_loop_exit();
+ cpu_loop_exit(env);
}
uint32_t HELPER(cpsr_read)(void)
diff --git a/target-i386/op_helper.c b/target-i386/op_helper.c
index 0488d2b..2543eb7 100644
--- a/target-i386/op_helper.c
+++ b/target-i386/op_helper.c
@@ -1003,7 +1003,7 @@
{
env->exception_index = EXCP_SYSCALL;
env->exception_next_eip = env->eip + next_eip_addend;
- cpu_loop_exit();
+ cpu_loop_exit(env);
}
#else
void helper_syscall(int next_eip_addend)
@@ -1338,7 +1338,7 @@
env->error_code = error_code;
env->exception_is_int = is_int;
env->exception_next_eip = env->eip + next_eip_addend;
- cpu_loop_exit();
+ cpu_loop_exit(env);
}
/* shortcuts to generate exceptions */
@@ -4640,7 +4640,7 @@
env->hflags &= ~HF_INHIBIT_IRQ_MASK; /* needed if sti is just before */
env->halted = 1;
env->exception_index = EXCP_HLT;
- cpu_loop_exit();
+ cpu_loop_exit(env);
}
void helper_hlt(int next_eip_addend)
@@ -4678,7 +4678,7 @@
void helper_debug(void)
{
env->exception_index = EXCP_DEBUG;
- cpu_loop_exit();
+ cpu_loop_exit(env);
}
void helper_reset_rf(void)
@@ -5040,7 +5040,7 @@
env->exception_is_int = 0;
env->exception_next_eip = EIP;
qemu_log_mask(CPU_LOG_TB_IN_ASM, "NMI");
- cpu_loop_exit();
+ cpu_loop_exit(env);
break;
case SVM_EVTINJ_TYPE_EXEPT:
env->exception_index = vector;
@@ -5048,7 +5048,7 @@
env->exception_is_int = 0;
env->exception_next_eip = -1;
qemu_log_mask(CPU_LOG_TB_IN_ASM, "EXEPT");
- cpu_loop_exit();
+ cpu_loop_exit(env);
break;
case SVM_EVTINJ_TYPE_SOFT:
env->exception_index = vector;
@@ -5056,7 +5056,7 @@
env->exception_is_int = 1;
env->exception_next_eip = EIP;
qemu_log_mask(CPU_LOG_TB_IN_ASM, "SOFT");
- cpu_loop_exit();
+ cpu_loop_exit(env);
break;
}
qemu_log_mask(CPU_LOG_TB_IN_ASM, " %#x %#x\n", env->exception_index, env->error_code);
@@ -5391,7 +5391,7 @@
env->error_code = 0;
env->old_exception = -1;
- cpu_loop_exit();
+ cpu_loop_exit(env);
}
#endif
diff --git a/target-mips/op_helper.c b/target-mips/op_helper.c
index 89ab947..780ad7b 100644
--- a/target-mips/op_helper.c
+++ b/target-mips/op_helper.c
@@ -33,7 +33,7 @@
#endif
env->exception_index = exception;
env->error_code = error_code;
- cpu_loop_exit();
+ cpu_loop_exit(env);
}
void helper_raise_exception (uint32_t exception)
@@ -284,7 +284,7 @@
lladdr = cpu_mips_translate_address(env, address, rw);
if (lladdr == (hwaddr)-1LL) {
- cpu_loop_exit();
+ cpu_loop_exit(env);
} else {
return lladdr;
}
diff --git a/translate-all.c b/translate-all.c
index bb369c0..d284062 100644
--- a/translate-all.c
+++ b/translate-all.c
@@ -171,12 +171,12 @@
/* The cpu state corresponding to 'searched_pc' is restored.
*/
-int cpu_restore_state(TranslationBlock *tb,
- CPUArchState *env, unsigned long searched_pc)
+bool cpu_restore_state(TranslationBlock *tb,
+ CPUArchState *env, uintptr_t searched_pc)
{
TCGContext *s = &tcg_ctx;
int j;
- unsigned long tc_ptr;
+ uintptr_t tc_ptr;
#ifdef CONFIG_PROFILER
int64_t ti;
#endif
@@ -196,7 +196,7 @@
}
/* find opc index corresponding to search_pc */
- tc_ptr = (unsigned long)tb->tc_ptr;
+ tc_ptr = (uintptr_t)tb->tc_ptr;
if (searched_pc < tc_ptr)
return -1;
@@ -210,7 +210,7 @@
#endif
j = tcg_gen_code_search_pc(s, (uint8_t *)tc_ptr, searched_pc - tc_ptr);
if (j < 0)
- return -1;
+ return false;
/* now find start of instruction before */
while (gen_opc_instr_start[j] == 0)
j--;
@@ -222,7 +222,7 @@
s->restore_time += profile_getclock() - ti;
s->restore_count++;
#endif
- return 0;
+ return true;
}
void tb_flush_jmp_cache(CPUArchState *env, target_ulong addr)