rename target_phy_addr_t to hwaddr to match upstream.
Upstream got rid of the target_phys_addr_t and replaced it with 'hwaddr',
so do the corresponding rename here. Note that:
- This also renames <exec/targphys.h> to <exec/hwaddr.h>
- Upstream always deins hwaddr as a 64-bit type, while the size of
our own hwaddr is still controlled by TARGET_PHYS_ADDR_BITS, and
will be 32 for now.
A future patch will change the type definition to fully match
upstream, but it is more risky / requires more cleanups. It's
simply cleaner / simpler to put the related work in a separate
patch, given the large number of sources touched by the
current change.
Change-Id: Iee30869a57798c12109b6a23570b166232bb9244
diff --git a/dma-helpers.c b/dma-helpers.c
index 280ace4..29b3138 100644
--- a/dma-helpers.c
+++ b/dma-helpers.c
@@ -18,8 +18,8 @@
qsg->size = 0;
}
-void qemu_sglist_add(QEMUSGList *qsg, target_phys_addr_t base,
- target_phys_addr_t len)
+void qemu_sglist_add(QEMUSGList *qsg, hwaddr base,
+ hwaddr len)
{
if (qsg->nsg == qsg->nalloc) {
qsg->nalloc = 2 * qsg->nalloc + 1;
@@ -44,7 +44,7 @@
uint64_t sector_num;
int is_write;
int sg_cur_index;
- target_phys_addr_t sg_cur_byte;
+ hwaddr sg_cur_byte;
QEMUIOVector iov;
QEMUBH *bh;
} DMAAIOCB;
@@ -82,7 +82,7 @@
static void dma_bdrv_cb(void *opaque, int ret)
{
DMAAIOCB *dbs = (DMAAIOCB *)opaque;
- target_phys_addr_t cur_addr, cur_len;
+ hwaddr cur_addr, cur_len;
void *mem;
dbs->acb = NULL;
diff --git a/exec.c b/exec.c
index f054039..cd693b2 100644
--- a/exec.c
+++ b/exec.c
@@ -202,7 +202,7 @@
#define SUBPAGE_IDX(addr) ((addr) & ~TARGET_PAGE_MASK)
typedef struct subpage_t {
- target_phys_addr_t base;
+ hwaddr base;
CPUReadMemoryFunc **mem_read[TARGET_PAGE_SIZE][4];
CPUWriteMemoryFunc **mem_write[TARGET_PAGE_SIZE][4];
void *opaque[TARGET_PAGE_SIZE][2][4];
@@ -344,7 +344,7 @@
return p + (index & (L2_SIZE - 1));
}
-static PhysPageDesc *phys_page_find_alloc(target_phys_addr_t index, int alloc)
+static PhysPageDesc *phys_page_find_alloc(hwaddr index, int alloc)
{
void **lp, **p;
PhysPageDesc *pd;
@@ -383,7 +383,7 @@
return ((PhysPageDesc *)pd) + (index & (L2_SIZE - 1));
}
-static inline PhysPageDesc *phys_page_find(target_phys_addr_t index)
+static inline PhysPageDesc *phys_page_find(hwaddr index)
{
return phys_page_find_alloc(index, 0);
}
@@ -784,7 +784,7 @@
CPUState *env;
PageDesc *p;
unsigned int h, n1;
- target_phys_addr_t phys_pc;
+ hwaddr phys_pc;
TranslationBlock *tb1, *tb2;
/* remove the TB from the hash list */
@@ -944,7 +944,7 @@
the same physical page. 'is_cpu_write_access' should be true if called
from a real cpu write access: the virtual CPU will exit the current
TB if code is modified inside this TB. */
-void tb_invalidate_phys_page_range(target_phys_addr_t start, target_phys_addr_t end,
+void tb_invalidate_phys_page_range(hwaddr start, hwaddr end,
int is_cpu_write_access)
{
TranslationBlock *tb, *tb_next, *saved_tb;
@@ -1050,7 +1050,7 @@
}
/* len must be <= 8 and start must be a multiple of len */
-static inline void tb_invalidate_phys_page_fast(target_phys_addr_t start, int len)
+static inline void tb_invalidate_phys_page_fast(hwaddr start, int len)
{
PageDesc *p;
int offset, b;
@@ -1077,7 +1077,7 @@
}
#if !defined(CONFIG_SOFTMMU)
-static void tb_invalidate_phys_page(target_phys_addr_t addr,
+static void tb_invalidate_phys_page(hwaddr addr,
unsigned long pc, void *puc)
{
TranslationBlock *tb;
@@ -1343,7 +1343,7 @@
#if defined(TARGET_HAS_ICE)
static void breakpoint_invalidate(CPUState *env, target_ulong pc)
{
- target_phys_addr_t addr;
+ hwaddr addr;
target_ulong pd;
ram_addr_t ram_addr;
PhysPageDesc *p;
@@ -1928,8 +1928,8 @@
return in_migration;
}
-int cpu_physical_sync_dirty_bitmap(target_phys_addr_t start_addr,
- target_phys_addr_t end_addr)
+int cpu_physical_sync_dirty_bitmap(hwaddr start_addr,
+ hwaddr end_addr)
{
int ret = 0;
@@ -1988,7 +1988,7 @@
(can only happen in non SOFTMMU mode for I/O pages or pages
conflicting with the host address space). */
int tlb_set_page_exec(CPUState *env, target_ulong vaddr,
- target_phys_addr_t paddr, int prot,
+ hwaddr paddr, int prot,
int mmu_idx, int is_softmmu)
{
PhysPageDesc *p;
@@ -2000,7 +2000,7 @@
int ret;
CPUTLBEntry *te;
CPUWatchpoint *wp;
- target_phys_addr_t iotlb;
+ hwaddr iotlb;
p = phys_page_find(paddr >> TARGET_PAGE_BITS);
if (!p) {
@@ -2128,7 +2128,7 @@
}
int tlb_set_page_exec(CPUState *env, target_ulong vaddr,
- target_phys_addr_t paddr, int prot,
+ hwaddr paddr, int prot,
int mmu_idx, int is_softmmu)
{
return 0;
@@ -2336,7 +2336,7 @@
static int subpage_register (subpage_t *mmio, uint32_t start, uint32_t end,
ram_addr_t memory, ram_addr_t region_offset);
-static void *subpage_init (target_phys_addr_t base, ram_addr_t *phys,
+static void *subpage_init (hwaddr base, ram_addr_t *phys,
ram_addr_t orig_memory, ram_addr_t region_offset);
#define CHECK_SUBPAGE(addr, start_addr, start_addr2, end_addr, end_addr2, \
need_subpage) \
@@ -2366,13 +2366,13 @@
start_addr and region_offset are rounded down to a page boundary
before calculating this offset. This should not be a problem unless
the low bits of start_addr and region_offset differ. */
-void cpu_register_physical_memory_log(target_phys_addr_t start_addr,
+void cpu_register_physical_memory_log(hwaddr start_addr,
ram_addr_t size,
ram_addr_t phys_offset,
ram_addr_t region_offset,
bool log_dirty)
{
- target_phys_addr_t addr, end_addr;
+ hwaddr addr, end_addr;
PhysPageDesc *p;
CPUState *env;
ram_addr_t orig_size = size;
@@ -2390,14 +2390,14 @@
}
region_offset &= TARGET_PAGE_MASK;
size = (size + TARGET_PAGE_SIZE - 1) & TARGET_PAGE_MASK;
- end_addr = start_addr + (target_phys_addr_t)size;
+ end_addr = start_addr + (hwaddr)size;
addr = start_addr;
do {
p = phys_page_find(addr >> TARGET_PAGE_BITS);
if (p && p->phys_offset != IO_MEM_UNASSIGNED) {
ram_addr_t orig_memory = p->phys_offset;
- target_phys_addr_t start_addr2, end_addr2;
+ hwaddr start_addr2, end_addr2;
int need_subpage = 0;
CHECK_SUBPAGE(addr, start_addr, start_addr2, end_addr, end_addr2,
@@ -2428,7 +2428,7 @@
(phys_offset & IO_MEM_ROMD)) {
phys_offset += TARGET_PAGE_SIZE;
} else {
- target_phys_addr_t start_addr2, end_addr2;
+ hwaddr start_addr2, end_addr2;
int need_subpage = 0;
CHECK_SUBPAGE(addr, start_addr, start_addr2, end_addr,
@@ -2457,7 +2457,7 @@
}
/* XXX: temporary until new memory mapping API */
-ram_addr_t cpu_get_physical_page_desc(target_phys_addr_t addr)
+ram_addr_t cpu_get_physical_page_desc(hwaddr addr)
{
PhysPageDesc *p;
@@ -2467,13 +2467,13 @@
return p->phys_offset;
}
-void qemu_register_coalesced_mmio(target_phys_addr_t addr, ram_addr_t size)
+void qemu_register_coalesced_mmio(hwaddr addr, ram_addr_t size)
{
if (kvm_enabled())
kvm_coalesce_mmio_region(addr, size);
}
-void qemu_unregister_coalesced_mmio(target_phys_addr_t addr, ram_addr_t size)
+void qemu_unregister_coalesced_mmio(hwaddr addr, ram_addr_t size)
{
if (kvm_enabled())
kvm_uncoalesce_mmio_region(addr, size);
@@ -2786,7 +2786,7 @@
return ram_addr;
}
-static uint32_t unassigned_mem_readb(void *opaque, target_phys_addr_t addr)
+static uint32_t unassigned_mem_readb(void *opaque, hwaddr addr)
{
#ifdef DEBUG_UNASSIGNED
printf("Unassigned mem read " TARGET_FMT_plx "\n", addr);
@@ -2797,7 +2797,7 @@
return 0;
}
-static uint32_t unassigned_mem_readw(void *opaque, target_phys_addr_t addr)
+static uint32_t unassigned_mem_readw(void *opaque, hwaddr addr)
{
#ifdef DEBUG_UNASSIGNED
printf("Unassigned mem read " TARGET_FMT_plx "\n", addr);
@@ -2808,7 +2808,7 @@
return 0;
}
-static uint32_t unassigned_mem_readl(void *opaque, target_phys_addr_t addr)
+static uint32_t unassigned_mem_readl(void *opaque, hwaddr addr)
{
#ifdef DEBUG_UNASSIGNED
printf("Unassigned mem read " TARGET_FMT_plx "\n", addr);
@@ -2819,7 +2819,7 @@
return 0;
}
-static void unassigned_mem_writeb(void *opaque, target_phys_addr_t addr, uint32_t val)
+static void unassigned_mem_writeb(void *opaque, hwaddr addr, uint32_t val)
{
#ifdef DEBUG_UNASSIGNED
printf("Unassigned mem write " TARGET_FMT_plx " = 0x%x\n", addr, val);
@@ -2829,7 +2829,7 @@
#endif
}
-static void unassigned_mem_writew(void *opaque, target_phys_addr_t addr, uint32_t val)
+static void unassigned_mem_writew(void *opaque, hwaddr addr, uint32_t val)
{
#ifdef DEBUG_UNASSIGNED
printf("Unassigned mem write " TARGET_FMT_plx " = 0x%x\n", addr, val);
@@ -2839,7 +2839,7 @@
#endif
}
-static void unassigned_mem_writel(void *opaque, target_phys_addr_t addr, uint32_t val)
+static void unassigned_mem_writel(void *opaque, hwaddr addr, uint32_t val)
{
#ifdef DEBUG_UNASSIGNED
printf("Unassigned mem write " TARGET_FMT_plx " = 0x%x\n", addr, val);
@@ -2861,7 +2861,7 @@
unassigned_mem_writel,
};
-static void notdirty_mem_writeb(void *opaque, target_phys_addr_t ram_addr,
+static void notdirty_mem_writeb(void *opaque, hwaddr ram_addr,
uint32_t val)
{
int dirty_flags;
@@ -2881,7 +2881,7 @@
tlb_set_dirty(cpu_single_env, cpu_single_env->mem_io_vaddr);
}
-static void notdirty_mem_writew(void *opaque, target_phys_addr_t ram_addr,
+static void notdirty_mem_writew(void *opaque, hwaddr ram_addr,
uint32_t val)
{
int dirty_flags;
@@ -2901,7 +2901,7 @@
tlb_set_dirty(cpu_single_env, cpu_single_env->mem_io_vaddr);
}
-static void notdirty_mem_writel(void *opaque, target_phys_addr_t ram_addr,
+static void notdirty_mem_writel(void *opaque, hwaddr ram_addr,
uint32_t val)
{
int dirty_flags;
@@ -2981,39 +2981,39 @@
/* Watchpoint access routines. Watchpoints are inserted using TLB tricks,
so these check for a hit then pass through to the normal out-of-line
phys routines. */
-static uint32_t watch_mem_readb(void *opaque, target_phys_addr_t addr)
+static uint32_t watch_mem_readb(void *opaque, hwaddr addr)
{
check_watchpoint(addr & ~TARGET_PAGE_MASK, ~0x0, BP_MEM_READ);
return ldub_phys(addr);
}
-static uint32_t watch_mem_readw(void *opaque, target_phys_addr_t addr)
+static uint32_t watch_mem_readw(void *opaque, hwaddr addr)
{
check_watchpoint(addr & ~TARGET_PAGE_MASK, ~0x1, BP_MEM_READ);
return lduw_phys(addr);
}
-static uint32_t watch_mem_readl(void *opaque, target_phys_addr_t addr)
+static uint32_t watch_mem_readl(void *opaque, hwaddr addr)
{
check_watchpoint(addr & ~TARGET_PAGE_MASK, ~0x3, BP_MEM_READ);
return ldl_phys(addr);
}
-static void watch_mem_writeb(void *opaque, target_phys_addr_t addr,
+static void watch_mem_writeb(void *opaque, hwaddr addr,
uint32_t val)
{
check_watchpoint(addr & ~TARGET_PAGE_MASK, ~0x0, BP_MEM_WRITE);
stb_phys(addr, val);
}
-static void watch_mem_writew(void *opaque, target_phys_addr_t addr,
+static void watch_mem_writew(void *opaque, hwaddr addr,
uint32_t val)
{
check_watchpoint(addr & ~TARGET_PAGE_MASK, ~0x1, BP_MEM_WRITE);
stw_phys(addr, val);
}
-static void watch_mem_writel(void *opaque, target_phys_addr_t addr,
+static void watch_mem_writel(void *opaque, hwaddr addr,
uint32_t val)
{
check_watchpoint(addr & ~TARGET_PAGE_MASK, ~0x3, BP_MEM_WRITE);
@@ -3032,7 +3032,7 @@
watch_mem_writel,
};
-static inline uint32_t subpage_readlen (subpage_t *mmio, target_phys_addr_t addr,
+static inline uint32_t subpage_readlen (subpage_t *mmio, hwaddr addr,
unsigned int len)
{
uint32_t ret;
@@ -3049,7 +3049,7 @@
return ret;
}
-static inline void subpage_writelen (subpage_t *mmio, target_phys_addr_t addr,
+static inline void subpage_writelen (subpage_t *mmio, hwaddr addr,
uint32_t value, unsigned int len)
{
unsigned int idx;
@@ -3064,7 +3064,7 @@
value);
}
-static uint32_t subpage_readb (void *opaque, target_phys_addr_t addr)
+static uint32_t subpage_readb (void *opaque, hwaddr addr)
{
#if defined(DEBUG_SUBPAGE)
printf("%s: addr " TARGET_FMT_plx "\n", __func__, addr);
@@ -3073,7 +3073,7 @@
return subpage_readlen(opaque, addr, 0);
}
-static void subpage_writeb (void *opaque, target_phys_addr_t addr,
+static void subpage_writeb (void *opaque, hwaddr addr,
uint32_t value)
{
#if defined(DEBUG_SUBPAGE)
@@ -3082,7 +3082,7 @@
subpage_writelen(opaque, addr, value, 0);
}
-static uint32_t subpage_readw (void *opaque, target_phys_addr_t addr)
+static uint32_t subpage_readw (void *opaque, hwaddr addr)
{
#if defined(DEBUG_SUBPAGE)
printf("%s: addr " TARGET_FMT_plx "\n", __func__, addr);
@@ -3091,7 +3091,7 @@
return subpage_readlen(opaque, addr, 1);
}
-static void subpage_writew (void *opaque, target_phys_addr_t addr,
+static void subpage_writew (void *opaque, hwaddr addr,
uint32_t value)
{
#if defined(DEBUG_SUBPAGE)
@@ -3100,7 +3100,7 @@
subpage_writelen(opaque, addr, value, 1);
}
-static uint32_t subpage_readl (void *opaque, target_phys_addr_t addr)
+static uint32_t subpage_readl (void *opaque, hwaddr addr)
{
#if defined(DEBUG_SUBPAGE)
printf("%s: addr " TARGET_FMT_plx "\n", __func__, addr);
@@ -3110,7 +3110,7 @@
}
static void subpage_writel (void *opaque,
- target_phys_addr_t addr, uint32_t value)
+ hwaddr addr, uint32_t value)
{
#if defined(DEBUG_SUBPAGE)
printf("%s: addr " TARGET_FMT_plx " val %08x\n", __func__, addr, value);
@@ -3163,7 +3163,7 @@
return 0;
}
-static void *subpage_init (target_phys_addr_t base, ram_addr_t *phys,
+static void *subpage_init (hwaddr base, ram_addr_t *phys,
ram_addr_t orig_memory, ram_addr_t region_offset)
{
subpage_t *mmio;
@@ -3269,7 +3269,7 @@
/* physical memory access (slow version, mainly for debug) */
#if defined(CONFIG_USER_ONLY)
-void cpu_physical_memory_rw(target_phys_addr_t addr, uint8_t *buf,
+void cpu_physical_memory_rw(hwaddr addr, uint8_t *buf,
int len, int is_write)
{
int l, flags;
@@ -3311,8 +3311,8 @@
#else
-static void invalidate_and_set_dirty(target_phys_addr_t addr,
- target_phys_addr_t length)
+static void invalidate_and_set_dirty(hwaddr addr,
+ hwaddr length)
{
if (!cpu_physical_memory_is_dirty(addr)) {
/* invalidate code */
@@ -3322,13 +3322,13 @@
}
}
-void cpu_physical_memory_rw(target_phys_addr_t addr, uint8_t *buf,
+void cpu_physical_memory_rw(hwaddr addr, uint8_t *buf,
int len, int is_write)
{
int l, io_index;
uint8_t *ptr;
uint32_t val;
- target_phys_addr_t page;
+ hwaddr page;
unsigned long pd;
PhysPageDesc *p;
@@ -3346,7 +3346,7 @@
if (is_write) {
if ((pd & ~TARGET_PAGE_MASK) != IO_MEM_RAM) {
- target_phys_addr_t addr1 = addr;
+ hwaddr addr1 = addr;
io_index = (pd >> IO_MEM_SHIFT) & (IO_MEM_NB_ENTRIES - 1);
if (p)
addr1 = (addr & ~TARGET_PAGE_MASK) + p->region_offset;
@@ -3379,7 +3379,7 @@
} else {
if ((pd & ~TARGET_PAGE_MASK) > IO_MEM_ROM &&
!(pd & IO_MEM_ROMD)) {
- target_phys_addr_t addr1 = addr;
+ hwaddr addr1 = addr;
/* I/O case */
io_index = (pd >> IO_MEM_SHIFT) & (IO_MEM_NB_ENTRIES - 1);
if (p)
@@ -3414,12 +3414,12 @@
}
/* used for ROM loading : can write in RAM and ROM */
-void cpu_physical_memory_write_rom(target_phys_addr_t addr,
+void cpu_physical_memory_write_rom(hwaddr addr,
const uint8_t *buf, int len)
{
int l;
uint8_t *ptr;
- target_phys_addr_t page;
+ hwaddr page;
unsigned long pd;
PhysPageDesc *p;
@@ -3455,8 +3455,8 @@
typedef struct {
void *buffer;
- target_phys_addr_t addr;
- target_phys_addr_t len;
+ hwaddr addr;
+ hwaddr len;
} BounceBuffer;
static BounceBuffer bounce;
@@ -3506,16 +3506,16 @@
* Use cpu_register_map_client() to know when retrying the map operation is
* likely to succeed.
*/
-void *cpu_physical_memory_map(target_phys_addr_t addr,
- target_phys_addr_t *plen,
+void *cpu_physical_memory_map(hwaddr addr,
+ hwaddr *plen,
int is_write)
{
- target_phys_addr_t len = *plen;
- target_phys_addr_t done = 0;
+ hwaddr len = *plen;
+ hwaddr done = 0;
int l;
uint8_t *ret = NULL;
uint8_t *ptr;
- target_phys_addr_t page;
+ hwaddr page;
unsigned long pd;
PhysPageDesc *p;
unsigned long addr1;
@@ -3565,8 +3565,8 @@
* Will also mark the memory as dirty if is_write == 1. access_len gives
* the amount of memory that was actually read or written by the caller.
*/
-void cpu_physical_memory_unmap(void *buffer, target_phys_addr_t len,
- int is_write, target_phys_addr_t access_len)
+void cpu_physical_memory_unmap(void *buffer, hwaddr len,
+ int is_write, hwaddr access_len)
{
if (buffer != bounce.buffer) {
if (is_write) {
@@ -3592,7 +3592,7 @@
}
/* warning: addr must be aligned */
-uint32_t ldl_phys(target_phys_addr_t addr)
+uint32_t ldl_phys(hwaddr addr)
{
int io_index;
uint8_t *ptr;
@@ -3624,7 +3624,7 @@
}
/* warning: addr must be aligned */
-uint64_t ldq_phys(target_phys_addr_t addr)
+uint64_t ldq_phys(hwaddr addr)
{
int io_index;
uint8_t *ptr;
@@ -3662,7 +3662,7 @@
}
/* XXX: optimize */
-uint32_t ldub_phys(target_phys_addr_t addr)
+uint32_t ldub_phys(hwaddr addr)
{
uint8_t val;
cpu_physical_memory_read(addr, &val, 1);
@@ -3670,7 +3670,7 @@
}
/* XXX: optimize */
-uint32_t lduw_phys(target_phys_addr_t addr)
+uint32_t lduw_phys(hwaddr addr)
{
uint16_t val;
cpu_physical_memory_read(addr, (uint8_t *)&val, 2);
@@ -3680,7 +3680,7 @@
/* warning: addr must be aligned. The ram page is not masked as dirty
and the code inside is not invalidated. It is useful if the dirty
bits are used to track modified PTEs */
-void stl_phys_notdirty(target_phys_addr_t addr, uint32_t val)
+void stl_phys_notdirty(hwaddr addr, uint32_t val)
{
int io_index;
uint8_t *ptr;
@@ -3716,7 +3716,7 @@
}
}
-void stq_phys_notdirty(target_phys_addr_t addr, uint64_t val)
+void stq_phys_notdirty(hwaddr addr, uint64_t val)
{
int io_index;
uint8_t *ptr;
@@ -3749,7 +3749,7 @@
}
/* warning: addr must be aligned */
-void stl_phys(target_phys_addr_t addr, uint32_t val)
+void stl_phys(hwaddr addr, uint32_t val)
{
int io_index;
uint8_t *ptr;
@@ -3779,21 +3779,21 @@
}
/* XXX: optimize */
-void stb_phys(target_phys_addr_t addr, uint32_t val)
+void stb_phys(hwaddr addr, uint32_t val)
{
uint8_t v = val;
cpu_physical_memory_write(addr, &v, 1);
}
/* XXX: optimize */
-void stw_phys(target_phys_addr_t addr, uint32_t val)
+void stw_phys(hwaddr addr, uint32_t val)
{
uint16_t v = tswap16(val);
cpu_physical_memory_write(addr, (const uint8_t *)&v, 2);
}
/* XXX: optimize */
-void stq_phys(target_phys_addr_t addr, uint64_t val)
+void stq_phys(hwaddr addr, uint64_t val)
{
val = tswap64(val);
cpu_physical_memory_write(addr, (const uint8_t *)&val, 8);
@@ -3806,7 +3806,7 @@
uint8_t *buf, int len, int is_write)
{
int l;
- target_phys_addr_t phys_addr;
+ hwaddr phys_addr;
target_ulong page;
while (len > 0) {
diff --git a/hw/android/goldfish/audio.c b/hw/android/goldfish/audio.c
index 8b868c4..1bb3289 100644
--- a/hw/android/goldfish/audio.c
+++ b/hw/android/goldfish/audio.c
@@ -373,7 +373,7 @@
}
#endif
-static uint32_t goldfish_audio_read(void *opaque, target_phys_addr_t offset)
+static uint32_t goldfish_audio_read(void *opaque, hwaddr offset)
{
uint32_t ret;
struct goldfish_audio_state *s = opaque;
@@ -407,7 +407,7 @@
}
}
-static void goldfish_audio_write(void *opaque, target_phys_addr_t offset, uint32_t val)
+static void goldfish_audio_write(void *opaque, hwaddr offset, uint32_t val)
{
struct goldfish_audio_state *s = opaque;
diff --git a/hw/android/goldfish/battery.c b/hw/android/goldfish/battery.c
index ad3e4ac..9c92e35 100644
--- a/hw/android/goldfish/battery.c
+++ b/hw/android/goldfish/battery.c
@@ -79,7 +79,7 @@
static struct goldfish_battery_state *battery_state;
-static uint32_t goldfish_battery_read(void *opaque, target_phys_addr_t offset)
+static uint32_t goldfish_battery_read(void *opaque, hwaddr offset)
{
uint32_t ret;
struct goldfish_battery_state *s = opaque;
@@ -113,7 +113,7 @@
}
}
-static void goldfish_battery_write(void *opaque, target_phys_addr_t offset, uint32_t val)
+static void goldfish_battery_write(void *opaque, hwaddr offset, uint32_t val)
{
struct goldfish_battery_state *s = opaque;
diff --git a/hw/android/goldfish/device.c b/hw/android/goldfish/device.c
index 84c4262..87ce575 100644
--- a/hw/android/goldfish/device.c
+++ b/hw/android/goldfish/device.c
@@ -96,7 +96,7 @@
return 0;
}
-static uint32_t goldfish_bus_read(void *opaque, target_phys_addr_t offset)
+static uint32_t goldfish_bus_read(void *opaque, hwaddr offset)
{
struct bus_state *s = (struct bus_state *)opaque;
@@ -147,7 +147,7 @@
goldfish_device_set_irq(&s->dev, 0, first_device != NULL);
}
-static void goldfish_bus_write(void *opaque, target_phys_addr_t offset, uint32_t value)
+static void goldfish_bus_write(void *opaque, hwaddr offset, uint32_t value)
{
struct bus_state *s = (struct bus_state *)opaque;
diff --git a/hw/android/goldfish/events_device.c b/hw/android/goldfish/events_device.c
index baff992..e80813d 100644
--- a/hw/android/goldfish/events_device.c
+++ b/hw/android/goldfish/events_device.c
@@ -210,7 +210,7 @@
return 0;
}
-static uint32_t events_read(void *x, target_phys_addr_t off)
+static uint32_t events_read(void *x, hwaddr off)
{
events_state *s = (events_state *) x;
int offset = off; // - s->base;
@@ -236,7 +236,7 @@
return 0; // this shouldn't happen, if the driver does the right thing
}
-static void events_write(void *x, target_phys_addr_t off, uint32_t val)
+static void events_write(void *x, hwaddr off, uint32_t val)
{
events_state *s = (events_state *) x;
int offset = off; // - s->base;
diff --git a/hw/android/goldfish/fb.c b/hw/android/goldfish/fb.c
index ee817fd..dd35d43 100644
--- a/hw/android/goldfish/fb.c
+++ b/hw/android/goldfish/fb.c
@@ -548,7 +548,7 @@
s->need_update = 1;
}
-static uint32_t goldfish_fb_read(void *opaque, target_phys_addr_t offset)
+static uint32_t goldfish_fb_read(void *opaque, hwaddr offset)
{
uint32_t ret;
struct goldfish_fb_state *s = opaque;
@@ -591,7 +591,7 @@
}
}
-static void goldfish_fb_write(void *opaque, target_phys_addr_t offset,
+static void goldfish_fb_write(void *opaque, hwaddr offset,
uint32_t val)
{
struct goldfish_fb_state *s = opaque;
diff --git a/hw/android/goldfish/interrupt.c b/hw/android/goldfish/interrupt.c
index 725830a..bd72a4c 100644
--- a/hw/android/goldfish/interrupt.c
+++ b/hw/android/goldfish/interrupt.c
@@ -92,7 +92,7 @@
goldfish_int_update(s);
}
-static uint32_t goldfish_int_read(void *opaque, target_phys_addr_t offset)
+static uint32_t goldfish_int_read(void *opaque, hwaddr offset)
{
struct goldfish_int_state *s = (struct goldfish_int_state *)opaque;
@@ -114,7 +114,7 @@
}
}
-static void goldfish_int_write(void *opaque, target_phys_addr_t offset, uint32_t value)
+static void goldfish_int_write(void *opaque, hwaddr offset, uint32_t value)
{
struct goldfish_int_state *s = (struct goldfish_int_state *)opaque;
uint32_t mask = (1U << value);
diff --git a/hw/android/goldfish/memlog.c b/hw/android/goldfish/memlog.c
index d93e5ad..4716c9c 100644
--- a/hw/android/goldfish/memlog.c
+++ b/hw/android/goldfish/memlog.c
@@ -21,7 +21,7 @@
int fd = -1;
-static uint32_t memlog_read(void *opaque, target_phys_addr_t offset)
+static uint32_t memlog_read(void *opaque, hwaddr offset)
{
(void)opaque;
(void)offset;
@@ -30,7 +30,7 @@
unsigned info[8];
-static void memlog_write(void *opaque, target_phys_addr_t offset, uint32_t val)
+static void memlog_write(void *opaque, hwaddr offset, uint32_t val)
{
char buf[128];
struct goldfish_device *dev = opaque;
diff --git a/hw/android/goldfish/mmc.c b/hw/android/goldfish/mmc.c
index 48347f7..4d27e23 100644
--- a/hw/android/goldfish/mmc.c
+++ b/hw/android/goldfish/mmc.c
@@ -172,7 +172,7 @@
static int goldfish_mmc_bdrv_read(struct goldfish_mmc_state *s,
int64_t sector_number,
- target_phys_addr_t dst_address,
+ hwaddr dst_address,
int num_sectors)
{
int ret;
@@ -192,7 +192,7 @@
static int goldfish_mmc_bdrv_write(struct goldfish_mmc_state *s,
int64_t sector_number,
- target_phys_addr_t dst_address,
+ hwaddr dst_address,
int num_sectors)
{
int ret;
@@ -412,7 +412,7 @@
}
}
-static uint32_t goldfish_mmc_read(void *opaque, target_phys_addr_t offset)
+static uint32_t goldfish_mmc_read(void *opaque, hwaddr offset)
{
uint32_t ret;
struct goldfish_mmc_state *s = opaque;
@@ -442,7 +442,7 @@
}
}
-static void goldfish_mmc_write(void *opaque, target_phys_addr_t offset, uint32_t val)
+static void goldfish_mmc_write(void *opaque, hwaddr offset, uint32_t val)
{
struct goldfish_mmc_state *s = opaque;
int status, old_status;
diff --git a/hw/android/goldfish/nand.c b/hw/android/goldfish/nand.c
index 9b40729..56e5973 100644
--- a/hw/android/goldfish/nand.c
+++ b/hw/android/goldfish/nand.c
@@ -523,7 +523,7 @@
}
/* I/O write */
-static void nand_dev_write(void *opaque, target_phys_addr_t offset, uint32_t value)
+static void nand_dev_write(void *opaque, hwaddr offset, uint32_t value)
{
nand_dev_controller_state *s = (nand_dev_controller_state *)opaque;
@@ -569,7 +569,7 @@
}
/* I/O read */
-static uint32_t nand_dev_read(void *opaque, target_phys_addr_t offset)
+static uint32_t nand_dev_read(void *opaque, hwaddr offset)
{
nand_dev_controller_state *s = (nand_dev_controller_state *)opaque;
nand_dev *dev;
diff --git a/hw/android/goldfish/pipe.c b/hw/android/goldfish/pipe.c
index e6d9288..a495b05 100644
--- a/hw/android/goldfish/pipe.c
+++ b/hw/android/goldfish/pipe.c
@@ -1012,7 +1012,7 @@
GoldfishPipeBuffer buffer;
uint32_t address = dev->address;
uint32_t page = address & TARGET_PAGE_MASK;
- target_phys_addr_t phys;
+ hwaddr phys;
phys = safe_get_phys_page_debug(env, page);
buffer.data = qemu_get_ram_ptr(phys) + (address - page);
buffer.size = dev->size;
@@ -1027,7 +1027,7 @@
GoldfishPipeBuffer buffer;
uint32_t address = dev->address;
uint32_t page = address & TARGET_PAGE_MASK;
- target_phys_addr_t phys;
+ hwaddr phys;
phys = safe_get_phys_page_debug(env, page);
buffer.data = qemu_get_ram_ptr(phys) + (address - page);
buffer.size = dev->size;
@@ -1060,7 +1060,7 @@
}
}
-static void pipe_dev_write(void *opaque, target_phys_addr_t offset, uint32_t value)
+static void pipe_dev_write(void *opaque, hwaddr offset, uint32_t value)
{
PipeDevice *s = (PipeDevice *)opaque;
@@ -1129,7 +1129,7 @@
}
/* I/O read */
-static uint32_t pipe_dev_read(void *opaque, target_phys_addr_t offset)
+static uint32_t pipe_dev_read(void *opaque, hwaddr offset)
{
PipeDevice *dev = (PipeDevice *)opaque;
diff --git a/hw/android/goldfish/switch.c b/hw/android/goldfish/switch.c
index e3e1c52..eb8fe67 100644
--- a/hw/android/goldfish/switch.c
+++ b/hw/android/goldfish/switch.c
@@ -60,7 +60,7 @@
return 0;
}
-static uint32_t goldfish_switch_read(void *opaque, target_phys_addr_t offset)
+static uint32_t goldfish_switch_read(void *opaque, hwaddr offset)
{
struct switch_state *s = (struct switch_state *)opaque;
@@ -86,7 +86,7 @@
}
}
-static void goldfish_switch_write(void *opaque, target_phys_addr_t offset, uint32_t value)
+static void goldfish_switch_write(void *opaque, hwaddr offset, uint32_t value)
{
struct switch_state *s = (struct switch_state *)opaque;
diff --git a/hw/android/goldfish/timer.c b/hw/android/goldfish/timer.c
index 8ebdd89..6204866 100644
--- a/hw/android/goldfish/timer.c
+++ b/hw/android/goldfish/timer.c
@@ -73,7 +73,7 @@
return 0;
}
-static uint32_t goldfish_timer_read(void *opaque, target_phys_addr_t offset)
+static uint32_t goldfish_timer_read(void *opaque, hwaddr offset)
{
struct timer_state *s = (struct timer_state *)opaque;
switch(offset) {
@@ -88,7 +88,7 @@
}
}
-static void goldfish_timer_write(void *opaque, target_phys_addr_t offset, uint32_t value_ns)
+static void goldfish_timer_write(void *opaque, hwaddr offset, uint32_t value_ns)
{
struct timer_state *s = (struct timer_state *)opaque;
int64_t alarm_ns, now_ns;
@@ -157,7 +157,7 @@
return 0;
}
-static uint32_t goldfish_rtc_read(void *opaque, target_phys_addr_t offset)
+static uint32_t goldfish_rtc_read(void *opaque, hwaddr offset)
{
struct rtc_state *s = (struct rtc_state *)opaque;
switch(offset) {
@@ -172,7 +172,7 @@
}
}
-static void goldfish_rtc_write(void *opaque, target_phys_addr_t offset, uint32_t value)
+static void goldfish_rtc_write(void *opaque, hwaddr offset, uint32_t value)
{
struct rtc_state *s = (struct rtc_state *)opaque;
int64_t alarm;
diff --git a/hw/android/goldfish/trace.c b/hw/android/goldfish/trace.c
index 681bce7..eb723fe 100644
--- a/hw/android/goldfish/trace.c
+++ b/hw/android/goldfish/trace.c
@@ -63,7 +63,7 @@
//static unsigned long cs_pid; // context switch PID
/* I/O write */
-static void trace_dev_write(void *opaque, target_phys_addr_t offset, uint32_t value)
+static void trace_dev_write(void *opaque, hwaddr offset, uint32_t value)
{
trace_dev_state *s = (trace_dev_state *)opaque;
@@ -361,7 +361,7 @@
}
/* I/O read */
-static uint32_t trace_dev_read(void *opaque, target_phys_addr_t offset)
+static uint32_t trace_dev_read(void *opaque, hwaddr offset)
{
trace_dev_state *s = (trace_dev_state *)opaque;
diff --git a/hw/android/goldfish/tty.c b/hw/android/goldfish/tty.c
index cd9ef1a..60bd8fb 100644
--- a/hw/android/goldfish/tty.c
+++ b/hw/android/goldfish/tty.c
@@ -67,7 +67,7 @@
return 0;
}
-static uint32_t goldfish_tty_read(void *opaque, target_phys_addr_t offset)
+static uint32_t goldfish_tty_read(void *opaque, hwaddr offset)
{
struct tty_state *s = (struct tty_state *)opaque;
@@ -82,7 +82,7 @@
}
}
-static void goldfish_tty_write(void *opaque, target_phys_addr_t offset, uint32_t value)
+static void goldfish_tty_write(void *opaque, hwaddr offset, uint32_t value)
{
struct tty_state *s = (struct tty_state *)opaque;
@@ -116,7 +116,7 @@
case TTY_CMD_WRITE_BUFFER:
if(s->cs) {
int len;
- target_phys_addr_t buf;
+ hwaddr buf;
buf = s->ptr;
len = s->ptr_len;
diff --git a/hw/android/goldfish/vmem.c b/hw/android/goldfish/vmem.c
index a78290f..e676b61 100644
--- a/hw/android/goldfish/vmem.c
+++ b/hw/android/goldfish/vmem.c
@@ -37,7 +37,7 @@
return cpu_memory_rw_debug(env, addr, buf, len, is_write);
}
-target_phys_addr_t safe_get_phys_page_debug(CPUState *env, target_ulong addr)
+hwaddr safe_get_phys_page_debug(CPUState *env, target_ulong addr)
{
#ifdef TARGET_I386
if (kvm_enabled()) {
diff --git a/hw/arm/arm_gic.c b/hw/arm/arm_gic.c
index 563397d..1f5af8b 100644
--- a/hw/arm/arm_gic.c
+++ b/hw/arm/arm_gic.c
@@ -238,7 +238,7 @@
}
}
-static uint32_t gic_dist_readb(void *opaque, target_phys_addr_t offset)
+static uint32_t gic_dist_readb(void *opaque, hwaddr offset)
{
gic_state *s = (gic_state *)opaque;
uint32_t res;
@@ -348,7 +348,7 @@
return 0;
}
-static uint32_t gic_dist_readw(void *opaque, target_phys_addr_t offset)
+static uint32_t gic_dist_readw(void *opaque, hwaddr offset)
{
uint32_t val;
val = gic_dist_readb(opaque, offset);
@@ -356,7 +356,7 @@
return val;
}
-static uint32_t gic_dist_readl(void *opaque, target_phys_addr_t offset)
+static uint32_t gic_dist_readl(void *opaque, hwaddr offset)
{
uint32_t val;
#ifdef NVIC
@@ -371,7 +371,7 @@
return val;
}
-static void gic_dist_writeb(void *opaque, target_phys_addr_t offset,
+static void gic_dist_writeb(void *opaque, hwaddr offset,
uint32_t value)
{
gic_state *s = (gic_state *)opaque;
@@ -509,14 +509,14 @@
hw_error("gic_dist_writeb: Bad offset %x\n", (int)offset);
}
-static void gic_dist_writew(void *opaque, target_phys_addr_t offset,
+static void gic_dist_writew(void *opaque, hwaddr offset,
uint32_t value)
{
gic_dist_writeb(opaque, offset, value & 0xff);
gic_dist_writeb(opaque, offset + 1, value >> 8);
}
-static void gic_dist_writel(void *opaque, target_phys_addr_t offset,
+static void gic_dist_writel(void *opaque, hwaddr offset,
uint32_t value)
{
gic_state *s = (gic_state *)opaque;
diff --git a/hw/arm/armv7m.c b/hw/arm/armv7m.c
index c902078..0563fef 100644
--- a/hw/arm/armv7m.c
+++ b/hw/arm/armv7m.c
@@ -24,14 +24,14 @@
}
-static uint32_t bitband_readb(void *opaque, target_phys_addr_t offset)
+static uint32_t bitband_readb(void *opaque, hwaddr offset)
{
uint8_t v;
cpu_physical_memory_read(bitband_addr(opaque, offset), &v, 1);
return (v & (1 << ((offset >> 2) & 7))) != 0;
}
-static void bitband_writeb(void *opaque, target_phys_addr_t offset,
+static void bitband_writeb(void *opaque, hwaddr offset,
uint32_t value)
{
uint32_t addr;
@@ -47,7 +47,7 @@
cpu_physical_memory_write(addr, &v, 1);
}
-static uint32_t bitband_readw(void *opaque, target_phys_addr_t offset)
+static uint32_t bitband_readw(void *opaque, hwaddr offset)
{
uint32_t addr;
uint16_t mask;
@@ -59,7 +59,7 @@
return (v & mask) != 0;
}
-static void bitband_writew(void *opaque, target_phys_addr_t offset,
+static void bitband_writew(void *opaque, hwaddr offset,
uint32_t value)
{
uint32_t addr;
@@ -76,7 +76,7 @@
cpu_physical_memory_write(addr, (uint8_t *)&v, 2);
}
-static uint32_t bitband_readl(void *opaque, target_phys_addr_t offset)
+static uint32_t bitband_readl(void *opaque, hwaddr offset)
{
uint32_t addr;
uint32_t mask;
@@ -88,7 +88,7 @@
return (v & mask) != 0;
}
-static void bitband_writel(void *opaque, target_phys_addr_t offset,
+static void bitband_writel(void *opaque, hwaddr offset,
uint32_t value)
{
uint32_t addr;
diff --git a/hw/arm/boot.c b/hw/arm/boot.c
index c6e0199..46f2e0b 100644
--- a/hw/arm/boot.c
+++ b/hw/arm/boot.c
@@ -59,9 +59,9 @@
} while (0)
static void set_kernel_args(struct arm_boot_info *info,
- int initrd_size, target_phys_addr_t base)
+ int initrd_size, hwaddr base)
{
- target_phys_addr_t p;
+ hwaddr p;
p = base + KERNEL_ARGS_ADDR;
/* ATAG_CORE */
@@ -112,9 +112,9 @@
}
static void set_kernel_args_old(struct arm_boot_info *info,
- int initrd_size, target_phys_addr_t base)
+ int initrd_size, hwaddr base)
{
- target_phys_addr_t p;
+ hwaddr p;
const char *s;
@@ -191,7 +191,7 @@
int n;
int is_linux = 0;
uint64_t elf_entry;
- target_phys_addr_t entry;
+ hwaddr entry;
int big_endian;
/* Load the kernel. */
diff --git a/hw/core/dma.c b/hw/core/dma.c
index ac56753..3c87547 100644
--- a/hw/core/dma.c
+++ b/hw/core/dma.c
@@ -403,7 +403,7 @@
int DMA_read_memory (int nchan, void *buf, int pos, int len)
{
struct dma_regs *r = &dma_controllers[nchan > 3].regs[nchan & 3];
- target_phys_addr_t addr = ((r->pageh & 0x7f) << 24) | (r->page << 16) | r->now[ADDR];
+ hwaddr addr = ((r->pageh & 0x7f) << 24) | (r->page << 16) | r->now[ADDR];
if (r->mode & 0x20) {
int i;
@@ -425,7 +425,7 @@
int DMA_write_memory (int nchan, void *buf, int pos, int len)
{
struct dma_regs *r = &dma_controllers[nchan > 3].regs[nchan & 3];
- target_phys_addr_t addr = ((r->pageh & 0x7f) << 24) | (r->page << 16) | r->now[ADDR];
+ hwaddr addr = ((r->pageh & 0x7f) << 24) | (r->page << 16) | r->now[ADDR];
if (r->mode & 0x20) {
int i;
diff --git a/hw/core/loader.c b/hw/core/loader.c
index 03c3366..b0959e6 100644
--- a/hw/core/loader.c
+++ b/hw/core/loader.c
@@ -81,10 +81,10 @@
}
/* return the amount read, just like fread. 0 may mean error or eof */
-int fread_targphys(target_phys_addr_t dst_addr, size_t nbytes, FILE *f)
+int fread_targphys(hwaddr dst_addr, size_t nbytes, FILE *f)
{
uint8_t buf[4096];
- target_phys_addr_t dst_begin = dst_addr;
+ hwaddr dst_begin = dst_addr;
size_t want, did;
while (nbytes) {
@@ -101,16 +101,16 @@
}
/* returns 0 on error, 1 if ok */
-int fread_targphys_ok(target_phys_addr_t dst_addr, size_t nbytes, FILE *f)
+int fread_targphys_ok(hwaddr dst_addr, size_t nbytes, FILE *f)
{
return fread_targphys(dst_addr, nbytes, f) == nbytes;
}
/* read()-like version */
-int read_targphys(int fd, target_phys_addr_t dst_addr, size_t nbytes)
+int read_targphys(int fd, hwaddr dst_addr, size_t nbytes)
{
uint8_t buf[4096];
- target_phys_addr_t dst_begin = dst_addr;
+ hwaddr dst_begin = dst_addr;
size_t want, did;
while (nbytes) {
@@ -127,7 +127,7 @@
/* return the size or -1 if error */
int load_image_targphys(const char *filename,
- target_phys_addr_t addr, int max_sz)
+ hwaddr addr, int max_sz)
{
FILE *f;
size_t got;
@@ -142,7 +142,7 @@
return got;
}
-void pstrcpy_targphys(target_phys_addr_t dest, int buf_size,
+void pstrcpy_targphys(hwaddr dest, int buf_size,
const char *source)
{
static const uint8_t nul_byte = 0;
@@ -208,7 +208,7 @@
: (_N_SEGMENT_ROUND (_N_TXTENDADDR(x))))
-int load_aout(const char *filename, target_phys_addr_t addr, int max_sz)
+int load_aout(const char *filename, hwaddr addr, int max_sz)
{
int fd, size, ret;
struct exec e;
diff --git a/hw/core/sysbus.c b/hw/core/sysbus.c
index 603e8ce..d345422 100644
--- a/hw/core/sysbus.c
+++ b/hw/core/sysbus.c
@@ -31,7 +31,7 @@
}
}
-void sysbus_mmio_map(SysBusDevice *dev, int n, target_phys_addr_t addr)
+void sysbus_mmio_map(SysBusDevice *dev, int n, hwaddr addr)
{
assert(n >= 0 && n < dev->num_mmio);
@@ -39,7 +39,7 @@
/* ??? region already mapped here. */
return;
}
- if (dev->mmio[n].addr != (target_phys_addr_t)-1) {
+ if (dev->mmio[n].addr != (hwaddr)-1) {
/* Unregister previous mapping. */
cpu_register_physical_memory(dev->mmio[n].addr, dev->mmio[n].size,
IO_MEM_UNASSIGNED);
@@ -75,7 +75,7 @@
}
}
-void sysbus_init_mmio(SysBusDevice *dev, target_phys_addr_t size, int iofunc)
+void sysbus_init_mmio(SysBusDevice *dev, hwaddr size, int iofunc)
{
int n;
@@ -86,7 +86,7 @@
dev->mmio[n].iofunc = iofunc;
}
-void sysbus_init_mmio_cb(SysBusDevice *dev, target_phys_addr_t size,
+void sysbus_init_mmio_cb(SysBusDevice *dev, hwaddr size,
mmio_mapfunc cb)
{
int n;
@@ -126,7 +126,7 @@
}
DeviceState *sysbus_create_varargs(const char *name,
- target_phys_addr_t addr, ...)
+ hwaddr addr, ...)
{
DeviceState *dev;
SysBusDevice *s;
@@ -137,7 +137,7 @@
dev = qdev_create(NULL, name);
s = sysbus_from_qdev(dev);
qdev_init(dev);
- if (addr != (target_phys_addr_t)-1) {
+ if (addr != (hwaddr)-1) {
sysbus_mmio_map(s, 0, addr);
}
va_start(va, addr);
diff --git a/hw/i386/pc.c b/hw/i386/pc.c
index 64332c1..6c6b909 100644
--- a/hw/i386/pc.c
+++ b/hw/i386/pc.c
@@ -70,7 +70,7 @@
typedef struct rom_reset_data {
uint8_t *data;
- target_phys_addr_t addr;
+ hwaddr addr;
unsigned size;
} RomResetData;
@@ -81,7 +81,7 @@
cpu_physical_memory_write_rom(rrd->addr, rrd->data, rrd->size);
}
-static void option_rom_setup_reset(target_phys_addr_t addr, unsigned size)
+static void option_rom_setup_reset(hwaddr addr, unsigned size)
{
RomResetData *rrd = qemu_malloc(sizeof *rrd);
@@ -516,7 +516,7 @@
/* Generate an initial boot sector which sets state and jump to
a specified vector */
-static void generate_bootsect(target_phys_addr_t option_rom,
+static void generate_bootsect(hwaddr option_rom,
uint32_t gpr[8], uint16_t segs[6], uint16_t ip)
{
uint8_t rom[512], *p, *reloc;
@@ -608,11 +608,11 @@
return size;
}
-static void load_linux(target_phys_addr_t option_rom,
+static void load_linux(hwaddr option_rom,
const char *kernel_filename,
const char *initrd_filename,
const char *kernel_cmdline,
- target_phys_addr_t max_ram_size)
+ hwaddr max_ram_size)
{
uint16_t protocol;
uint32_t gpr[8];
@@ -621,7 +621,7 @@
int setup_size, kernel_size, initrd_size = 0, cmdline_size;
uint32_t initrd_max;
uint8_t header[1024];
- target_phys_addr_t real_addr, prot_addr, cmdline_addr, initrd_addr = 0;
+ hwaddr real_addr, prot_addr, cmdline_addr, initrd_addr = 0;
FILE *f, *fi;
/* Align to 16 bytes as a paranoia measure */
@@ -819,8 +819,8 @@
nb_ne2k++;
}
-static int load_option_rom(const char *oprom, target_phys_addr_t start,
- target_phys_addr_t end)
+static int load_option_rom(const char *oprom, hwaddr start,
+ hwaddr end)
{
int size;
char *filename;
diff --git a/hw/input/pckbd.c b/hw/input/pckbd.c
index ad20bd7..e4c3816 100644
--- a/hw/input/pckbd.c
+++ b/hw/input/pckbd.c
@@ -123,7 +123,7 @@
qemu_irq irq_kbd;
qemu_irq irq_mouse;
- target_phys_addr_t mask;
+ hwaddr mask;
} KBDState;
static KBDState kbd_state;
@@ -387,7 +387,7 @@
}
/* Memory mapped interface */
-static uint32_t kbd_mm_readb (void *opaque, target_phys_addr_t addr)
+static uint32_t kbd_mm_readb (void *opaque, hwaddr addr)
{
KBDState *s = opaque;
@@ -397,7 +397,7 @@
return kbd_read_data(s, 0) & 0xff;
}
-static void kbd_mm_writeb (void *opaque, target_phys_addr_t addr, uint32_t value)
+static void kbd_mm_writeb (void *opaque, hwaddr addr, uint32_t value)
{
KBDState *s = opaque;
@@ -420,8 +420,8 @@
};
void i8042_mm_init(qemu_irq kbd_irq, qemu_irq mouse_irq,
- target_phys_addr_t base, ram_addr_t size,
- target_phys_addr_t mask)
+ hwaddr base, ram_addr_t size,
+ hwaddr mask)
{
KBDState *s = &kbd_state;
int s_io_memory;
diff --git a/hw/intc/apic.c b/hw/intc/apic.c
index bde5028..839ec56 100644
--- a/hw/intc/apic.c
+++ b/hw/intc/apic.c
@@ -646,25 +646,25 @@
apic_timer_update(s, s->next_time);
}
-static uint32_t apic_mem_readb(void *opaque, target_phys_addr_t addr)
+static uint32_t apic_mem_readb(void *opaque, hwaddr addr)
{
return 0;
}
-static uint32_t apic_mem_readw(void *opaque, target_phys_addr_t addr)
+static uint32_t apic_mem_readw(void *opaque, hwaddr addr)
{
return 0;
}
-static void apic_mem_writeb(void *opaque, target_phys_addr_t addr, uint32_t val)
+static void apic_mem_writeb(void *opaque, hwaddr addr, uint32_t val)
{
}
-static void apic_mem_writew(void *opaque, target_phys_addr_t addr, uint32_t val)
+static void apic_mem_writew(void *opaque, hwaddr addr, uint32_t val)
{
}
-static uint32_t apic_mem_readl(void *opaque, target_phys_addr_t addr)
+static uint32_t apic_mem_readl(void *opaque, hwaddr addr)
{
CPUState *env;
APICState *s;
@@ -745,7 +745,7 @@
return val;
}
-static void apic_mem_writel(void *opaque, target_phys_addr_t addr, uint32_t val)
+static void apic_mem_writel(void *opaque, hwaddr addr, uint32_t val)
{
CPUState *env;
APICState *s;
diff --git a/hw/intc/ioapic.c b/hw/intc/ioapic.c
index fb4e98a..b80d684 100644
--- a/hw/intc/ioapic.c
+++ b/hw/intc/ioapic.c
@@ -120,7 +120,7 @@
}
}
-static uint32_t ioapic_mem_readl(void *opaque, target_phys_addr_t addr)
+static uint32_t ioapic_mem_readl(void *opaque, hwaddr addr)
{
IOAPICState *s = opaque;
int index;
@@ -156,7 +156,7 @@
return val;
}
-static void ioapic_mem_writel(void *opaque, target_phys_addr_t addr, uint32_t val)
+static void ioapic_mem_writel(void *opaque, hwaddr addr, uint32_t val)
{
IOAPICState *s = opaque;
int index;
diff --git a/hw/mips/mips_r4k.c b/hw/mips/mips_r4k.c
index e90f404..03de0dd 100644
--- a/hw/mips/mips_r4k.c
+++ b/hw/mips/mips_r4k.c
@@ -42,7 +42,7 @@
const char *initrd_filename;
} loaderparams;
-static void mips_qemu_writel (void *opaque, target_phys_addr_t addr,
+static void mips_qemu_writel (void *opaque, hwaddr addr,
uint32_t val)
{
if ((addr & 0xffff) == 0 && val == 42)
@@ -51,7 +51,7 @@
qemu_system_shutdown_request ();
}
-static uint32_t mips_qemu_readl (void *opaque, target_phys_addr_t addr)
+static uint32_t mips_qemu_readl (void *opaque, hwaddr addr)
{
return 0;
}
diff --git a/hw/net/smc91c111.c b/hw/net/smc91c111.c
index 3ba10ca..a2ef1a2 100644
--- a/hw/net/smc91c111.c
+++ b/hw/net/smc91c111.c
@@ -322,7 +322,7 @@
#define SET_LOW(name, val) s->name = (s->name & 0xff00) | val
#define SET_HIGH(name, val) s->name = (s->name & 0xff) | (val << 8)
-static void smc91c111_writeb(void *opaque, target_phys_addr_t offset,
+static void smc91c111_writeb(void *opaque, hwaddr offset,
uint32_t value)
{
smc91c111_state *s = (smc91c111_state *)opaque;
@@ -494,7 +494,7 @@
hw_error("smc91c111_write: Bad reg %d:%x\n", s->bank, (int)offset);
}
-static uint32_t smc91c111_readb(void *opaque, target_phys_addr_t offset)
+static uint32_t smc91c111_readb(void *opaque, hwaddr offset)
{
smc91c111_state *s = (smc91c111_state *)opaque;
@@ -635,14 +635,14 @@
return 0;
}
-static void smc91c111_writew(void *opaque, target_phys_addr_t offset,
+static void smc91c111_writew(void *opaque, hwaddr offset,
uint32_t value)
{
smc91c111_writeb(opaque, offset, value & 0xff);
smc91c111_writeb(opaque, offset + 1, value >> 8);
}
-static void smc91c111_writel(void *opaque, target_phys_addr_t offset,
+static void smc91c111_writel(void *opaque, hwaddr offset,
uint32_t value)
{
/* 32-bit writes to offset 0xc only actually write to the bank select
@@ -652,7 +652,7 @@
smc91c111_writew(opaque, offset + 2, value >> 16);
}
-static uint32_t smc91c111_readw(void *opaque, target_phys_addr_t offset)
+static uint32_t smc91c111_readw(void *opaque, hwaddr offset)
{
uint32_t val;
val = smc91c111_readb(opaque, offset);
@@ -660,7 +660,7 @@
return val;
}
-static uint32_t smc91c111_readl(void *opaque, target_phys_addr_t offset)
+static uint32_t smc91c111_readl(void *opaque, hwaddr offset)
{
uint32_t val;
val = smc91c111_readw(opaque, offset);
diff --git a/hw/nvram/fw_cfg.c b/hw/nvram/fw_cfg.c
index 98a97cf..e1231db 100644
--- a/hw/nvram/fw_cfg.c
+++ b/hw/nvram/fw_cfg.c
@@ -116,18 +116,18 @@
fw_cfg_select(opaque, (uint16_t)value);
}
-static uint32_t fw_cfg_mem_readb(void *opaque, target_phys_addr_t addr)
+static uint32_t fw_cfg_mem_readb(void *opaque, hwaddr addr)
{
return fw_cfg_read(opaque);
}
-static void fw_cfg_mem_writeb(void *opaque, target_phys_addr_t addr,
+static void fw_cfg_mem_writeb(void *opaque, hwaddr addr,
uint32_t value)
{
fw_cfg_write(opaque, (uint8_t)value);
}
-static void fw_cfg_mem_writew(void *opaque, target_phys_addr_t addr,
+static void fw_cfg_mem_writew(void *opaque, hwaddr addr,
uint32_t value)
{
fw_cfg_select(opaque, (uint16_t)value);
@@ -251,7 +251,7 @@
}
void *fw_cfg_init(uint32_t ctl_port, uint32_t data_port,
- target_phys_addr_t ctl_addr, target_phys_addr_t data_addr)
+ hwaddr ctl_addr, hwaddr data_addr)
{
FWCfgState *s;
int io_ctl_memory, io_data_memory;
diff --git a/hw/pci-host/pci_host.h b/hw/pci-host/pci_host.h
index 0465e02..49be01f 100644
--- a/hw/pci-host/pci_host.h
+++ b/hw/pci-host/pci_host.h
@@ -44,7 +44,7 @@
PCIHostState *s = opaque;
PCI_DPRINTF("writeb addr " TARGET_FMT_plx " val %x\n",
- (target_phys_addr_t)addr, val);
+ (hwaddr)addr, val);
if (s->config_reg & (1u << 31))
pci_data_write(s->bus, s->config_reg | (addr & 3), val, 1);
}
@@ -56,7 +56,7 @@
val = bswap16(val);
#endif
PCI_DPRINTF("writew addr " TARGET_FMT_plx " val %x\n",
- (target_phys_addr_t)addr, val);
+ (hwaddr)addr, val);
if (s->config_reg & (1u << 31))
pci_data_write(s->bus, s->config_reg | (addr & 3), val, 2);
}
@@ -68,7 +68,7 @@
val = bswap32(val);
#endif
PCI_DPRINTF("writel addr " TARGET_FMT_plx " val %x\n",
- (target_phys_addr_t)addr, val);
+ (hwaddr)addr, val);
if (s->config_reg & (1u << 31))
pci_data_write(s->bus, s->config_reg, val, 4);
}
@@ -82,7 +82,7 @@
return 0xff;
val = pci_data_read(s->bus, s->config_reg | (addr & 3), 1);
PCI_DPRINTF("readb addr " TARGET_FMT_plx " val %x\n",
- (target_phys_addr_t)addr, val);
+ (hwaddr)addr, val);
return val;
}
@@ -94,7 +94,7 @@
return 0xffff;
val = pci_data_read(s->bus, s->config_reg | (addr & 3), 2);
PCI_DPRINTF("readw addr " TARGET_FMT_plx " val %x\n",
- (target_phys_addr_t)addr, val);
+ (hwaddr)addr, val);
#ifdef TARGET_WORDS_BIGENDIAN
val = bswap16(val);
#endif
@@ -109,7 +109,7 @@
return 0xffffffff;
val = pci_data_read(s->bus, s->config_reg | (addr & 3), 4);
PCI_DPRINTF("readl addr " TARGET_FMT_plx " val %x\n",
- (target_phys_addr_t)addr, val);
+ (hwaddr)addr, val);
#ifdef TARGET_WORDS_BIGENDIAN
val = bswap32(val);
#endif
diff --git a/hw/pci-host/piix.c b/hw/pci-host/piix.c
index 78bb72f..43ee738 100644
--- a/hw/pci-host/piix.c
+++ b/hw/pci-host/piix.c
@@ -55,7 +55,7 @@
return (irq_num + slot_addend) & 3;
}
-static target_phys_addr_t isa_page_descs[384 / 4];
+static hwaddr isa_page_descs[384 / 4];
static uint8_t smm_enabled;
static int pci_irq_levels[4];
diff --git a/hw/pci/pci.c b/hw/pci/pci.c
index 03a2fc3..1eab25c 100644
--- a/hw/pci/pci.c
+++ b/hw/pci/pci.c
@@ -51,7 +51,7 @@
static void pci_update_mappings(PCIDevice *d);
static void pci_set_irq(void *opaque, int irq_num, int level);
-target_phys_addr_t pci_mem_base;
+hwaddr pci_mem_base;
static uint16_t pci_default_sub_vendor_id = PCI_SUBVENDOR_ID_REDHAT_QUMRANET;
static uint16_t pci_default_sub_device_id = PCI_SUBDEVICE_ID_QEMU;
static PCIBus *first_bus;
@@ -281,7 +281,7 @@
config_read, config_write);
return pci_dev;
}
-static target_phys_addr_t pci_to_cpu_addr(target_phys_addr_t addr)
+static hwaddr pci_to_cpu_addr(hwaddr addr)
{
return addr + pci_mem_base;
}
diff --git a/hw/timer/mc146818rtc.c b/hw/timer/mc146818rtc.c
index b4a77eb..5036d78 100644
--- a/hw/timer/mc146818rtc.c
+++ b/hw/timer/mc146818rtc.c
@@ -643,7 +643,7 @@
}
/* Memory mapped interface */
-static uint32_t cmos_mm_readb (void *opaque, target_phys_addr_t addr)
+static uint32_t cmos_mm_readb (void *opaque, hwaddr addr)
{
RTCState *s = opaque;
@@ -651,14 +651,14 @@
}
static void cmos_mm_writeb (void *opaque,
- target_phys_addr_t addr, uint32_t value)
+ hwaddr addr, uint32_t value)
{
RTCState *s = opaque;
cmos_ioport_write(s, addr >> s->it_shift, value & 0xFF);
}
-static uint32_t cmos_mm_readw (void *opaque, target_phys_addr_t addr)
+static uint32_t cmos_mm_readw (void *opaque, hwaddr addr)
{
RTCState *s = opaque;
uint32_t val;
@@ -671,7 +671,7 @@
}
static void cmos_mm_writew (void *opaque,
- target_phys_addr_t addr, uint32_t value)
+ hwaddr addr, uint32_t value)
{
RTCState *s = opaque;
#ifdef TARGET_WORDS_BIGENDIAN
@@ -680,7 +680,7 @@
cmos_ioport_write(s, addr >> s->it_shift, value & 0xFFFF);
}
-static uint32_t cmos_mm_readl (void *opaque, target_phys_addr_t addr)
+static uint32_t cmos_mm_readl (void *opaque, hwaddr addr)
{
RTCState *s = opaque;
uint32_t val;
@@ -693,7 +693,7 @@
}
static void cmos_mm_writel (void *opaque,
- target_phys_addr_t addr, uint32_t value)
+ hwaddr addr, uint32_t value)
{
RTCState *s = opaque;
#ifdef TARGET_WORDS_BIGENDIAN
@@ -714,7 +714,7 @@
&cmos_mm_writel,
};
-RTCState *rtc_mm_init(target_phys_addr_t base, int it_shift, qemu_irq irq,
+RTCState *rtc_mm_init(hwaddr base, int it_shift, qemu_irq irq,
int base_year)
{
RTCState *s;
diff --git a/hw/usb/hcd-ohci.c b/hw/usb/hcd-ohci.c
index 23e525d..1ac54a3 100644
--- a/hw/usb/hcd-ohci.c
+++ b/hw/usb/hcd-ohci.c
@@ -110,7 +110,7 @@
uint32_t htest;
/* SM501 local memory offset */
- target_phys_addr_t localmem_base;
+ hwaddr localmem_base;
/* Active packets. */
uint32_t old_ctl;
@@ -1397,7 +1397,7 @@
return;
}
-static uint32_t ohci_mem_read(void *ptr, target_phys_addr_t addr)
+static uint32_t ohci_mem_read(void *ptr, hwaddr addr)
{
OHCIState *ohci = ptr;
uint32_t retval;
@@ -1521,7 +1521,7 @@
return retval;
}
-static void ohci_mem_write(void *ptr, target_phys_addr_t addr, uint32_t val)
+static void ohci_mem_write(void *ptr, hwaddr addr, uint32_t val)
{
OHCIState *ohci = ptr;
@@ -1735,7 +1735,7 @@
PCI_ADDRESS_SPACE_MEM, ohci_mapfunc);
}
-void usb_ohci_init_pxa(target_phys_addr_t base, int num_ports, int devfn,
+void usb_ohci_init_pxa(hwaddr base, int num_ports, int devfn,
qemu_irq irq)
{
OHCIState *ohci = (OHCIState *)qemu_mallocz(sizeof(OHCIState));
diff --git a/include/disas/disas.h b/include/disas/disas.h
index f9287f7..254963c 100644
--- a/include/disas/disas.h
+++ b/include/disas/disas.h
@@ -22,7 +22,7 @@
#if defined(CONFIG_USER_ONLY)
typedef const char *(*lookup_symbol_t)(struct syminfo *s, target_ulong orig_addr);
#else
-typedef const char *(*lookup_symbol_t)(struct syminfo *s, target_phys_addr_t orig_addr);
+typedef const char *(*lookup_symbol_t)(struct syminfo *s, hwaddr orig_addr);
#endif
struct syminfo {
diff --git a/include/exec/cpu-all.h b/include/exec/cpu-all.h
index 1b7cd6d..e4dea7b 100644
--- a/include/exec/cpu-all.h
+++ b/include/exec/cpu-all.h
@@ -901,7 +901,7 @@
/* Return the physical page corresponding to a virtual one. Use it
only for debugging because no protection checks are done. Return -1
if no page found. */
-target_phys_addr_t cpu_get_phys_page_debug(CPUState *env, target_ulong addr);
+hwaddr cpu_get_phys_page_debug(CPUState *env, target_ulong addr);
/* memory API */
@@ -1005,8 +1005,8 @@
int cpu_physical_memory_get_dirty_tracking(void);
-int cpu_physical_sync_dirty_bitmap(target_phys_addr_t start_addr,
- target_phys_addr_t end_addr);
+int cpu_physical_sync_dirty_bitmap(hwaddr start_addr,
+ hwaddr end_addr);
void dump_exec_info(FILE *f,
int (*cpu_fprintf)(FILE *f, const char *fmt, ...));
@@ -1016,9 +1016,9 @@
* batching which can make a major impact on performance when using
* virtualization.
*/
-void qemu_register_coalesced_mmio(target_phys_addr_t addr, ram_addr_t size);
+void qemu_register_coalesced_mmio(hwaddr addr, ram_addr_t size);
-void qemu_unregister_coalesced_mmio(target_phys_addr_t addr, ram_addr_t size);
+void qemu_unregister_coalesced_mmio(hwaddr addr, ram_addr_t size);
void qemu_flush_coalesced_mmio_buffer(void);
diff --git a/include/exec/cpu-common.h b/include/exec/cpu-common.h
index 8245562..251a718 100644
--- a/include/exec/cpu-common.h
+++ b/include/exec/cpu-common.h
@@ -8,7 +8,7 @@
#endif
#ifdef TARGET_PHYS_ADDR_BITS
-#include "exec/targphys.h"
+#include "exec/hwaddr.h"
#endif
#ifndef NEED_CPU_H
@@ -25,16 +25,16 @@
/* memory API */
-typedef void CPUWriteMemoryFunc(void *opaque, target_phys_addr_t addr, uint32_t value);
-typedef uint32_t CPUReadMemoryFunc(void *opaque, target_phys_addr_t addr);
+typedef void CPUWriteMemoryFunc(void *opaque, hwaddr addr, uint32_t value);
+typedef uint32_t CPUReadMemoryFunc(void *opaque, hwaddr addr);
-void cpu_register_physical_memory_log(target_phys_addr_t start_addr,
+void cpu_register_physical_memory_log(hwaddr start_addr,
ram_addr_t size,
ram_addr_t phys_offset,
ram_addr_t region_offset,
bool log_dirty);
-static inline void cpu_register_physical_memory_offset(target_phys_addr_t start_addr,
+static inline void cpu_register_physical_memory_offset(hwaddr start_addr,
ram_addr_t size,
ram_addr_t phys_offset,
ram_addr_t region_offset)
@@ -43,14 +43,14 @@
region_offset, false);
}
-static inline void cpu_register_physical_memory(target_phys_addr_t start_addr,
+static inline void cpu_register_physical_memory(hwaddr start_addr,
ram_addr_t size,
ram_addr_t phys_offset)
{
cpu_register_physical_memory_offset(start_addr, size, phys_offset, 0);
}
-ram_addr_t cpu_get_physical_page_desc(target_phys_addr_t addr);
+ram_addr_t cpu_get_physical_page_desc(hwaddr addr);
ram_addr_t qemu_ram_alloc_from_ptr(DeviceState *dev, const char *name,
ram_addr_t size, void *host);
ram_addr_t qemu_ram_alloc(DeviceState *dev, const char *name, ram_addr_t size);
@@ -70,38 +70,38 @@
void *opaque);
void cpu_unregister_io_memory(int table_address);
-void cpu_physical_memory_rw(target_phys_addr_t addr, uint8_t *buf,
+void cpu_physical_memory_rw(hwaddr addr, uint8_t *buf,
int len, int is_write);
-static inline void cpu_physical_memory_read(target_phys_addr_t addr,
+static inline void cpu_physical_memory_read(hwaddr addr,
uint8_t *buf, int len)
{
cpu_physical_memory_rw(addr, buf, len, 0);
}
-static inline void cpu_physical_memory_write(target_phys_addr_t addr,
+static inline void cpu_physical_memory_write(hwaddr addr,
const uint8_t *buf, int len)
{
cpu_physical_memory_rw(addr, (uint8_t *)buf, len, 1);
}
-void *cpu_physical_memory_map(target_phys_addr_t addr,
- target_phys_addr_t *plen,
+void *cpu_physical_memory_map(hwaddr addr,
+ hwaddr *plen,
int is_write);
-void cpu_physical_memory_unmap(void *buffer, target_phys_addr_t len,
- int is_write, target_phys_addr_t access_len);
+void cpu_physical_memory_unmap(void *buffer, hwaddr len,
+ int is_write, hwaddr access_len);
void *cpu_register_map_client(void *opaque, void (*callback)(void *opaque));
void cpu_unregister_map_client(void *cookie);
-uint32_t ldub_phys(target_phys_addr_t addr);
-uint32_t lduw_phys(target_phys_addr_t addr);
-uint32_t ldl_phys(target_phys_addr_t addr);
-uint64_t ldq_phys(target_phys_addr_t addr);
-void stl_phys_notdirty(target_phys_addr_t addr, uint32_t val);
-void stq_phys_notdirty(target_phys_addr_t addr, uint64_t val);
-void stb_phys(target_phys_addr_t addr, uint32_t val);
-void stw_phys(target_phys_addr_t addr, uint32_t val);
-void stl_phys(target_phys_addr_t addr, uint32_t val);
-void stq_phys(target_phys_addr_t addr, uint64_t val);
+uint32_t ldub_phys(hwaddr addr);
+uint32_t lduw_phys(hwaddr addr);
+uint32_t ldl_phys(hwaddr addr);
+uint64_t ldq_phys(hwaddr addr);
+void stl_phys_notdirty(hwaddr addr, uint32_t val);
+void stq_phys_notdirty(hwaddr addr, uint64_t val);
+void stb_phys(hwaddr addr, uint32_t val);
+void stw_phys(hwaddr addr, uint32_t val);
+void stl_phys(hwaddr addr, uint32_t val);
+void stq_phys(hwaddr addr, uint64_t val);
-void cpu_physical_memory_write_rom(target_phys_addr_t addr,
+void cpu_physical_memory_write_rom(hwaddr addr,
const uint8_t *buf, int len);
#define IO_MEM_SHIFT 3
diff --git a/include/exec/cpu-defs.h b/include/exec/cpu-defs.h
index 7aa9ccc..98ca890 100644
--- a/include/exec/cpu-defs.h
+++ b/include/exec/cpu-defs.h
@@ -29,7 +29,7 @@
#include <signal.h>
#include "qemu/osdep.h"
#include "qemu/queue.h"
-#include "exec/targphys.h"
+#include "exec/hwaddr.h"
#ifndef TARGET_LONG_BITS
#error TARGET_LONG_BITS must be defined before including this header
@@ -107,7 +107,7 @@
#define CPU_COMMON_TLB \
/* The meaning of the MMU modes is defined in the target code. */ \
CPUTLBEntry tlb_table[NB_MMU_MODES][CPU_TLB_SIZE]; \
- target_phys_addr_t iotlb[NB_MMU_MODES][CPU_TLB_SIZE]; \
+ hwaddr iotlb[NB_MMU_MODES][CPU_TLB_SIZE]; \
target_ulong tlb_flush_addr; \
target_ulong tlb_flush_mask;
diff --git a/include/exec/exec-all.h b/include/exec/exec-all.h
index 9220175..cc5ae84 100644
--- a/include/exec/exec-all.h
+++ b/include/exec/exec-all.h
@@ -85,16 +85,16 @@
void cpu_exec_init(CPUState *env);
void QEMU_NORETURN cpu_loop_exit(void);
int page_unprotect(target_ulong address, unsigned long pc, void *puc);
-void tb_invalidate_phys_page_range(target_phys_addr_t start, target_phys_addr_t end,
+void tb_invalidate_phys_page_range(hwaddr start, hwaddr end,
int is_cpu_write_access);
void tb_invalidate_page_range(target_ulong start, target_ulong end);
void tlb_flush_page(CPUState *env, target_ulong addr);
void tlb_flush(CPUState *env, int flush_global);
int tlb_set_page_exec(CPUState *env, target_ulong vaddr,
- target_phys_addr_t paddr, int prot,
+ hwaddr paddr, int prot,
int mmu_idx, int is_softmmu);
static inline int tlb_set_page(CPUState *env1, target_ulong vaddr,
- target_phys_addr_t paddr, int prot,
+ hwaddr paddr, int prot,
int mmu_idx, int is_softmmu)
{
if (prot & PAGE_READ)
diff --git a/include/exec/hax.h b/include/exec/hax.h
index a29e45e..25ff5a2 100644
--- a/include/exec/hax.h
+++ b/include/exec/hax.h
@@ -20,7 +20,7 @@
int hax_sync_vcpus(void);
void hax_vcpu_sync_state(CPUState *env, int modified);
int hax_populate_ram(uint64_t va, uint32_t size);
-int hax_set_phys_mem(target_phys_addr_t start_addr,
+int hax_set_phys_mem(hwaddr start_addr,
ram_addr_t size, ram_addr_t phys_offset);
/* Check if QEMU need emulate guest execution */
int hax_vcpu_emulation_mode(CPUState *env);
diff --git a/include/exec/targphys.h b/include/exec/hwaddr.h
similarity index 64%
rename from include/exec/targphys.h
rename to include/exec/hwaddr.h
index 95648d6..9ccf56d 100644
--- a/include/exec/targphys.h
+++ b/include/exec/hwaddr.h
@@ -1,18 +1,18 @@
-/* Define target_phys_addr_t if it exists. */
+/* Define hwaddr if it exists. */
#ifndef TARGPHYS_H
#define TARGPHYS_H
#ifdef TARGET_PHYS_ADDR_BITS
-/* target_phys_addr_t is the type of a physical address (its size can
+/* hwaddr is the type of a physical address (its size can
be different from 'target_ulong'). */
#if TARGET_PHYS_ADDR_BITS == 32
-typedef uint32_t target_phys_addr_t;
+typedef uint32_t hwaddr;
#define TARGET_PHYS_ADDR_MAX UINT32_MAX
#define TARGET_FMT_plx "%08x"
#elif TARGET_PHYS_ADDR_BITS == 64
-typedef uint64_t target_phys_addr_t;
+typedef uint64_t hwaddr;
#define TARGET_PHYS_ADDR_MAX UINT64_MAX
#define TARGET_FMT_plx "%016" PRIx64
#endif
diff --git a/include/exec/softmmu_template.h b/include/exec/softmmu_template.h
index 82505ec..c3a88a5 100644
--- a/include/exec/softmmu_template.h
+++ b/include/exec/softmmu_template.h
@@ -65,7 +65,7 @@
static DATA_TYPE glue(glue(slow_ld, SUFFIX), MMUSUFFIX)(target_ulong addr,
int mmu_idx,
void *retaddr);
-static inline DATA_TYPE glue(io_read, SUFFIX)(target_phys_addr_t physaddr,
+static inline DATA_TYPE glue(io_read, SUFFIX)(hwaddr physaddr,
target_ulong addr,
void *retaddr)
{
@@ -101,7 +101,7 @@
DATA_TYPE res;
int index;
target_ulong tlb_addr;
- target_phys_addr_t ioaddr;
+ hwaddr ioaddr;
unsigned long addend;
void *retaddr;
#ifdef CONFIG_MEMCHECK_MMU
@@ -194,7 +194,7 @@
{
DATA_TYPE res, res1, res2;
int index, shift;
- target_phys_addr_t ioaddr;
+ hwaddr ioaddr;
unsigned long addend;
target_ulong tlb_addr, addr1, addr2;
@@ -244,7 +244,7 @@
int mmu_idx,
void *retaddr);
-static inline void glue(io_write, SUFFIX)(target_phys_addr_t physaddr,
+static inline void glue(io_write, SUFFIX)(hwaddr physaddr,
DATA_TYPE val,
target_ulong addr,
void *retaddr)
@@ -276,7 +276,7 @@
DATA_TYPE val,
int mmu_idx)
{
- target_phys_addr_t ioaddr;
+ hwaddr ioaddr;
unsigned long addend;
target_ulong tlb_addr;
void *retaddr;
@@ -368,7 +368,7 @@
int mmu_idx,
void *retaddr)
{
- target_phys_addr_t ioaddr;
+ hwaddr ioaddr;
unsigned long addend;
target_ulong tlb_addr;
int index, i;
diff --git a/include/hw/android/goldfish/vmem.h b/include/hw/android/goldfish/vmem.h
index 1e55246..6be87d7 100644
--- a/include/hw/android/goldfish/vmem.h
+++ b/include/hw/android/goldfish/vmem.h
@@ -19,7 +19,7 @@
int safe_memory_rw_debug(CPUState *env, target_ulong addr, uint8_t *buf,
int len, int is_write);
-target_phys_addr_t safe_get_phys_page_debug(CPUState *env, target_ulong addr);
+hwaddr safe_get_phys_page_debug(CPUState *env, target_ulong addr);
#endif /* GOLDFISH_VMEM_H */
diff --git a/include/hw/arm/arm.h b/include/hw/arm/arm.h
index 010acb4..ab7ed17 100644
--- a/include/hw/arm/arm.h
+++ b/include/hw/arm/arm.h
@@ -26,16 +26,16 @@
const char *kernel_filename;
const char *kernel_cmdline;
const char *initrd_filename;
- target_phys_addr_t loader_start;
- target_phys_addr_t smp_loader_start;
- target_phys_addr_t smp_priv_base;
+ hwaddr loader_start;
+ hwaddr smp_loader_start;
+ hwaddr smp_priv_base;
int nb_cpus;
int board_id;
int (*atag_board)(struct arm_boot_info *info, void *p);
/* Used internally by arm_boot.c */
int is_linux;
- target_phys_addr_t initrd_size;
- target_phys_addr_t entry;
+ hwaddr initrd_size;
+ hwaddr entry;
};
void arm_load_kernel(CPUState *env, struct arm_boot_info *info);
diff --git a/include/hw/arm/pxa.h b/include/hw/arm/pxa.h
index e524ef0..f1608ca 100644
--- a/include/hw/arm/pxa.h
+++ b/include/hw/arm/pxa.h
@@ -63,15 +63,15 @@
# define PXA2XX_INTERNAL_SIZE 0x40000
/* pxa2xx_pic.c */
-qemu_irq *pxa2xx_pic_init(target_phys_addr_t base, CPUState *env);
+qemu_irq *pxa2xx_pic_init(hwaddr base, CPUState *env);
/* pxa2xx_timer.c */
-void pxa25x_timer_init(target_phys_addr_t base, qemu_irq *irqs);
-void pxa27x_timer_init(target_phys_addr_t base, qemu_irq *irqs, qemu_irq irq4);
+void pxa25x_timer_init(hwaddr base, qemu_irq *irqs);
+void pxa27x_timer_init(hwaddr base, qemu_irq *irqs, qemu_irq irq4);
/* pxa2xx_gpio.c */
typedef struct PXA2xxGPIOInfo PXA2xxGPIOInfo;
-PXA2xxGPIOInfo *pxa2xx_gpio_init(target_phys_addr_t base,
+PXA2xxGPIOInfo *pxa2xx_gpio_init(hwaddr base,
CPUState *env, qemu_irq *pic, int lines);
qemu_irq *pxa2xx_gpio_in_get(PXA2xxGPIOInfo *s);
void pxa2xx_gpio_out_set(PXA2xxGPIOInfo *s,
@@ -80,29 +80,29 @@
/* pxa2xx_dma.c */
typedef struct PXA2xxDMAState PXA2xxDMAState;
-PXA2xxDMAState *pxa255_dma_init(target_phys_addr_t base,
+PXA2xxDMAState *pxa255_dma_init(hwaddr base,
qemu_irq irq);
-PXA2xxDMAState *pxa27x_dma_init(target_phys_addr_t base,
+PXA2xxDMAState *pxa27x_dma_init(hwaddr base,
qemu_irq irq);
void pxa2xx_dma_request(PXA2xxDMAState *s, int req_num, int on);
/* pxa2xx_lcd.c */
typedef struct PXA2xxLCDState PXA2xxLCDState;
-PXA2xxLCDState *pxa2xx_lcdc_init(target_phys_addr_t base,
+PXA2xxLCDState *pxa2xx_lcdc_init(hwaddr base,
qemu_irq irq);
void pxa2xx_lcd_vsync_notifier(PXA2xxLCDState *s, qemu_irq handler);
void pxa2xx_lcdc_oritentation(void *opaque, int angle);
/* pxa2xx_mmci.c */
typedef struct PXA2xxMMCIState PXA2xxMMCIState;
-PXA2xxMMCIState *pxa2xx_mmci_init(target_phys_addr_t base,
+PXA2xxMMCIState *pxa2xx_mmci_init(hwaddr base,
BlockDriverState *bd, qemu_irq irq, void *dma);
void pxa2xx_mmci_handlers(PXA2xxMMCIState *s, qemu_irq readonly,
qemu_irq coverswitch);
/* pxa2xx_pcmcia.c */
typedef struct PXA2xxPCMCIAState PXA2xxPCMCIAState;
-PXA2xxPCMCIAState *pxa2xx_pcmcia_init(target_phys_addr_t base);
+PXA2xxPCMCIAState *pxa2xx_pcmcia_init(hwaddr base);
int pxa2xx_pcmcia_attach(void *opaque, PCMCIACardState *card);
int pxa2xx_pcmcia_dettach(void *opaque);
void pxa2xx_pcmcia_set_irq_cb(void *opaque, qemu_irq irq, qemu_irq cd_irq);
@@ -113,14 +113,14 @@
int row;
};
typedef struct PXA2xxKeyPadState PXA2xxKeyPadState;
-PXA2xxKeyPadState *pxa27x_keypad_init(target_phys_addr_t base,
+PXA2xxKeyPadState *pxa27x_keypad_init(hwaddr base,
qemu_irq irq);
void pxa27x_register_keypad(PXA2xxKeyPadState *kp, struct keymap *map,
int size);
/* pxa2xx.c */
typedef struct PXA2xxI2CState PXA2xxI2CState;
-PXA2xxI2CState *pxa2xx_i2c_init(target_phys_addr_t base,
+PXA2xxI2CState *pxa2xx_i2c_init(hwaddr base,
qemu_irq irq, uint32_t page_size);
i2c_bus *pxa2xx_i2c_bus(PXA2xxI2CState *s);
@@ -143,23 +143,23 @@
PXA2xxKeyPadState *kp;
/* Power management */
- target_phys_addr_t pm_base;
+ hwaddr pm_base;
uint32_t pm_regs[0x40];
/* Clock management */
- target_phys_addr_t cm_base;
+ hwaddr cm_base;
uint32_t cm_regs[4];
uint32_t clkcfg;
/* Memory management */
- target_phys_addr_t mm_base;
+ hwaddr mm_base;
uint32_t mm_regs[0x1a];
/* Performance monitoring */
uint32_t pmnc;
/* Real-Time clock */
- target_phys_addr_t rtc_base;
+ hwaddr rtc_base;
uint32_t rttr;
uint32_t rtsr;
uint32_t rtar;
@@ -214,7 +214,7 @@
PXA2xxState *pxa255_init(unsigned int sdram_size);
/* usb-ohci.c */
-void usb_ohci_init_pxa(target_phys_addr_t base, int num_ports, int devfn,
+void usb_ohci_init_pxa(hwaddr base, int num_ports, int devfn,
qemu_irq irq);
#endif /* PXA_H */
diff --git a/include/hw/block/fdc.h b/include/hw/block/fdc.h
index 7b6a9de..f6436b6 100644
--- a/include/hw/block/fdc.h
+++ b/include/hw/block/fdc.h
@@ -4,8 +4,8 @@
typedef struct fdctrl_t fdctrl_t;
fdctrl_t *fdctrl_init (qemu_irq irq, int dma_chann, int mem_mapped,
- target_phys_addr_t io_base,
+ hwaddr io_base,
BlockDriverState **fds);
-fdctrl_t *sun4m_fdctrl_init (qemu_irq irq, target_phys_addr_t io_base,
+fdctrl_t *sun4m_fdctrl_init (qemu_irq irq, hwaddr io_base,
BlockDriverState **fds, qemu_irq *fdc_tc);
int fdctrl_get_drive_type(fdctrl_t *fdctrl, int drive_num);
diff --git a/include/hw/i386/pc.h b/include/hw/i386/pc.h
index 0afffa2..dcbaa8a 100644
--- a/include/hw/i386/pc.h
+++ b/include/hw/i386/pc.h
@@ -9,21 +9,21 @@
SerialState *serial_init(int base, qemu_irq irq, int baudbase,
CharDriverState *chr);
-SerialState *serial_mm_init (target_phys_addr_t base, int it_shift,
+SerialState *serial_mm_init (hwaddr base, int it_shift,
qemu_irq irq, int baudbase,
CharDriverState *chr, int ioregister);
-uint32_t serial_mm_readb (void *opaque, target_phys_addr_t addr);
-void serial_mm_writeb (void *opaque, target_phys_addr_t addr, uint32_t value);
-uint32_t serial_mm_readw (void *opaque, target_phys_addr_t addr);
-void serial_mm_writew (void *opaque, target_phys_addr_t addr, uint32_t value);
-uint32_t serial_mm_readl (void *opaque, target_phys_addr_t addr);
-void serial_mm_writel (void *opaque, target_phys_addr_t addr, uint32_t value);
+uint32_t serial_mm_readb (void *opaque, hwaddr addr);
+void serial_mm_writeb (void *opaque, hwaddr addr, uint32_t value);
+uint32_t serial_mm_readw (void *opaque, hwaddr addr);
+void serial_mm_writew (void *opaque, hwaddr addr, uint32_t value);
+uint32_t serial_mm_readl (void *opaque, hwaddr addr);
+void serial_mm_writel (void *opaque, hwaddr addr, uint32_t value);
/* parallel.c */
typedef struct ParallelState ParallelState;
ParallelState *parallel_init(int base, qemu_irq irq, CharDriverState *chr);
-ParallelState *parallel_mm_init(target_phys_addr_t base, int it_shift, qemu_irq irq, CharDriverState *chr);
+ParallelState *parallel_mm_init(hwaddr base, int it_shift, qemu_irq irq, CharDriverState *chr);
/* i8259.c */
@@ -82,8 +82,8 @@
void i8042_init(qemu_irq kbd_irq, qemu_irq mouse_irq, uint32_t io_base);
void i8042_mm_init(qemu_irq kbd_irq, qemu_irq mouse_irq,
- target_phys_addr_t base, ram_addr_t size,
- target_phys_addr_t mask);
+ hwaddr base, ram_addr_t size,
+ hwaddr mask);
/* mc146818rtc.c */
@@ -91,7 +91,7 @@
RTCState *rtc_init(int base, qemu_irq irq, int base_year);
RTCState *rtc_init_sqw(int base, qemu_irq irq, qemu_irq sqw_irq, int base_year);
-RTCState *rtc_mm_init(target_phys_addr_t base, int it_shift, qemu_irq irq,
+RTCState *rtc_mm_init(hwaddr base, int it_shift, qemu_irq irq,
int base_year);
void rtc_set_memory(RTCState *s, int addr, int val);
void rtc_set_date(RTCState *s, const struct tm *tm);
@@ -141,8 +141,8 @@
int isa_vga_init(void);
int pci_vga_init(PCIBus *bus,
unsigned long vga_bios_offset, int vga_bios_size);
-int isa_vga_mm_init(target_phys_addr_t vram_base,
- target_phys_addr_t ctrl_base, int it_shift);
+int isa_vga_mm_init(hwaddr vram_base,
+ hwaddr ctrl_base, int it_shift);
/* cirrus_vga.c */
void pci_cirrus_vga_init(PCIBus *bus);
diff --git a/include/hw/isa/isa.h b/include/hw/isa/isa.h
index 4c37370..4f5bc83 100644
--- a/include/hw/isa/isa.h
+++ b/include/hw/isa/isa.h
@@ -6,9 +6,9 @@
#include "exec/ioport.h"
#include "hw/qdev.h"
-extern target_phys_addr_t isa_mem_base;
+extern hwaddr isa_mem_base;
-void isa_mmio_init(target_phys_addr_t base, target_phys_addr_t size);
+void isa_mmio_init(hwaddr base, hwaddr size);
/* dma.c */
int DMA_get_channel_mode (int nchan);
diff --git a/include/hw/mips/mips.h b/include/hw/mips/mips.h
index 5fd72bb..faa86b6 100644
--- a/include/hw/mips/mips.h
+++ b/include/hw/mips/mips.h
@@ -6,19 +6,19 @@
PCIBus *pci_gt64120_init(qemu_irq *pic);
/* ds1225y.c */
-void *ds1225y_init(target_phys_addr_t mem_base, const char *filename);
+void *ds1225y_init(hwaddr mem_base, const char *filename);
void ds1225y_set_protection(void *opaque, int protection);
/* g364fb.c */
-int g364fb_mm_init(target_phys_addr_t vram_base,
- target_phys_addr_t ctrl_base, int it_shift,
+int g364fb_mm_init(hwaddr vram_base,
+ hwaddr ctrl_base, int it_shift,
qemu_irq irq);
/* mipsnet.c */
void mipsnet_init(int base, qemu_irq irq, NICInfo *nd);
/* jazz_led.c */
-extern void jazz_led_init(target_phys_addr_t base);
+extern void jazz_led_init(hwaddr base);
/* mips_int.c */
extern void cpu_mips_irq_init_cpu(CPUState *env);
@@ -28,7 +28,7 @@
/* rc4030.c */
typedef struct rc4030DMAState *rc4030_dma;
-void rc4030_dma_memory_rw(void *opaque, target_phys_addr_t addr, uint8_t *buf, int len, int is_write);
+void rc4030_dma_memory_rw(void *opaque, hwaddr addr, uint8_t *buf, int len, int is_write);
void rc4030_dma_read(void *dma, uint8_t *buf, int len);
void rc4030_dma_write(void *dma, uint8_t *buf, int len);
@@ -36,8 +36,8 @@
qemu_irq **irqs, rc4030_dma **dmas);
/* dp8393x.c */
-void dp83932_init(NICInfo *nd, target_phys_addr_t base, int it_shift,
+void dp83932_init(NICInfo *nd, hwaddr base, int it_shift,
qemu_irq irq, void* mem_opaque,
- void (*memory_rw)(void *opaque, target_phys_addr_t addr, uint8_t *buf, int len, int is_write));
+ void (*memory_rw)(void *opaque, hwaddr addr, uint8_t *buf, int len, int is_write));
#endif
diff --git a/include/hw/nvram/fw_cfg.h b/include/hw/nvram/fw_cfg.h
index f616ed2..5364ced 100644
--- a/include/hw/nvram/fw_cfg.h
+++ b/include/hw/nvram/fw_cfg.h
@@ -33,7 +33,7 @@
int fw_cfg_add_callback(void *opaque, uint16_t key, FWCfgCallback callback,
void *callback_opaque, uint8_t *data, size_t len);
void *fw_cfg_init(uint32_t ctl_port, uint32_t data_port,
- target_phys_addr_t crl_addr, target_phys_addr_t data_addr);
+ hwaddr crl_addr, hwaddr data_addr);
#endif /* NO_QEMU_PROTOS */
diff --git a/include/hw/pci/pci.h b/include/hw/pci/pci.h
index 6278556..1aef3e3 100644
--- a/include/hw/pci/pci.h
+++ b/include/hw/pci/pci.h
@@ -10,7 +10,7 @@
/* PCI bus */
-extern target_phys_addr_t pci_mem_base;
+extern hwaddr pci_mem_base;
#define PCI_DEVFN(slot, func) ((((slot) & 0x1f) << 3) | ((func) & 0x07))
#define PCI_SLOT(devfn) (((devfn) >> 3) & 0x1f)
@@ -240,8 +240,8 @@
PCIBus *pci_prep_init(qemu_irq *pic);
/* apb_pci.c */
-PCIBus *pci_apb_init(target_phys_addr_t special_base,
- target_phys_addr_t mem_base,
+PCIBus *pci_apb_init(hwaddr special_base,
+ hwaddr mem_base,
qemu_irq *pic, PCIBus **bus2, PCIBus **bus3);
/* sh_pci.c */
diff --git a/include/hw/sysbus.h b/include/hw/sysbus.h
index 33e507c..105806e 100644
--- a/include/hw/sysbus.h
+++ b/include/hw/sysbus.h
@@ -9,7 +9,7 @@
#define QDEV_MAX_IRQ 32
typedef struct SysBusDevice SysBusDevice;
-typedef void (*mmio_mapfunc)(SysBusDevice *dev, target_phys_addr_t addr);
+typedef void (*mmio_mapfunc)(SysBusDevice *dev, hwaddr addr);
struct SysBusDevice {
DeviceState qdev;
@@ -18,8 +18,8 @@
qemu_irq *irqp[QDEV_MAX_IRQ];
int num_mmio;
struct {
- target_phys_addr_t addr;
- target_phys_addr_t size;
+ hwaddr addr;
+ hwaddr size;
mmio_mapfunc cb;
int iofunc;
} mmio[QDEV_MAX_MMIO];
@@ -39,21 +39,21 @@
void sysbus_register_dev(const char *name, size_t size, sysbus_initfn init);
void sysbus_register_withprop(SysBusDeviceInfo *info);
void *sysbus_new(void);
-void sysbus_init_mmio(SysBusDevice *dev, target_phys_addr_t size, int iofunc);
-void sysbus_init_mmio_cb(SysBusDevice *dev, target_phys_addr_t size,
+void sysbus_init_mmio(SysBusDevice *dev, hwaddr size, int iofunc);
+void sysbus_init_mmio_cb(SysBusDevice *dev, hwaddr size,
mmio_mapfunc cb);
void sysbus_init_irq(SysBusDevice *dev, qemu_irq *p);
void sysbus_pass_irq(SysBusDevice *dev, SysBusDevice *target);
void sysbus_connect_irq(SysBusDevice *dev, int n, qemu_irq irq);
-void sysbus_mmio_map(SysBusDevice *dev, int n, target_phys_addr_t addr);
+void sysbus_mmio_map(SysBusDevice *dev, int n, hwaddr addr);
/* Legacy helper function for creating devices. */
DeviceState *sysbus_create_varargs(const char *name,
- target_phys_addr_t addr, ...);
+ hwaddr addr, ...);
static inline DeviceState *sysbus_create_simple(const char *name,
- target_phys_addr_t addr,
+ hwaddr addr,
qemu_irq irq)
{
return sysbus_create_varargs(name, addr, irq, NULL);
diff --git a/include/sysemu/dma.h b/include/sysemu/dma.h
index 9951ddd..7880383 100644
--- a/include/sysemu/dma.h
+++ b/include/sysemu/dma.h
@@ -16,20 +16,20 @@
#include "block/block.h"
typedef struct {
- target_phys_addr_t base;
- target_phys_addr_t len;
+ hwaddr base;
+ hwaddr len;
} ScatterGatherEntry;
typedef struct {
ScatterGatherEntry *sg;
int nsg;
int nalloc;
- target_phys_addr_t size;
+ hwaddr size;
} QEMUSGList;
void qemu_sglist_init(QEMUSGList *qsg, int alloc_hint);
-void qemu_sglist_add(QEMUSGList *qsg, target_phys_addr_t base,
- target_phys_addr_t len);
+void qemu_sglist_add(QEMUSGList *qsg, hwaddr base,
+ hwaddr len);
void qemu_sglist_destroy(QEMUSGList *qsg);
BlockDriverAIOCB *dma_bdrv_read(BlockDriverState *bs,
diff --git a/include/sysemu/kvm.h b/include/sysemu/kvm.h
index 47a2e1f..e59ae20 100644
--- a/include/sysemu/kvm.h
+++ b/include/sysemu/kvm.h
@@ -42,23 +42,23 @@
int kvm_cpu_exec(CPUState *env);
-void kvm_set_phys_mem(target_phys_addr_t start_addr,
+void kvm_set_phys_mem(hwaddr start_addr,
ram_addr_t size,
ram_addr_t phys_offset);
-int kvm_physical_sync_dirty_bitmap(target_phys_addr_t start_addr,
- target_phys_addr_t end_addr);
+int kvm_physical_sync_dirty_bitmap(hwaddr start_addr,
+ hwaddr end_addr);
-int kvm_log_start(target_phys_addr_t phys_addr, ram_addr_t size);
-int kvm_log_stop(target_phys_addr_t phys_addr, ram_addr_t size);
+int kvm_log_start(hwaddr phys_addr, ram_addr_t size);
+int kvm_log_stop(hwaddr phys_addr, ram_addr_t size);
int kvm_set_migration_log(int enable);
int kvm_has_sync_mmu(void);
void kvm_setup_guest_memory(void *start, size_t size);
-int kvm_coalesce_mmio_region(target_phys_addr_t start, ram_addr_t size);
-int kvm_uncoalesce_mmio_region(target_phys_addr_t start, ram_addr_t size);
+int kvm_coalesce_mmio_region(hwaddr start, ram_addr_t size);
+int kvm_uncoalesce_mmio_region(hwaddr start, ram_addr_t size);
int kvm_insert_breakpoint(CPUState *current_env, target_ulong addr,
target_ulong len, int type);
diff --git a/include/sysemu/sysemu.h b/include/sysemu/sysemu.h
index 44db207..821492b 100644
--- a/include/sysemu/sysemu.h
+++ b/include/sysemu/sysemu.h
@@ -225,17 +225,17 @@
/* loader.c */
int get_image_size(const char *filename);
int load_image(const char *filename, uint8_t *addr); /* deprecated */
-int load_image_targphys(const char *filename, target_phys_addr_t, int max_sz);
+int load_image_targphys(const char *filename, hwaddr, int max_sz);
int load_elf(const char *filename, int64_t address_offset,
uint64_t *pentry, uint64_t *lowaddr, uint64_t *highaddr);
-int load_aout(const char *filename, target_phys_addr_t addr, int max_sz);
+int load_aout(const char *filename, hwaddr addr, int max_sz);
int load_uimage(const char *filename, target_ulong *ep, target_ulong *loadaddr,
int *is_linux);
-int fread_targphys(target_phys_addr_t dst_addr, size_t nbytes, FILE *f);
-int fread_targphys_ok(target_phys_addr_t dst_addr, size_t nbytes, FILE *f);
-int read_targphys(int fd, target_phys_addr_t dst_addr, size_t nbytes);
-void pstrcpy_targphys(target_phys_addr_t dest, int buf_size,
+int fread_targphys(hwaddr dst_addr, size_t nbytes, FILE *f);
+int fread_targphys_ok(hwaddr dst_addr, size_t nbytes, FILE *f);
+int read_targphys(int fd, hwaddr dst_addr, size_t nbytes);
+void pstrcpy_targphys(hwaddr dest, int buf_size,
const char *source);
#endif
diff --git a/kvm-all.c b/kvm-all.c
index 7084b33..64e6858 100644
--- a/kvm-all.c
+++ b/kvm-all.c
@@ -41,7 +41,7 @@
typedef struct KVMSlot
{
- target_phys_addr_t start_addr;
+ hwaddr start_addr;
ram_addr_t memory_size;
ram_addr_t phys_offset;
int slot;
@@ -84,8 +84,8 @@
}
static KVMSlot *kvm_lookup_matching_slot(KVMState *s,
- target_phys_addr_t start_addr,
- target_phys_addr_t end_addr)
+ hwaddr start_addr,
+ hwaddr end_addr)
{
int i;
@@ -105,8 +105,8 @@
* Find overlapping slot with lowest start address
*/
static KVMSlot *kvm_lookup_overlapping_slot(KVMState *s,
- target_phys_addr_t start_addr,
- target_phys_addr_t end_addr)
+ hwaddr start_addr,
+ hwaddr end_addr)
{
KVMSlot *found = NULL;
int i;
@@ -219,7 +219,7 @@
/*
* dirty pages logging control
*/
-static int kvm_dirty_pages_log_change(target_phys_addr_t phys_addr,
+static int kvm_dirty_pages_log_change(hwaddr phys_addr,
ram_addr_t size, int flags, int mask)
{
KVMState *s = kvm_state;
@@ -249,14 +249,14 @@
return kvm_set_user_memory_region(s, mem);
}
-int kvm_log_start(target_phys_addr_t phys_addr, ram_addr_t size)
+int kvm_log_start(hwaddr phys_addr, ram_addr_t size)
{
return kvm_dirty_pages_log_change(phys_addr, size,
KVM_MEM_LOG_DIRTY_PAGES,
KVM_MEM_LOG_DIRTY_PAGES);
}
-int kvm_log_stop(target_phys_addr_t phys_addr, ram_addr_t size)
+int kvm_log_stop(hwaddr phys_addr, ram_addr_t size)
{
return kvm_dirty_pages_log_change(phys_addr, size,
0,
@@ -293,12 +293,12 @@
* @start_add: start of logged region.
* @end_addr: end of logged region.
*/
-int kvm_physical_sync_dirty_bitmap(target_phys_addr_t start_addr,
- target_phys_addr_t end_addr)
+int kvm_physical_sync_dirty_bitmap(hwaddr start_addr,
+ hwaddr end_addr)
{
KVMState *s = kvm_state;
unsigned long size, allocated_size = 0;
- target_phys_addr_t phys_addr;
+ hwaddr phys_addr;
ram_addr_t addr;
KVMDirtyLog d;
KVMSlot *mem;
@@ -347,7 +347,7 @@
return ret;
}
-int kvm_coalesce_mmio_region(target_phys_addr_t start, ram_addr_t size)
+int kvm_coalesce_mmio_region(hwaddr start, ram_addr_t size)
{
int ret = -ENOSYS;
#ifdef KVM_CAP_COALESCED_MMIO
@@ -366,7 +366,7 @@
return ret;
}
-int kvm_uncoalesce_mmio_region(target_phys_addr_t start, ram_addr_t size)
+int kvm_uncoalesce_mmio_region(hwaddr start, ram_addr_t size)
{
int ret = -ENOSYS;
#ifdef KVM_CAP_COALESCED_MMIO
@@ -670,7 +670,7 @@
return ret;
}
-void kvm_set_phys_mem(target_phys_addr_t start_addr,
+void kvm_set_phys_mem(hwaddr start_addr,
ram_addr_t size,
ram_addr_t phys_offset)
{
diff --git a/monitor.c b/monitor.c
index df74768..7866587 100644
--- a/monitor.c
+++ b/monitor.c
@@ -634,7 +634,7 @@
}
static void memory_dump(Monitor *mon, int count, int format, int wsize,
- target_phys_addr_t addr, int is_physical)
+ hwaddr addr, int is_physical)
{
CPUState *env;
int nb_per_line, l, line_size, i, max_digits, len;
@@ -781,14 +781,14 @@
int size, uint32_t addrh, uint32_t addrl)
{
- target_phys_addr_t addr = GET_TPHYSADDR(addrh, addrl);
+ hwaddr addr = GET_TPHYSADDR(addrh, addrl);
memory_dump(mon, count, format, size, addr, 1);
}
static void do_print(Monitor *mon, int count, int format, int size,
unsigned int valh, unsigned int vall)
{
- target_phys_addr_t val = GET_TPHYSADDR(valh, vall);
+ hwaddr val = GET_TPHYSADDR(valh, vall);
#if TARGET_PHYS_ADDR_BITS == 32
switch(format) {
case 'o':
@@ -868,7 +868,7 @@
FILE *f;
uint32_t l;
uint8_t buf[1024];
- target_phys_addr_t addr = GET_TPHYSADDR(valh, vall);
+ hwaddr addr = GET_TPHYSADDR(valh, vall);
f = fopen(filename, "wb");
if (!f) {
diff --git a/target-arm/helper.c b/target-arm/helper.c
index d4cd851..a59204f 100644
--- a/target-arm/helper.c
+++ b/target-arm/helper.c
@@ -1351,7 +1351,7 @@
return 1;
}
-target_phys_addr_t cpu_get_phys_page_debug(CPUState *env, target_ulong addr)
+hwaddr cpu_get_phys_page_debug(CPUState *env, target_ulong addr)
{
uint32_t phys_addr;
target_ulong page_size;
diff --git a/target-i386/hax-darwin.c b/target-i386/hax-darwin.c
index 19a1c2d..d8c3cf2 100644
--- a/target-i386/hax-darwin.c
+++ b/target-i386/hax-darwin.c
@@ -54,7 +54,7 @@
return 0;
}
-int hax_set_phys_mem(target_phys_addr_t start_addr, ram_addr_t size, ram_addr_t phys_offset)
+int hax_set_phys_mem(hwaddr start_addr, ram_addr_t size, ram_addr_t phys_offset)
{
struct hax_set_ram_info info, *pinfo = &info;
int ret;
diff --git a/target-i386/hax-windows.c b/target-i386/hax-windows.c
index 6c52388..e4026ff 100644
--- a/target-i386/hax-windows.c
+++ b/target-i386/hax-windows.c
@@ -93,7 +93,7 @@
}
-int hax_set_phys_mem(target_phys_addr_t start_addr, ram_addr_t size, ram_addr_t phys_offset)
+int hax_set_phys_mem(hwaddr start_addr, ram_addr_t size, ram_addr_t phys_offset)
{
struct hax_set_ram_info info, *pinfo = &info;
ram_addr_t flags = phys_offset & ~TARGET_PAGE_MASK;
diff --git a/target-i386/helper.c b/target-i386/helper.c
index b49ef14..856da20 100644
--- a/target-i386/helper.c
+++ b/target-i386/helper.c
@@ -953,7 +953,7 @@
return 1;
}
-target_phys_addr_t cpu_get_phys_page_debug(CPUState *env, target_ulong addr)
+hwaddr cpu_get_phys_page_debug(CPUState *env, target_ulong addr)
{
return addr;
}
@@ -984,7 +984,7 @@
uint64_t ptep, pte;
target_ulong pde_addr, pte_addr;
int error_code, is_dirty, prot, page_size, ret, is_write, is_user;
- target_phys_addr_t paddr;
+ hwaddr paddr;
uint32_t page_offset;
target_ulong vaddr, virt_addr;
@@ -1268,11 +1268,11 @@
return 1;
}
-target_phys_addr_t cpu_get_phys_page_debug(CPUState *env, target_ulong addr)
+hwaddr cpu_get_phys_page_debug(CPUState *env, target_ulong addr)
{
target_ulong pde_addr, pte_addr;
uint64_t pte;
- target_phys_addr_t paddr;
+ hwaddr paddr;
uint32_t page_offset;
int page_size;
diff --git a/target-i386/op_helper.c b/target-i386/op_helper.c
index d866a84..45e1005 100644
--- a/target-i386/op_helper.c
+++ b/target-i386/op_helper.c
@@ -4900,7 +4900,7 @@
}
#else
-static inline void svm_save_seg(target_phys_addr_t addr,
+static inline void svm_save_seg(hwaddr addr,
const SegmentCache *sc)
{
stw_phys(addr + offsetof(struct vmcb_seg, selector),
@@ -4913,7 +4913,7 @@
((sc->flags >> 8) & 0xff) | ((sc->flags >> 12) & 0x0f00));
}
-static inline void svm_load_seg(target_phys_addr_t addr, SegmentCache *sc)
+static inline void svm_load_seg(hwaddr addr, SegmentCache *sc)
{
unsigned int flags;
@@ -4924,7 +4924,7 @@
sc->flags = ((flags & 0xff) << 8) | ((flags & 0x0f00) << 12);
}
-static inline void svm_load_seg_cache(target_phys_addr_t addr,
+static inline void svm_load_seg_cache(hwaddr addr,
CPUState *env, int seg_reg)
{
SegmentCache sc1, *sc = &sc1;
diff --git a/target-mips/cpu.h b/target-mips/cpu.h
index 33fb8f2..edbc3bf 100644
--- a/target-mips/cpu.h
+++ b/target-mips/cpu.h
@@ -39,7 +39,7 @@
typedef struct CPUMIPSTLBContext CPUMIPSTLBContext;
struct CPUMIPSTLBContext {
uint32_t nb_tlb;
- int (*map_address) (struct CPUMIPSState *env, target_phys_addr_t *physical, int *prot, target_ulong address, int rw, int access_type);
+ int (*map_address) (struct CPUMIPSState *env, hwaddr *physical, int *prot, target_ulong address, int rw, int access_type);
void (*helper_tlbwi) (void);
void (*helper_tlbwr) (void);
void (*helper_tlbp) (void);
@@ -465,11 +465,11 @@
struct QEMUTimer *timer; /* Internal timer */
};
-int no_mmu_map_address (CPUMIPSState *env, target_phys_addr_t *physical, int *prot,
+int no_mmu_map_address (CPUMIPSState *env, hwaddr *physical, int *prot,
target_ulong address, int rw, int access_type);
-int fixed_mmu_map_address (CPUMIPSState *env, target_phys_addr_t *physical, int *prot,
+int fixed_mmu_map_address (CPUMIPSState *env, hwaddr *physical, int *prot,
target_ulong address, int rw, int access_type);
-int r4k_map_address (CPUMIPSState *env, target_phys_addr_t *physical, int *prot,
+int r4k_map_address (CPUMIPSState *env, hwaddr *physical, int *prot,
target_ulong address, int rw, int access_type);
void r4k_helper_tlbwi (void);
void r4k_helper_tlbwr (void);
@@ -477,7 +477,7 @@
void r4k_helper_tlbr (void);
void mips_cpu_list (FILE *f, int (*cpu_fprintf)(FILE *f, const char *fmt, ...));
-void do_unassigned_access(target_phys_addr_t addr, int is_write, int is_exec,
+void do_unassigned_access(hwaddr addr, int is_write, int is_exec,
int unused, int size);
#define cpu_init cpu_mips_init
@@ -629,7 +629,7 @@
int mmu_idx, int is_softmmu);
#define cpu_handle_mmu_fault cpu_mips_handle_mmu_fault
void do_interrupt (CPUState *env);
-target_phys_addr_t cpu_mips_translate_address (CPUState *env, target_ulong address,
+hwaddr cpu_mips_translate_address (CPUState *env, target_ulong address,
int rw);
static inline void cpu_pc_from_tb(CPUState *env, TranslationBlock *tb)
diff --git a/target-mips/helper.c b/target-mips/helper.c
index 6179159..fe97355 100644
--- a/target-mips/helper.c
+++ b/target-mips/helper.c
@@ -35,7 +35,7 @@
};
/* no MMU emulation */
-int no_mmu_map_address (CPUState *env, target_phys_addr_t *physical, int *prot,
+int no_mmu_map_address (CPUState *env, hwaddr *physical, int *prot,
target_ulong address, int rw, int access_type)
{
*physical = address;
@@ -44,7 +44,7 @@
}
/* fixed mapping MMU emulation */
-int fixed_mmu_map_address (CPUState *env, target_phys_addr_t *physical, int *prot,
+int fixed_mmu_map_address (CPUState *env, hwaddr *physical, int *prot,
target_ulong address, int rw, int access_type)
{
if (address <= (int32_t)0x7FFFFFFFUL) {
@@ -62,7 +62,7 @@
}
/* MIPS32/MIPS64 R4000-style MMU emulation */
-int r4k_map_address (CPUState *env, target_phys_addr_t *physical, int *prot,
+int r4k_map_address (CPUState *env, hwaddr *physical, int *prot,
target_ulong address, int rw, int access_type)
{
uint8_t ASID = env->CP0_EntryHi & 0xFF;
@@ -105,7 +105,7 @@
}
#if !defined(CONFIG_USER_ONLY)
-static int get_physical_address (CPUState *env, target_phys_addr_t *physical,
+static int get_physical_address (CPUState *env, hwaddr *physical,
int *prot, target_ulong address,
int rw, int access_type)
{
@@ -439,7 +439,7 @@
int mmu_idx, int is_softmmu)
{
#if !defined(CONFIG_USER_ONLY)
- target_phys_addr_t physical;
+ hwaddr physical;
int prot;
#endif
int exception = 0, error_code = 0;
@@ -483,9 +483,9 @@
}
#if !defined(CONFIG_USER_ONLY)
-target_phys_addr_t cpu_mips_translate_address(CPUState *env, target_ulong address, int rw)
+hwaddr cpu_mips_translate_address(CPUState *env, target_ulong address, int rw)
{
- target_phys_addr_t physical;
+ hwaddr physical;
int prot;
int access_type;
int ret = 0;
@@ -505,12 +505,12 @@
}
#endif
-target_phys_addr_t cpu_get_phys_page_debug(CPUState *env, target_ulong addr)
+hwaddr cpu_get_phys_page_debug(CPUState *env, target_ulong addr)
{
#if defined(CONFIG_USER_ONLY)
return addr;
#else
- target_phys_addr_t phys_addr;
+ hwaddr phys_addr;
int prot, ret;
ret = get_physical_address(env, &phys_addr, &prot, addr, 0, ACCESS_INT);
diff --git a/target-mips/op_helper.c b/target-mips/op_helper.c
index 4a393f6..ce31a48 100644
--- a/target-mips/op_helper.c
+++ b/target-mips/op_helper.c
@@ -277,9 +277,9 @@
#ifndef CONFIG_USER_ONLY
-static inline target_phys_addr_t do_translate_address(target_ulong address, int rw)
+static inline hwaddr do_translate_address(target_ulong address, int rw)
{
- target_phys_addr_t lladdr;
+ hwaddr lladdr;
lladdr = cpu_mips_translate_address(env, address, rw);
@@ -1932,7 +1932,7 @@
env = saved_env;
}
-void do_unassigned_access(target_phys_addr_t addr, int is_write, int is_exec,
+void do_unassigned_access(hwaddr addr, int is_write, int is_exec,
int unused, int size)
{
if (is_exec)
diff --git a/vl-android.c b/vl-android.c
index b3482c5..4054a1c 100644
--- a/vl-android.c
+++ b/vl-android.c
@@ -69,7 +69,7 @@
#include "android/snapshot.h"
#include "android/opengles.h"
#include "android/multitouch-screen.h"
-#include "exec/targphys.h"
+#include "exec/hwaddr.h"
#include "android/tcpdump.h"
#ifdef CONFIG_MEMCHECK
@@ -436,7 +436,7 @@
/***********************************************************/
/* x86 ISA bus support */
-target_phys_addr_t isa_mem_base = 0;
+hwaddr isa_mem_base = 0;
PicState2 *isa_pic;
static IOPortReadFunc default_ioport_readb, default_ioport_readw, default_ioport_readl;
diff --git a/vl.c b/vl.c
index aef8dfd..c5b66ea 100644
--- a/vl.c
+++ b/vl.c
@@ -264,7 +264,7 @@
/***********************************************************/
/* x86 ISA bus support */
-target_phys_addr_t isa_mem_base = 0;
+hwaddr isa_mem_base = 0;
PicState2 *isa_pic;
static IOPortReadFunc default_ioport_readb, default_ioport_readw, default_ioport_readl;