Move singlestep_enabled to CPUState.
The previous patch forgot to move this field from CPU_COMMON to
CPUState, so do it here.
Change-Id: I71ed4605c939eb6c23d3e70b08ea89e59842cdd0
diff --git a/cpu-exec.c b/cpu-exec.c
index 6dfd0fc..3cfc079 100644
--- a/cpu-exec.c
+++ b/cpu-exec.c
@@ -327,7 +327,7 @@
for(;;) {
interrupt_request = cpu->interrupt_request;
if (unlikely(need_handle_intr_request(env))) {
- if (unlikely(env->singlestep_enabled & SSTEP_NOIRQ)) {
+ if (unlikely(cpu->singlestep_enabled & SSTEP_NOIRQ)) {
/* Mask out external interrupts for this step. */
interrupt_request &= ~CPU_INTERRUPT_SSTEP_MASK;
}
diff --git a/exec.c b/exec.c
index 6a46d48..8c1639f 100644
--- a/exec.c
+++ b/exec.c
@@ -383,17 +383,17 @@
/* enable or disable single step mode. EXCP_DEBUG is returned by the
CPU loop after each instruction */
-void cpu_single_step(CPUOldState *env, int enabled)
+void cpu_single_step(CPUState *cpu, int enabled)
{
#if defined(TARGET_HAS_ICE)
- if (env->singlestep_enabled != enabled) {
- env->singlestep_enabled = enabled;
+ if (cpu->singlestep_enabled != enabled) {
+ cpu->singlestep_enabled = enabled;
if (kvm_enabled()) {
- kvm_update_guest_debug(env, 0);
+ kvm_update_guest_debug(cpu->env_ptr, 0);
} else {
/* must flush all the translated code to avoid inconsistencies */
/* XXX: only flush what is necessary */
- tb_flush(env);
+ tb_flush(cpu->env_ptr);
}
}
#endif
diff --git a/gdbstub.c b/gdbstub.c
index 92c4153..28cfe1c 100644
--- a/gdbstub.c
+++ b/gdbstub.c
@@ -1650,7 +1650,7 @@
addr = strtoull(p, (char **)&p, 16);
gdb_set_cpu_pc(s, addr);
}
- cpu_single_step(s->c_cpu, sstep_flags);
+ cpu_single_step(ENV_GET_CPU(s->c_cpu), sstep_flags);
gdb_continue(s);
return RS_IDLE;
case 'F':
@@ -1971,7 +1971,7 @@
return;
/* disable single step if it was enable */
- cpu_single_step(env, 0);
+ cpu_single_step(ENV_GET_CPU(env), 0);
if (reason == EXCP_DEBUG) {
if (env->watchpoint_hit) {
diff --git a/include/exec/cpu-all.h b/include/exec/cpu-all.h
index b963280..d79680c 100644
--- a/include/exec/cpu-all.h
+++ b/include/exec/cpu-all.h
@@ -456,7 +456,7 @@
#define SSTEP_NOIRQ 0x2 /* Do not use IRQ while single stepping */
#define SSTEP_NOTIMER 0x4 /* Do not Timers while single stepping */
-void cpu_single_step(CPUOldState *env, int enabled);
+void cpu_single_step(CPUState *cpu, int enabled);
void cpu_reset(CPUOldState *s);
int cpu_is_stopped(CPUOldState *env);
void run_on_cpu(CPUOldState *env, void (*func)(void *data), void *data);
diff --git a/include/exec/cpu-defs.h b/include/exec/cpu-defs.h
index e993938..4f36369 100644
--- a/include/exec/cpu-defs.h
+++ b/include/exec/cpu-defs.h
@@ -175,7 +175,6 @@
/* from this point: preserved by CPU reset */ \
/* ice debug support */ \
QTAILQ_HEAD(breakpoints_head, CPUBreakpoint) breakpoints; \
- int singlestep_enabled; \
\
QTAILQ_HEAD(watchpoints_head, CPUWatchpoint) watchpoints; \
CPUWatchpoint *watchpoint_hit; \
diff --git a/include/qom/cpu.h b/include/qom/cpu.h
index 80f1c1f..af747cf 100644
--- a/include/qom/cpu.h
+++ b/include/qom/cpu.h
@@ -56,6 +56,7 @@
void *env_ptr; /* CPUArchState */
struct TranslationBlock *current_tb; /* currently executing TB */
+ int singlestep_enabled;
struct GDBRegisterState *gdb_regs;
QTAILQ_ENTRY(CPUState) node; /* next CPU sharing TB cache */
diff --git a/kvm-all.c b/kvm-all.c
index bf72708..4edab48 100644
--- a/kvm-all.c
+++ b/kvm-all.c
@@ -914,7 +914,7 @@
struct kvm_guest_debug dbg;
dbg.control = 0;
- if (env->singlestep_enabled)
+ if (ENV_GET_CPU(env)->singlestep_enabled)
dbg.control = KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_SINGLESTEP;
kvm_arch_update_guest_debug(env, &dbg);
diff --git a/target-arm/translate.c b/target-arm/translate.c
index c824c7a..24c881d 100644
--- a/target-arm/translate.c
+++ b/target-arm/translate.c
@@ -9713,7 +9713,7 @@
dc->is_jmp = DISAS_NEXT;
dc->pc = pc_start;
- dc->singlestep_enabled = env->singlestep_enabled;
+ dc->singlestep_enabled = ENV_GET_CPU(env)->singlestep_enabled;
dc->condjmp = 0;
dc->thumb = ARM_TBFLAG_THUMB(tb->flags);
dc->condexec_mask = (ARM_TBFLAG_CONDEXEC(tb->flags) & 0xf) << 1;
@@ -9865,7 +9865,7 @@
* ensures prefetch aborts occur at the right place. */
num_insns ++;
} while (!dc->is_jmp && tcg_ctx.gen_opc_ptr < gen_opc_end &&
- !env->singlestep_enabled &&
+ !ENV_GET_CPU(env)->singlestep_enabled &&
!singlestep &&
dc->pc < next_page_start &&
num_insns < max_insns);
@@ -9882,7 +9882,7 @@
/* At this stage dc->condjmp will only be set when the skipped
instruction was a conditional branch or trap, and the PC has
already been written. */
- if (unlikely(env->singlestep_enabled)) {
+ if (unlikely(ENV_GET_CPU(env)->singlestep_enabled)) {
/* Make sure the pc is updated, and raise a debug exception. */
if (dc->condjmp) {
gen_set_condexec(dc);
diff --git a/target-i386/kvm.c b/target-i386/kvm.c
index 0201ea8..866f7a7 100644
--- a/target-i386/kvm.c
+++ b/target-i386/kvm.c
@@ -900,7 +900,7 @@
if (arch_info->exception == 1) {
if (arch_info->dr6 & (1 << 14)) {
- if (cpu_single_env->singlestep_enabled)
+ if (current_cpu->singlestep_enabled)
handle = 1;
} else {
for (n = 0; n < 4; n++)
diff --git a/target-i386/translate.c b/target-i386/translate.c
index 6e9b1bc..a9cf004 100644
--- a/target-i386/translate.c
+++ b/target-i386/translate.c
@@ -7805,7 +7805,7 @@
dc->cpl = (flags >> HF_CPL_SHIFT) & 3;
dc->iopl = (flags >> IOPL_SHIFT) & 3;
dc->tf = (flags >> TF_SHIFT) & 1;
- dc->singlestep_enabled = env->singlestep_enabled;
+ dc->singlestep_enabled = ENV_GET_CPU(env)->singlestep_enabled;
dc->cc_op = CC_OP_DYNAMIC;
dc->cs_base = cs_base;
dc->tb = tb;
@@ -7827,7 +7827,7 @@
dc->code64 = (flags >> HF_CS64_SHIFT) & 1;
#endif
dc->flags = flags;
- dc->jmp_opt = !(dc->tf || env->singlestep_enabled ||
+ dc->jmp_opt = !(dc->tf || ENV_GET_CPU(env)->singlestep_enabled ||
(flags & HF_INHIBIT_IRQ_MASK)
#ifndef CONFIG_SOFTMMU
|| (flags & HF_SOFTMMU_MASK)
diff --git a/target-mips/translate.c b/target-mips/translate.c
index f29e7dc..3952979 100755
--- a/target-mips/translate.c
+++ b/target-mips/translate.c
@@ -8299,7 +8299,7 @@
gen_opc_end = tcg_ctx.gen_opc_buf + OPC_MAX_SIZE;
ctx.pc = pc_start;
ctx.saved_pc = -1;
- ctx.singlestep_enabled = env->singlestep_enabled;
+ ctx.singlestep_enabled = ENV_GET_CPU(env)->singlestep_enabled;
ctx.tb = tb;
ctx.bstate = BS_NONE;
/* Restore delay slot state from the tb context. */
@@ -8359,7 +8359,7 @@
This is what GDB expects and is consistent with what the
hardware does (e.g. if a delay slot instruction faults, the
reported PC is the PC of the branch). */
- if (env->singlestep_enabled && (ctx.hflags & MIPS_HFLAG_BMASK) == 0)
+ if (ENV_GET_CPU(env)->singlestep_enabled && (ctx.hflags & MIPS_HFLAG_BMASK) == 0)
break;
/* Do not split a branch instruction and its delay slot into two
@@ -8379,7 +8379,7 @@
}
if (tb->cflags & CF_LAST_IO)
gen_io_end();
- if (env->singlestep_enabled && ctx.bstate != BS_BRANCH) {
+ if (ENV_GET_CPU(env)->singlestep_enabled && ctx.bstate != BS_BRANCH) {
save_cpu_state(&ctx, ctx.bstate == BS_NONE);
gen_helper_1i(raise_exception, cpu_env, EXCP_DEBUG);
} else {