blob: 892d6fe9087c71b5a9007976ce46cdf176fc3e1e [file] [log] [blame]
Wichert Akkerman76baf7c1999-02-19 00:21:36 +00001/*
2 * Copyright (c) 1991, 1992 Paul Kranenburg <pk@cs.few.eur.nl>
3 * Copyright (c) 1993 Branko Lankester <branko@hacktic.nl>
4 * Copyright (c) 1993, 1994, 1995, 1996 Rick Sladkey <jrs@world.std.com>
Wichert Akkerman4dc8a2a1999-12-23 14:20:14 +00005 * Copyright (c) 1996-1999 Wichert Akkerman <wichert@cistron.nl>
6 * Copyright (c) 1999 IBM Deutschland Entwicklung GmbH, IBM Corporation
7 * Linux for s390 port by D.J. Barrow
8 * <barrow_dj@mail.yahoo.com,djbarrow@de.ibm.com>
Wichert Akkermanccef6372002-05-01 16:39:22 +00009 * Copyright (c) 2000 PocketPenguins Inc. Linux for Hitachi SuperH
10 * port by Greg Banks <gbanks@pocketpenguins.com>
Wichert Akkerman4dc8a2a1999-12-23 14:20:14 +000011 *
Wichert Akkerman76baf7c1999-02-19 00:21:36 +000012 * All rights reserved.
13 *
14 * Redistribution and use in source and binary forms, with or without
15 * modification, are permitted provided that the following conditions
16 * are met:
17 * 1. Redistributions of source code must retain the above copyright
18 * notice, this list of conditions and the following disclaimer.
19 * 2. Redistributions in binary form must reproduce the above copyright
20 * notice, this list of conditions and the following disclaimer in the
21 * documentation and/or other materials provided with the distribution.
22 * 3. The name of the author may not be used to endorse or promote products
23 * derived from this software without specific prior written permission.
24 *
25 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
26 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
27 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
28 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
29 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
30 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
31 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
32 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
33 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
34 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
Wichert Akkerman76baf7c1999-02-19 00:21:36 +000035 */
36
37#include "defs.h"
Wichert Akkerman76baf7c1999-02-19 00:21:36 +000038#include <fcntl.h>
39#include <sys/stat.h>
Wichert Akkerman76baf7c1999-02-19 00:21:36 +000040#include <sys/user.h>
Dmitry V. Levinc41808b2013-03-18 00:52:29 +000041#ifdef HAVE_ELF_H
42# include <elf.h>
43#endif
Wichert Akkerman76baf7c1999-02-19 00:21:36 +000044
Wichert Akkerman36915a11999-07-13 15:45:02 +000045#ifdef HAVE_SYS_REG_H
Wichert Akkerman76baf7c1999-02-19 00:21:36 +000046# include <sys/reg.h>
Wichert Akkerman15dea971999-10-06 13:06:34 +000047#endif
Wichert Akkerman76baf7c1999-02-19 00:21:36 +000048
Roland McGrath5bd7cf82003-01-24 04:31:18 +000049#ifdef HAVE_LINUX_PTRACE_H
Denys Vlasenko84703742012-02-25 02:38:52 +010050# undef PTRACE_SYSCALL
Roland McGrathfb1bc072004-03-01 21:29:24 +000051# ifdef HAVE_STRUCT_IA64_FPREG
52# define ia64_fpreg XXX_ia64_fpreg
53# endif
54# ifdef HAVE_STRUCT_PT_ALL_USER_REGS
55# define pt_all_user_regs XXX_pt_all_user_regs
56# endif
Ali Polatel0b4060f2013-09-24 20:04:32 +030057# ifdef HAVE_STRUCT_PTRACE_PEEKSIGINFO_ARGS
58# define ptrace_peeksiginfo_args XXX_ptrace_peeksiginfo_args
59# endif
Denys Vlasenko84703742012-02-25 02:38:52 +010060# include <linux/ptrace.h>
Ali Polatel0b4060f2013-09-24 20:04:32 +030061# undef ptrace_peeksiginfo_args
Roland McGrathfb1bc072004-03-01 21:29:24 +000062# undef ia64_fpreg
63# undef pt_all_user_regs
Roland McGrath5bd7cf82003-01-24 04:31:18 +000064#endif
65
Denys Vlasenko84703742012-02-25 02:38:52 +010066#if defined(SPARC64)
Roland McGrath6d1a65c2004-07-12 07:44:08 +000067# define r_pc r_tpc
68# undef PTRACE_GETREGS
69# define PTRACE_GETREGS PTRACE_GETREGS64
70# undef PTRACE_SETREGS
71# define PTRACE_SETREGS PTRACE_SETREGS64
Denys Vlasenko84703742012-02-25 02:38:52 +010072#endif
Roland McGrath6d1a65c2004-07-12 07:44:08 +000073
Denys Vlasenko84703742012-02-25 02:38:52 +010074#if defined(IA64)
Wichert Akkerman8b1b40c2000-02-03 21:58:30 +000075# include <asm/ptrace_offsets.h>
76# include <asm/rse.h>
77#endif
78
Dmitry V. Levin0ed617b2014-04-25 23:30:54 +000079#include "xlat/ptrace_cmds.h"
Dmitry V. Levin0ed617b2014-04-25 23:30:54 +000080#include "xlat/ptrace_setoptions_flags.h"
Dmitry V. Levin0ed617b2014-04-25 23:30:54 +000081#include "xlat/nt_descriptor_types.h"
Dmitry V. Levinc41808b2013-03-18 00:52:29 +000082
Denys Vlasenko513e9c22012-03-21 14:39:22 +010083#define uoff(member) offsetof(struct user, member)
Dmitry V. Levinc6ce4fd2014-12-11 19:25:02 +000084#define XLAT_UOFF(member) { uoff(member), "offsetof(struct user, " #member ")" }
Denys Vlasenko513e9c22012-03-21 14:39:22 +010085
Roland McGrathd9f816f2004-09-04 03:39:20 +000086const struct xlat struct_user_offsets[] = {
Denys Vlasenko3e3490a2012-03-17 01:27:37 +010087#if defined(S390) || defined(S390X)
Wichert Akkerman4dc8a2a1999-12-23 14:20:14 +000088 { PT_PSWMASK, "psw_mask" },
89 { PT_PSWADDR, "psw_addr" },
90 { PT_GPR0, "gpr0" },
91 { PT_GPR1, "gpr1" },
92 { PT_GPR2, "gpr2" },
93 { PT_GPR3, "gpr3" },
94 { PT_GPR4, "gpr4" },
95 { PT_GPR5, "gpr5" },
96 { PT_GPR6, "gpr6" },
97 { PT_GPR7, "gpr7" },
98 { PT_GPR8, "gpr8" },
99 { PT_GPR9, "gpr9" },
100 { PT_GPR10, "gpr10" },
101 { PT_GPR11, "gpr11" },
102 { PT_GPR12, "gpr12" },
103 { PT_GPR13, "gpr13" },
104 { PT_GPR14, "gpr14" },
105 { PT_GPR15, "gpr15" },
106 { PT_ACR0, "acr0" },
107 { PT_ACR1, "acr1" },
108 { PT_ACR2, "acr2" },
109 { PT_ACR3, "acr3" },
110 { PT_ACR4, "acr4" },
111 { PT_ACR5, "acr5" },
112 { PT_ACR6, "acr6" },
113 { PT_ACR7, "acr7" },
114 { PT_ACR8, "acr8" },
115 { PT_ACR9, "acr9" },
116 { PT_ACR10, "acr10" },
117 { PT_ACR11, "acr11" },
118 { PT_ACR12, "acr12" },
119 { PT_ACR13, "acr13" },
120 { PT_ACR14, "acr14" },
121 { PT_ACR15, "acr15" },
122 { PT_ORIGGPR2, "orig_gpr2" },
123 { PT_FPC, "fpc" },
Denys Vlasenko3e3490a2012-03-17 01:27:37 +0100124#if defined(S390)
Wichert Akkerman4dc8a2a1999-12-23 14:20:14 +0000125 { PT_FPR0_HI, "fpr0.hi" },
126 { PT_FPR0_LO, "fpr0.lo" },
127 { PT_FPR1_HI, "fpr1.hi" },
128 { PT_FPR1_LO, "fpr1.lo" },
129 { PT_FPR2_HI, "fpr2.hi" },
130 { PT_FPR2_LO, "fpr2.lo" },
131 { PT_FPR3_HI, "fpr3.hi" },
132 { PT_FPR3_LO, "fpr3.lo" },
133 { PT_FPR4_HI, "fpr4.hi" },
134 { PT_FPR4_LO, "fpr4.lo" },
135 { PT_FPR5_HI, "fpr5.hi" },
136 { PT_FPR5_LO, "fpr5.lo" },
137 { PT_FPR6_HI, "fpr6.hi" },
138 { PT_FPR6_LO, "fpr6.lo" },
139 { PT_FPR7_HI, "fpr7.hi" },
140 { PT_FPR7_LO, "fpr7.lo" },
141 { PT_FPR8_HI, "fpr8.hi" },
142 { PT_FPR8_LO, "fpr8.lo" },
143 { PT_FPR9_HI, "fpr9.hi" },
144 { PT_FPR9_LO, "fpr9.lo" },
145 { PT_FPR10_HI, "fpr10.hi" },
146 { PT_FPR10_LO, "fpr10.lo" },
147 { PT_FPR11_HI, "fpr11.hi" },
148 { PT_FPR11_LO, "fpr11.lo" },
149 { PT_FPR12_HI, "fpr12.hi" },
150 { PT_FPR12_LO, "fpr12.lo" },
151 { PT_FPR13_HI, "fpr13.hi" },
152 { PT_FPR13_LO, "fpr13.lo" },
153 { PT_FPR14_HI, "fpr14.hi" },
154 { PT_FPR14_LO, "fpr14.lo" },
155 { PT_FPR15_HI, "fpr15.hi" },
156 { PT_FPR15_LO, "fpr15.lo" },
Denys Vlasenko3e3490a2012-03-17 01:27:37 +0100157#endif
158#if defined(S390X)
Michal Ludvig10a88d02002-10-07 14:31:00 +0000159 { PT_FPR0, "fpr0" },
160 { PT_FPR1, "fpr1" },
161 { PT_FPR2, "fpr2" },
162 { PT_FPR3, "fpr3" },
163 { PT_FPR4, "fpr4" },
164 { PT_FPR5, "fpr5" },
165 { PT_FPR6, "fpr6" },
166 { PT_FPR7, "fpr7" },
167 { PT_FPR8, "fpr8" },
168 { PT_FPR9, "fpr9" },
169 { PT_FPR10, "fpr10" },
170 { PT_FPR11, "fpr11" },
171 { PT_FPR12, "fpr12" },
172 { PT_FPR13, "fpr13" },
173 { PT_FPR14, "fpr14" },
174 { PT_FPR15, "fpr15" },
Denys Vlasenko3e3490a2012-03-17 01:27:37 +0100175#endif
Wichert Akkerman4dc8a2a1999-12-23 14:20:14 +0000176 { PT_CR_9, "cr9" },
177 { PT_CR_10, "cr10" },
178 { PT_CR_11, "cr11" },
Denys Vlasenkob63256e2011-06-07 12:13:24 +0200179 { PT_IEEE_IP, "ieee_exception_ip" },
Denys Vlasenko3e3490a2012-03-17 01:27:37 +0100180#elif defined(SPARC)
Wichert Akkerman76baf7c1999-02-19 00:21:36 +0000181 /* XXX No support for these offsets yet. */
Denys Vlasenko3e3490a2012-03-17 01:27:37 +0100182#elif defined(HPPA)
Wichert Akkermanc1652e22001-03-27 12:17:16 +0000183 /* XXX No support for these offsets yet. */
Denys Vlasenko3e3490a2012-03-17 01:27:37 +0100184#elif defined(POWERPC)
185# ifndef PT_ORIG_R3
186# define PT_ORIG_R3 34
187# endif
188# define REGSIZE (sizeof(unsigned long))
Roland McGratheb285352003-01-14 09:59:00 +0000189 { REGSIZE*PT_R0, "r0" },
190 { REGSIZE*PT_R1, "r1" },
191 { REGSIZE*PT_R2, "r2" },
192 { REGSIZE*PT_R3, "r3" },
193 { REGSIZE*PT_R4, "r4" },
194 { REGSIZE*PT_R5, "r5" },
195 { REGSIZE*PT_R6, "r6" },
196 { REGSIZE*PT_R7, "r7" },
197 { REGSIZE*PT_R8, "r8" },
198 { REGSIZE*PT_R9, "r9" },
199 { REGSIZE*PT_R10, "r10" },
200 { REGSIZE*PT_R11, "r11" },
201 { REGSIZE*PT_R12, "r12" },
202 { REGSIZE*PT_R13, "r13" },
203 { REGSIZE*PT_R14, "r14" },
204 { REGSIZE*PT_R15, "r15" },
205 { REGSIZE*PT_R16, "r16" },
206 { REGSIZE*PT_R17, "r17" },
207 { REGSIZE*PT_R18, "r18" },
208 { REGSIZE*PT_R19, "r19" },
209 { REGSIZE*PT_R20, "r20" },
210 { REGSIZE*PT_R21, "r21" },
211 { REGSIZE*PT_R22, "r22" },
212 { REGSIZE*PT_R23, "r23" },
213 { REGSIZE*PT_R24, "r24" },
214 { REGSIZE*PT_R25, "r25" },
215 { REGSIZE*PT_R26, "r26" },
216 { REGSIZE*PT_R27, "r27" },
217 { REGSIZE*PT_R28, "r28" },
218 { REGSIZE*PT_R29, "r29" },
219 { REGSIZE*PT_R30, "r30" },
220 { REGSIZE*PT_R31, "r31" },
221 { REGSIZE*PT_NIP, "NIP" },
222 { REGSIZE*PT_MSR, "MSR" },
223 { REGSIZE*PT_ORIG_R3, "ORIG_R3" },
224 { REGSIZE*PT_CTR, "CTR" },
225 { REGSIZE*PT_LNK, "LNK" },
226 { REGSIZE*PT_XER, "XER" },
227 { REGSIZE*PT_CCR, "CCR" },
228 { REGSIZE*PT_FPR0, "FPR0" },
Denys Vlasenko3e3490a2012-03-17 01:27:37 +0100229# undef REGSIZE
230#elif defined(ALPHA)
Wichert Akkerman4dc8a2a1999-12-23 14:20:14 +0000231 { 0, "r0" },
232 { 1, "r1" },
233 { 2, "r2" },
234 { 3, "r3" },
235 { 4, "r4" },
236 { 5, "r5" },
237 { 6, "r6" },
238 { 7, "r7" },
239 { 8, "r8" },
240 { 9, "r9" },
241 { 10, "r10" },
242 { 11, "r11" },
243 { 12, "r12" },
244 { 13, "r13" },
245 { 14, "r14" },
246 { 15, "r15" },
247 { 16, "r16" },
248 { 17, "r17" },
249 { 18, "r18" },
250 { 19, "r19" },
251 { 20, "r20" },
252 { 21, "r21" },
253 { 22, "r22" },
254 { 23, "r23" },
255 { 24, "r24" },
256 { 25, "r25" },
257 { 26, "r26" },
258 { 27, "r27" },
259 { 28, "r28" },
260 { 29, "gp" },
261 { 30, "fp" },
262 { 31, "zero" },
263 { 32, "fp0" },
264 { 33, "fp" },
265 { 34, "fp2" },
266 { 35, "fp3" },
267 { 36, "fp4" },
268 { 37, "fp5" },
269 { 38, "fp6" },
270 { 39, "fp7" },
271 { 40, "fp8" },
272 { 41, "fp9" },
273 { 42, "fp10" },
274 { 43, "fp11" },
275 { 44, "fp12" },
276 { 45, "fp13" },
277 { 46, "fp14" },
278 { 47, "fp15" },
279 { 48, "fp16" },
280 { 49, "fp17" },
281 { 50, "fp18" },
282 { 51, "fp19" },
283 { 52, "fp20" },
284 { 53, "fp21" },
285 { 54, "fp22" },
286 { 55, "fp23" },
287 { 56, "fp24" },
288 { 57, "fp25" },
289 { 58, "fp26" },
290 { 59, "fp27" },
291 { 60, "fp28" },
292 { 61, "fp29" },
293 { 62, "fp30" },
294 { 63, "fp31" },
295 { 64, "pc" },
Denys Vlasenko3e3490a2012-03-17 01:27:37 +0100296#elif defined(IA64)
Wichert Akkerman8b1b40c2000-02-03 21:58:30 +0000297 { PT_F32, "f32" }, { PT_F33, "f33" }, { PT_F34, "f34" },
298 { PT_F35, "f35" }, { PT_F36, "f36" }, { PT_F37, "f37" },
299 { PT_F38, "f38" }, { PT_F39, "f39" }, { PT_F40, "f40" },
300 { PT_F41, "f41" }, { PT_F42, "f42" }, { PT_F43, "f43" },
301 { PT_F44, "f44" }, { PT_F45, "f45" }, { PT_F46, "f46" },
302 { PT_F47, "f47" }, { PT_F48, "f48" }, { PT_F49, "f49" },
303 { PT_F50, "f50" }, { PT_F51, "f51" }, { PT_F52, "f52" },
304 { PT_F53, "f53" }, { PT_F54, "f54" }, { PT_F55, "f55" },
305 { PT_F56, "f56" }, { PT_F57, "f57" }, { PT_F58, "f58" },
306 { PT_F59, "f59" }, { PT_F60, "f60" }, { PT_F61, "f61" },
307 { PT_F62, "f62" }, { PT_F63, "f63" }, { PT_F64, "f64" },
308 { PT_F65, "f65" }, { PT_F66, "f66" }, { PT_F67, "f67" },
309 { PT_F68, "f68" }, { PT_F69, "f69" }, { PT_F70, "f70" },
310 { PT_F71, "f71" }, { PT_F72, "f72" }, { PT_F73, "f73" },
311 { PT_F74, "f74" }, { PT_F75, "f75" }, { PT_F76, "f76" },
312 { PT_F77, "f77" }, { PT_F78, "f78" }, { PT_F79, "f79" },
313 { PT_F80, "f80" }, { PT_F81, "f81" }, { PT_F82, "f82" },
314 { PT_F83, "f83" }, { PT_F84, "f84" }, { PT_F85, "f85" },
315 { PT_F86, "f86" }, { PT_F87, "f87" }, { PT_F88, "f88" },
316 { PT_F89, "f89" }, { PT_F90, "f90" }, { PT_F91, "f91" },
317 { PT_F92, "f92" }, { PT_F93, "f93" }, { PT_F94, "f94" },
318 { PT_F95, "f95" }, { PT_F96, "f96" }, { PT_F97, "f97" },
319 { PT_F98, "f98" }, { PT_F99, "f99" }, { PT_F100, "f100" },
320 { PT_F101, "f101" }, { PT_F102, "f102" }, { PT_F103, "f103" },
321 { PT_F104, "f104" }, { PT_F105, "f105" }, { PT_F106, "f106" },
322 { PT_F107, "f107" }, { PT_F108, "f108" }, { PT_F109, "f109" },
323 { PT_F110, "f110" }, { PT_F111, "f111" }, { PT_F112, "f112" },
324 { PT_F113, "f113" }, { PT_F114, "f114" }, { PT_F115, "f115" },
325 { PT_F116, "f116" }, { PT_F117, "f117" }, { PT_F118, "f118" },
326 { PT_F119, "f119" }, { PT_F120, "f120" }, { PT_F121, "f121" },
327 { PT_F122, "f122" }, { PT_F123, "f123" }, { PT_F124, "f124" },
328 { PT_F125, "f125" }, { PT_F126, "f126" }, { PT_F127, "f127" },
329 /* switch stack: */
330 { PT_F2, "f2" }, { PT_F3, "f3" }, { PT_F4, "f4" },
331 { PT_F5, "f5" }, { PT_F10, "f10" }, { PT_F11, "f11" },
332 { PT_F12, "f12" }, { PT_F13, "f13" }, { PT_F14, "f14" },
333 { PT_F15, "f15" }, { PT_F16, "f16" }, { PT_F17, "f17" },
334 { PT_F18, "f18" }, { PT_F19, "f19" }, { PT_F20, "f20" },
335 { PT_F21, "f21" }, { PT_F22, "f22" }, { PT_F23, "f23" },
336 { PT_F24, "f24" }, { PT_F25, "f25" }, { PT_F26, "f26" },
337 { PT_F27, "f27" }, { PT_F28, "f28" }, { PT_F29, "f29" },
338 { PT_F30, "f30" }, { PT_F31, "f31" }, { PT_R4, "r4" },
339 { PT_R5, "r5" }, { PT_R6, "r6" }, { PT_R7, "r7" },
Wichert Akkerman8b1b40c2000-02-03 21:58:30 +0000340 { PT_B1, "b1" }, { PT_B2, "b2" }, { PT_B3, "b3" },
341 { PT_B4, "b4" }, { PT_B5, "b5" },
Roland McGrathca4e10c2004-01-13 10:13:20 +0000342 { PT_AR_EC, "ar.ec" }, { PT_AR_LC, "ar.lc" },
Wichert Akkerman8b1b40c2000-02-03 21:58:30 +0000343 /* pt_regs */
Roland McGrathca4e10c2004-01-13 10:13:20 +0000344 { PT_CR_IPSR, "psr" }, { PT_CR_IIP, "ip" },
345 { PT_CFM, "cfm" }, { PT_AR_UNAT, "ar.unat" },
Wichert Akkerman8b1b40c2000-02-03 21:58:30 +0000346 { PT_AR_PFS, "ar.pfs" }, { PT_AR_RSC, "ar.rsc" },
347 { PT_AR_RNAT, "ar.rnat" }, { PT_AR_BSPSTORE, "ar.bspstore" },
348 { PT_PR, "pr" }, { PT_B6, "b6" }, { PT_AR_BSP, "ar.bsp" },
349 { PT_R1, "r1" }, { PT_R2, "r2" }, { PT_R3, "r3" },
350 { PT_R12, "r12" }, { PT_R13, "r13" }, { PT_R14, "r14" },
351 { PT_R15, "r15" }, { PT_R8, "r8" }, { PT_R9, "r9" },
352 { PT_R10, "r10" }, { PT_R11, "r11" }, { PT_R16, "r16" },
353 { PT_R17, "r17" }, { PT_R18, "r18" }, { PT_R19, "r19" },
354 { PT_R20, "r20" }, { PT_R21, "r21" }, { PT_R22, "r22" },
355 { PT_R23, "r23" }, { PT_R24, "r24" }, { PT_R25, "r25" },
356 { PT_R26, "r26" }, { PT_R27, "r27" }, { PT_R28, "r28" },
357 { PT_R29, "r29" }, { PT_R30, "r30" }, { PT_R31, "r31" },
358 { PT_AR_CCV, "ar.ccv" }, { PT_AR_FPSR, "ar.fpsr" },
359 { PT_B0, "b0" }, { PT_B7, "b7" }, { PT_F6, "f6" },
360 { PT_F7, "f7" }, { PT_F8, "f8" }, { PT_F9, "f9" },
Denys Vlasenko3e3490a2012-03-17 01:27:37 +0100361# ifdef PT_AR_CSD
Roland McGrathfb1bc072004-03-01 21:29:24 +0000362 { PT_AR_CSD, "ar.csd" },
Denys Vlasenko3e3490a2012-03-17 01:27:37 +0100363# endif
364# ifdef PT_AR_SSD
Roland McGrathfb1bc072004-03-01 21:29:24 +0000365 { PT_AR_SSD, "ar.ssd" },
Denys Vlasenko3e3490a2012-03-17 01:27:37 +0100366# endif
Roland McGrathca4e10c2004-01-13 10:13:20 +0000367 { PT_DBR, "dbr" }, { PT_IBR, "ibr" }, { PT_PMD, "pmd" },
Denys Vlasenko3e3490a2012-03-17 01:27:37 +0100368#elif defined(I386)
Dmitry V. Levinbce0cc62014-02-05 01:33:50 +0000369 XLAT(4*EBX),
370 XLAT(4*ECX),
371 XLAT(4*EDX),
372 XLAT(4*ESI),
373 XLAT(4*EDI),
374 XLAT(4*EBP),
375 XLAT(4*EAX),
376 XLAT(4*DS),
377 XLAT(4*ES),
378 XLAT(4*FS),
379 XLAT(4*GS),
380 XLAT(4*ORIG_EAX),
381 XLAT(4*EIP),
382 XLAT(4*CS),
383 XLAT(4*EFL),
384 XLAT(4*UESP),
385 XLAT(4*SS),
H.J. Lu35be5812012-04-16 13:00:01 +0200386#elif defined(X86_64) || defined(X32)
Dmitry V. Levinbce0cc62014-02-05 01:33:50 +0000387 XLAT(8*R15),
388 XLAT(8*R14),
389 XLAT(8*R13),
390 XLAT(8*R12),
391 XLAT(8*RBP),
392 XLAT(8*RBX),
393 XLAT(8*R11),
394 XLAT(8*R10),
395 XLAT(8*R9),
396 XLAT(8*R8),
397 XLAT(8*RAX),
398 XLAT(8*RCX),
399 XLAT(8*RDX),
400 XLAT(8*RSI),
401 XLAT(8*RDI),
402 XLAT(8*ORIG_RAX),
403 XLAT(8*RIP),
404 XLAT(8*CS),
Michal Ludvig0e035502002-09-23 15:41:01 +0000405 { 8*EFLAGS, "8*EFL" },
Dmitry V. Levinbce0cc62014-02-05 01:33:50 +0000406 XLAT(8*RSP),
407 XLAT(8*SS),
Denys Vlasenko3e3490a2012-03-17 01:27:37 +0100408#elif defined(M68K)
Dmitry V. Levinbce0cc62014-02-05 01:33:50 +0000409 XLAT(4*PT_D1),
410 XLAT(4*PT_D2),
411 XLAT(4*PT_D3),
412 XLAT(4*PT_D4),
413 XLAT(4*PT_D5),
414 XLAT(4*PT_D6),
415 XLAT(4*PT_D7),
416 XLAT(4*PT_A0),
417 XLAT(4*PT_A1),
418 XLAT(4*PT_A2),
419 XLAT(4*PT_A3),
420 XLAT(4*PT_A4),
421 XLAT(4*PT_A5),
422 XLAT(4*PT_A6),
423 XLAT(4*PT_D0),
424 XLAT(4*PT_USP),
425 XLAT(4*PT_ORIG_D0),
426 XLAT(4*PT_SR),
427 XLAT(4*PT_PC),
Denys Vlasenko3e3490a2012-03-17 01:27:37 +0100428#elif defined(SH)
Dmitry V. Levinbce0cc62014-02-05 01:33:50 +0000429 XLAT(4*REG_REG0),
Denys Vlasenkob63256e2011-06-07 12:13:24 +0200430 { 4*(REG_REG0+1), "4*REG_REG1" },
431 { 4*(REG_REG0+2), "4*REG_REG2" },
432 { 4*(REG_REG0+3), "4*REG_REG3" },
433 { 4*(REG_REG0+4), "4*REG_REG4" },
434 { 4*(REG_REG0+5), "4*REG_REG5" },
435 { 4*(REG_REG0+6), "4*REG_REG6" },
436 { 4*(REG_REG0+7), "4*REG_REG7" },
437 { 4*(REG_REG0+8), "4*REG_REG8" },
438 { 4*(REG_REG0+9), "4*REG_REG9" },
439 { 4*(REG_REG0+10), "4*REG_REG10" },
440 { 4*(REG_REG0+11), "4*REG_REG11" },
441 { 4*(REG_REG0+12), "4*REG_REG12" },
442 { 4*(REG_REG0+13), "4*REG_REG13" },
443 { 4*(REG_REG0+14), "4*REG_REG14" },
Dmitry V. Levinbce0cc62014-02-05 01:33:50 +0000444 XLAT(4*REG_REG15),
445 XLAT(4*REG_PC),
446 XLAT(4*REG_PR),
447 XLAT(4*REG_SR),
448 XLAT(4*REG_GBR),
449 XLAT(4*REG_MACH),
450 XLAT(4*REG_MACL),
451 XLAT(4*REG_SYSCALL),
452 XLAT(4*REG_FPUL),
453 XLAT(4*REG_FPREG0),
Denys Vlasenkob63256e2011-06-07 12:13:24 +0200454 { 4*(REG_FPREG0+1), "4*REG_FPREG1" },
455 { 4*(REG_FPREG0+2), "4*REG_FPREG2" },
456 { 4*(REG_FPREG0+3), "4*REG_FPREG3" },
457 { 4*(REG_FPREG0+4), "4*REG_FPREG4" },
458 { 4*(REG_FPREG0+5), "4*REG_FPREG5" },
459 { 4*(REG_FPREG0+6), "4*REG_FPREG6" },
460 { 4*(REG_FPREG0+7), "4*REG_FPREG7" },
461 { 4*(REG_FPREG0+8), "4*REG_FPREG8" },
462 { 4*(REG_FPREG0+9), "4*REG_FPREG9" },
463 { 4*(REG_FPREG0+10), "4*REG_FPREG10" },
464 { 4*(REG_FPREG0+11), "4*REG_FPREG11" },
465 { 4*(REG_FPREG0+12), "4*REG_FPREG12" },
466 { 4*(REG_FPREG0+13), "4*REG_FPREG13" },
467 { 4*(REG_FPREG0+14), "4*REG_FPREG14" },
Dmitry V. Levinbce0cc62014-02-05 01:33:50 +0000468 XLAT(4*REG_FPREG15),
Denys Vlasenko3e3490a2012-03-17 01:27:37 +0100469# ifdef REG_XDREG0
Dmitry V. Levinbce0cc62014-02-05 01:33:50 +0000470 XLAT(4*REG_XDREG0),
Denys Vlasenkob63256e2011-06-07 12:13:24 +0200471 { 4*(REG_XDREG0+2), "4*REG_XDREG2" },
472 { 4*(REG_XDREG0+4), "4*REG_XDREG4" },
473 { 4*(REG_XDREG0+6), "4*REG_XDREG6" },
474 { 4*(REG_XDREG0+8), "4*REG_XDREG8" },
475 { 4*(REG_XDREG0+10), "4*REG_XDREG10" },
476 { 4*(REG_XDREG0+12), "4*REG_XDREG12" },
Dmitry V. Levinbce0cc62014-02-05 01:33:50 +0000477 XLAT(4*REG_XDREG14),
Denys Vlasenko3e3490a2012-03-17 01:27:37 +0100478# endif
Dmitry V. Levinbce0cc62014-02-05 01:33:50 +0000479 XLAT(4*REG_FPSCR),
Denys Vlasenko3e3490a2012-03-17 01:27:37 +0100480#elif defined(SH64)
Denys Vlasenkob63256e2011-06-07 12:13:24 +0200481 { 0, "PC(L)" },
482 { 4, "PC(U)" },
483 { 8, "SR(L)" },
484 { 12, "SR(U)" },
485 { 16, "syscall no.(L)" },
486 { 20, "syscall_no.(U)" },
487 { 24, "R0(L)" },
488 { 28, "R0(U)" },
489 { 32, "R1(L)" },
490 { 36, "R1(U)" },
491 { 40, "R2(L)" },
492 { 44, "R2(U)" },
493 { 48, "R3(L)" },
494 { 52, "R3(U)" },
495 { 56, "R4(L)" },
496 { 60, "R4(U)" },
497 { 64, "R5(L)" },
498 { 68, "R5(U)" },
499 { 72, "R6(L)" },
500 { 76, "R6(U)" },
501 { 80, "R7(L)" },
502 { 84, "R7(U)" },
503 { 88, "R8(L)" },
504 { 92, "R8(U)" },
505 { 96, "R9(L)" },
506 { 100, "R9(U)" },
507 { 104, "R10(L)" },
508 { 108, "R10(U)" },
509 { 112, "R11(L)" },
510 { 116, "R11(U)" },
511 { 120, "R12(L)" },
512 { 124, "R12(U)" },
513 { 128, "R13(L)" },
514 { 132, "R13(U)" },
515 { 136, "R14(L)" },
516 { 140, "R14(U)" },
517 { 144, "R15(L)" },
518 { 148, "R15(U)" },
519 { 152, "R16(L)" },
520 { 156, "R16(U)" },
521 { 160, "R17(L)" },
522 { 164, "R17(U)" },
523 { 168, "R18(L)" },
524 { 172, "R18(U)" },
525 { 176, "R19(L)" },
526 { 180, "R19(U)" },
527 { 184, "R20(L)" },
528 { 188, "R20(U)" },
529 { 192, "R21(L)" },
530 { 196, "R21(U)" },
531 { 200, "R22(L)" },
532 { 204, "R22(U)" },
533 { 208, "R23(L)" },
534 { 212, "R23(U)" },
535 { 216, "R24(L)" },
536 { 220, "R24(U)" },
537 { 224, "R25(L)" },
538 { 228, "R25(U)" },
539 { 232, "R26(L)" },
540 { 236, "R26(U)" },
541 { 240, "R27(L)" },
542 { 244, "R27(U)" },
543 { 248, "R28(L)" },
544 { 252, "R28(U)" },
545 { 256, "R29(L)" },
546 { 260, "R29(U)" },
547 { 264, "R30(L)" },
548 { 268, "R30(U)" },
549 { 272, "R31(L)" },
550 { 276, "R31(U)" },
551 { 280, "R32(L)" },
552 { 284, "R32(U)" },
553 { 288, "R33(L)" },
554 { 292, "R33(U)" },
555 { 296, "R34(L)" },
556 { 300, "R34(U)" },
557 { 304, "R35(L)" },
558 { 308, "R35(U)" },
559 { 312, "R36(L)" },
560 { 316, "R36(U)" },
561 { 320, "R37(L)" },
562 { 324, "R37(U)" },
563 { 328, "R38(L)" },
564 { 332, "R38(U)" },
565 { 336, "R39(L)" },
566 { 340, "R39(U)" },
567 { 344, "R40(L)" },
568 { 348, "R40(U)" },
569 { 352, "R41(L)" },
570 { 356, "R41(U)" },
571 { 360, "R42(L)" },
572 { 364, "R42(U)" },
573 { 368, "R43(L)" },
574 { 372, "R43(U)" },
575 { 376, "R44(L)" },
576 { 380, "R44(U)" },
577 { 384, "R45(L)" },
578 { 388, "R45(U)" },
579 { 392, "R46(L)" },
580 { 396, "R46(U)" },
581 { 400, "R47(L)" },
582 { 404, "R47(U)" },
583 { 408, "R48(L)" },
584 { 412, "R48(U)" },
585 { 416, "R49(L)" },
586 { 420, "R49(U)" },
587 { 424, "R50(L)" },
588 { 428, "R50(U)" },
589 { 432, "R51(L)" },
590 { 436, "R51(U)" },
591 { 440, "R52(L)" },
592 { 444, "R52(U)" },
593 { 448, "R53(L)" },
594 { 452, "R53(U)" },
595 { 456, "R54(L)" },
596 { 460, "R54(U)" },
597 { 464, "R55(L)" },
598 { 468, "R55(U)" },
599 { 472, "R56(L)" },
600 { 476, "R56(U)" },
601 { 480, "R57(L)" },
602 { 484, "R57(U)" },
603 { 488, "R58(L)" },
604 { 492, "R58(U)" },
605 { 496, "R59(L)" },
606 { 500, "R59(U)" },
607 { 504, "R60(L)" },
608 { 508, "R60(U)" },
609 { 512, "R61(L)" },
610 { 516, "R61(U)" },
611 { 520, "R62(L)" },
612 { 524, "R62(U)" },
613 { 528, "TR0(L)" },
614 { 532, "TR0(U)" },
615 { 536, "TR1(L)" },
616 { 540, "TR1(U)" },
617 { 544, "TR2(L)" },
618 { 548, "TR2(U)" },
619 { 552, "TR3(L)" },
620 { 556, "TR3(U)" },
621 { 560, "TR4(L)" },
622 { 564, "TR4(U)" },
623 { 568, "TR5(L)" },
624 { 572, "TR5(U)" },
625 { 576, "TR6(L)" },
626 { 580, "TR6(U)" },
627 { 584, "TR7(L)" },
628 { 588, "TR7(U)" },
Denys Vlasenkoadedb512008-12-30 18:47:55 +0000629 /* This entry is in case pt_regs contains dregs (depends on
630 the kernel build options). */
Dmitry V. Levinc6ce4fd2014-12-11 19:25:02 +0000631 XLAT_UOFF(regs),
632 XLAT_UOFF(fpu),
Denys Vlasenko3e3490a2012-03-17 01:27:37 +0100633#elif defined(ARM)
Roland McGrath0f87c492003-06-03 23:29:04 +0000634 { uoff(regs.ARM_r0), "r0" },
635 { uoff(regs.ARM_r1), "r1" },
636 { uoff(regs.ARM_r2), "r2" },
637 { uoff(regs.ARM_r3), "r3" },
638 { uoff(regs.ARM_r4), "r4" },
639 { uoff(regs.ARM_r5), "r5" },
640 { uoff(regs.ARM_r6), "r6" },
641 { uoff(regs.ARM_r7), "r7" },
642 { uoff(regs.ARM_r8), "r8" },
643 { uoff(regs.ARM_r9), "r9" },
644 { uoff(regs.ARM_r10), "r10" },
645 { uoff(regs.ARM_fp), "fp" },
646 { uoff(regs.ARM_ip), "ip" },
647 { uoff(regs.ARM_sp), "sp" },
648 { uoff(regs.ARM_lr), "lr" },
649 { uoff(regs.ARM_pc), "pc" },
650 { uoff(regs.ARM_cpsr), "cpsr" },
Denys Vlasenko3e3490a2012-03-17 01:27:37 +0100651#elif defined(AVR32)
Denys Vlasenko5ae2b7c2009-02-27 20:32:52 +0000652 { uoff(regs.sr), "sr" },
653 { uoff(regs.pc), "pc" },
654 { uoff(regs.lr), "lr" },
655 { uoff(regs.sp), "sp" },
656 { uoff(regs.r12), "r12" },
657 { uoff(regs.r11), "r11" },
658 { uoff(regs.r10), "r10" },
659 { uoff(regs.r9), "r9" },
660 { uoff(regs.r8), "r8" },
661 { uoff(regs.r7), "r7" },
662 { uoff(regs.r6), "r6" },
663 { uoff(regs.r5), "r5" },
664 { uoff(regs.r4), "r4" },
665 { uoff(regs.r3), "r3" },
666 { uoff(regs.r2), "r2" },
667 { uoff(regs.r1), "r1" },
668 { uoff(regs.r0), "r0" },
669 { uoff(regs.r12_orig), "orig_r12" },
Denys Vlasenko3e3490a2012-03-17 01:27:37 +0100670#elif defined(MIPS)
Roland McGrath542c2c62008-05-20 01:11:56 +0000671 { 0, "r0" },
672 { 1, "r1" },
673 { 2, "r2" },
674 { 3, "r3" },
675 { 4, "r4" },
676 { 5, "r5" },
677 { 6, "r6" },
678 { 7, "r7" },
679 { 8, "r8" },
680 { 9, "r9" },
681 { 10, "r10" },
682 { 11, "r11" },
683 { 12, "r12" },
684 { 13, "r13" },
685 { 14, "r14" },
686 { 15, "r15" },
687 { 16, "r16" },
688 { 17, "r17" },
689 { 18, "r18" },
690 { 19, "r19" },
691 { 20, "r20" },
692 { 21, "r21" },
693 { 22, "r22" },
694 { 23, "r23" },
695 { 24, "r24" },
696 { 25, "r25" },
697 { 26, "r26" },
698 { 27, "r27" },
699 { 28, "r28" },
700 { 29, "r29" },
701 { 30, "r30" },
702 { 31, "r31" },
703 { 32, "f0" },
704 { 33, "f1" },
705 { 34, "f2" },
706 { 35, "f3" },
707 { 36, "f4" },
708 { 37, "f5" },
709 { 38, "f6" },
710 { 39, "f7" },
711 { 40, "f8" },
712 { 41, "f9" },
713 { 42, "f10" },
714 { 43, "f11" },
715 { 44, "f12" },
716 { 45, "f13" },
717 { 46, "f14" },
718 { 47, "f15" },
719 { 48, "f16" },
720 { 49, "f17" },
721 { 50, "f18" },
722 { 51, "f19" },
723 { 52, "f20" },
724 { 53, "f21" },
725 { 54, "f22" },
726 { 55, "f23" },
727 { 56, "f24" },
728 { 57, "f25" },
729 { 58, "f26" },
730 { 59, "f27" },
731 { 60, "f28" },
732 { 61, "f29" },
733 { 62, "f30" },
734 { 63, "f31" },
735 { 64, "pc" },
736 { 65, "cause" },
737 { 66, "badvaddr" },
738 { 67, "mmhi" },
739 { 68, "mmlo" },
740 { 69, "fpcsr" },
741 { 70, "fpeir" },
Denys Vlasenko3e3490a2012-03-17 01:27:37 +0100742#elif defined(TILE)
Chris Metcalfc8c66982009-12-28 10:00:15 -0500743 { PTREGS_OFFSET_REG(0), "r0" },
744 { PTREGS_OFFSET_REG(1), "r1" },
745 { PTREGS_OFFSET_REG(2), "r2" },
746 { PTREGS_OFFSET_REG(3), "r3" },
747 { PTREGS_OFFSET_REG(4), "r4" },
748 { PTREGS_OFFSET_REG(5), "r5" },
749 { PTREGS_OFFSET_REG(6), "r6" },
750 { PTREGS_OFFSET_REG(7), "r7" },
751 { PTREGS_OFFSET_REG(8), "r8" },
752 { PTREGS_OFFSET_REG(9), "r9" },
753 { PTREGS_OFFSET_REG(10), "r10" },
754 { PTREGS_OFFSET_REG(11), "r11" },
755 { PTREGS_OFFSET_REG(12), "r12" },
756 { PTREGS_OFFSET_REG(13), "r13" },
757 { PTREGS_OFFSET_REG(14), "r14" },
758 { PTREGS_OFFSET_REG(15), "r15" },
759 { PTREGS_OFFSET_REG(16), "r16" },
760 { PTREGS_OFFSET_REG(17), "r17" },
761 { PTREGS_OFFSET_REG(18), "r18" },
762 { PTREGS_OFFSET_REG(19), "r19" },
763 { PTREGS_OFFSET_REG(20), "r20" },
764 { PTREGS_OFFSET_REG(21), "r21" },
765 { PTREGS_OFFSET_REG(22), "r22" },
766 { PTREGS_OFFSET_REG(23), "r23" },
767 { PTREGS_OFFSET_REG(24), "r24" },
768 { PTREGS_OFFSET_REG(25), "r25" },
769 { PTREGS_OFFSET_REG(26), "r26" },
770 { PTREGS_OFFSET_REG(27), "r27" },
771 { PTREGS_OFFSET_REG(28), "r28" },
772 { PTREGS_OFFSET_REG(29), "r29" },
773 { PTREGS_OFFSET_REG(30), "r30" },
774 { PTREGS_OFFSET_REG(31), "r31" },
775 { PTREGS_OFFSET_REG(32), "r32" },
776 { PTREGS_OFFSET_REG(33), "r33" },
777 { PTREGS_OFFSET_REG(34), "r34" },
778 { PTREGS_OFFSET_REG(35), "r35" },
779 { PTREGS_OFFSET_REG(36), "r36" },
780 { PTREGS_OFFSET_REG(37), "r37" },
781 { PTREGS_OFFSET_REG(38), "r38" },
782 { PTREGS_OFFSET_REG(39), "r39" },
783 { PTREGS_OFFSET_REG(40), "r40" },
784 { PTREGS_OFFSET_REG(41), "r41" },
785 { PTREGS_OFFSET_REG(42), "r42" },
786 { PTREGS_OFFSET_REG(43), "r43" },
787 { PTREGS_OFFSET_REG(44), "r44" },
788 { PTREGS_OFFSET_REG(45), "r45" },
789 { PTREGS_OFFSET_REG(46), "r46" },
790 { PTREGS_OFFSET_REG(47), "r47" },
791 { PTREGS_OFFSET_REG(48), "r48" },
792 { PTREGS_OFFSET_REG(49), "r49" },
793 { PTREGS_OFFSET_REG(50), "r50" },
794 { PTREGS_OFFSET_REG(51), "r51" },
795 { PTREGS_OFFSET_REG(52), "r52" },
796 { PTREGS_OFFSET_TP, "tp" },
797 { PTREGS_OFFSET_SP, "sp" },
798 { PTREGS_OFFSET_LR, "lr" },
799 { PTREGS_OFFSET_PC, "pc" },
800 { PTREGS_OFFSET_EX1, "ex1" },
801 { PTREGS_OFFSET_FAULTNUM, "faultnum" },
802 { PTREGS_OFFSET_ORIG_R0, "orig_r0" },
803 { PTREGS_OFFSET_FLAGS, "flags" },
Denys Vlasenko3e3490a2012-03-17 01:27:37 +0100804#endif
805#ifdef CRISV10
Dmitry V. Levinbce0cc62014-02-05 01:33:50 +0000806 XLAT(4*PT_FRAMETYPE),
807 XLAT(4*PT_ORIG_R10),
808 XLAT(4*PT_R13),
809 XLAT(4*PT_R12),
810 XLAT(4*PT_R11),
811 XLAT(4*PT_R10),
812 XLAT(4*PT_R9),
813 XLAT(4*PT_R8),
814 XLAT(4*PT_R7),
815 XLAT(4*PT_R6),
816 XLAT(4*PT_R5),
817 XLAT(4*PT_R4),
818 XLAT(4*PT_R3),
819 XLAT(4*PT_R2),
820 XLAT(4*PT_R1),
821 XLAT(4*PT_R0),
822 XLAT(4*PT_MOF),
823 XLAT(4*PT_DCCR),
824 XLAT(4*PT_SRP),
825 XLAT(4*PT_IRP),
826 XLAT(4*PT_CSRINSTR),
827 XLAT(4*PT_CSRADDR),
828 XLAT(4*PT_CSRDATA),
829 XLAT(4*PT_USP),
Denys Vlasenko3e3490a2012-03-17 01:27:37 +0100830#endif
831#ifdef CRISV32
Dmitry V. Levinbce0cc62014-02-05 01:33:50 +0000832 XLAT(4*PT_ORIG_R10),
833 XLAT(4*PT_R0),
834 XLAT(4*PT_R1),
835 XLAT(4*PT_R2),
836 XLAT(4*PT_R3),
837 XLAT(4*PT_R4),
838 XLAT(4*PT_R5),
839 XLAT(4*PT_R6),
840 XLAT(4*PT_R7),
841 XLAT(4*PT_R8),
842 XLAT(4*PT_R9),
843 XLAT(4*PT_R10),
844 XLAT(4*PT_R11),
845 XLAT(4*PT_R12),
846 XLAT(4*PT_R13),
847 XLAT(4*PT_ACR),
848 XLAT(4*PT_SRS),
849 XLAT(4*PT_MOF),
850 XLAT(4*PT_SPC),
851 XLAT(4*PT_CCS),
852 XLAT(4*PT_SRP),
853 XLAT(4*PT_ERP),
854 XLAT(4*PT_EXS),
855 XLAT(4*PT_EDA),
856 XLAT(4*PT_USP),
857 XLAT(4*PT_PPC),
858 XLAT(4*PT_BP_CTRL),
859 XLAT(4*PT_BP+4),
860 XLAT(4*PT_BP+8),
861 XLAT(4*PT_BP+12),
862 XLAT(4*PT_BP+16),
863 XLAT(4*PT_BP+20),
864 XLAT(4*PT_BP+24),
865 XLAT(4*PT_BP+28),
866 XLAT(4*PT_BP+32),
867 XLAT(4*PT_BP+36),
868 XLAT(4*PT_BP+40),
869 XLAT(4*PT_BP+44),
870 XLAT(4*PT_BP+48),
871 XLAT(4*PT_BP+52),
872 XLAT(4*PT_BP+56),
Denys Vlasenko3e3490a2012-03-17 01:27:37 +0100873#endif
874#ifdef MICROBLAZE
Edgar E. Iglesias939caba2010-07-06 14:21:07 +0200875 { PT_GPR(0), "r0" },
876 { PT_GPR(1), "r1" },
877 { PT_GPR(2), "r2" },
878 { PT_GPR(3), "r3" },
879 { PT_GPR(4), "r4" },
880 { PT_GPR(5), "r5" },
881 { PT_GPR(6), "r6" },
882 { PT_GPR(7), "r7" },
883 { PT_GPR(8), "r8" },
884 { PT_GPR(9), "r9" },
885 { PT_GPR(10), "r10" },
886 { PT_GPR(11), "r11" },
887 { PT_GPR(12), "r12" },
888 { PT_GPR(13), "r13" },
889 { PT_GPR(14), "r14" },
890 { PT_GPR(15), "r15" },
891 { PT_GPR(16), "r16" },
892 { PT_GPR(17), "r17" },
893 { PT_GPR(18), "r18" },
894 { PT_GPR(19), "r19" },
895 { PT_GPR(20), "r20" },
896 { PT_GPR(21), "r21" },
897 { PT_GPR(22), "r22" },
898 { PT_GPR(23), "r23" },
899 { PT_GPR(24), "r24" },
900 { PT_GPR(25), "r25" },
901 { PT_GPR(26), "r26" },
902 { PT_GPR(27), "r27" },
903 { PT_GPR(28), "r28" },
904 { PT_GPR(29), "r29" },
905 { PT_GPR(30), "r30" },
906 { PT_GPR(31), "r31" },
Denys Vlasenkob63256e2011-06-07 12:13:24 +0200907 { PT_PC, "rpc", },
908 { PT_MSR, "rmsr", },
Edgar E. Iglesias939caba2010-07-06 14:21:07 +0200909 { PT_EAR, "rear", },
910 { PT_ESR, "resr", },
911 { PT_FSR, "rfsr", },
Denys Vlasenkob63256e2011-06-07 12:13:24 +0200912 { PT_KERNEL_MODE, "kernel_mode", },
Denys Vlasenko3e3490a2012-03-17 01:27:37 +0100913#endif
Christian Svensson492f81f2013-02-14 13:26:27 +0100914#ifdef OR1K
915 { 4*0, "r0" },
916 { 4*1, "r1" },
917 { 4*2, "r2" },
918 { 4*3, "r3" },
919 { 4*4, "r4" },
920 { 4*5, "r5" },
921 { 4*6, "r6" },
922 { 4*7, "r7" },
923 { 4*8, "r8" },
924 { 4*9, "r9" },
925 { 4*10, "r10" },
926 { 4*11, "r11" },
927 { 4*12, "r12" },
928 { 4*13, "r13" },
929 { 4*14, "r14" },
930 { 4*15, "r15" },
931 { 4*16, "r16" },
932 { 4*17, "r17" },
933 { 4*18, "r18" },
934 { 4*19, "r19" },
935 { 4*20, "r20" },
936 { 4*21, "r21" },
937 { 4*22, "r22" },
938 { 4*23, "r23" },
939 { 4*24, "r24" },
940 { 4*25, "r25" },
941 { 4*26, "r26" },
942 { 4*27, "r27" },
943 { 4*28, "r28" },
944 { 4*29, "r29" },
945 { 4*30, "r30" },
946 { 4*31, "r31" },
947 { 4*32, "pc" },
948 { 4*33, "sr" },
949#endif
Chris Zankel8f636ed2013-03-25 10:22:07 -0700950#ifdef XTENSA
Max Filippov57fac752014-06-18 06:04:06 +0400951 { REG_A_BASE, "a0" },
952 { REG_A_BASE+1, "a1" },
953 { REG_A_BASE+2, "a2" },
954 { REG_A_BASE+3, "a3" },
955 { REG_A_BASE+4, "a4" },
956 { REG_A_BASE+5, "a5" },
957 { REG_A_BASE+6, "a6" },
958 { REG_A_BASE+7, "a7" },
959 { REG_A_BASE+8, "a8" },
960 { REG_A_BASE+9, "a9" },
961 { REG_A_BASE+10, "a10" },
962 { REG_A_BASE+11, "a11" },
963 { REG_A_BASE+12, "a12" },
964 { REG_A_BASE+13, "a13" },
965 { REG_A_BASE+14, "a14" },
966 { REG_A_BASE+15, "a15" },
967 { REG_PC, "pc" },
Chris Zankel8f636ed2013-03-25 10:22:07 -0700968 { SYSCALL_NR, "syscall_nr" },
969 { REG_AR_BASE, "ar0" },
970 { REG_AR_BASE+1, "ar1" },
971 { REG_AR_BASE+2, "ar2" },
972 { REG_AR_BASE+3, "ar3" },
973 { REG_AR_BASE+4, "ar4" },
974 { REG_AR_BASE+5, "ar5" },
975 { REG_AR_BASE+6, "ar6" },
976 { REG_AR_BASE+7, "ar7" },
977 { REG_AR_BASE+8, "ar8" },
978 { REG_AR_BASE+9, "ar9" },
979 { REG_AR_BASE+10, "ar10" },
980 { REG_AR_BASE+11, "ar11" },
981 { REG_AR_BASE+12, "ar12" },
982 { REG_AR_BASE+13, "ar13" },
983 { REG_AR_BASE+14, "ar14" },
984 { REG_AR_BASE+15, "ar15" },
985 { REG_AR_BASE+16, "ar16" },
986 { REG_AR_BASE+17, "ar17" },
987 { REG_AR_BASE+18, "ar18" },
988 { REG_AR_BASE+19, "ar19" },
989 { REG_AR_BASE+20, "ar20" },
990 { REG_AR_BASE+21, "ar21" },
991 { REG_AR_BASE+22, "ar22" },
992 { REG_AR_BASE+23, "ar23" },
993 { REG_AR_BASE+24, "ar24" },
994 { REG_AR_BASE+25, "ar25" },
995 { REG_AR_BASE+26, "ar26" },
996 { REG_AR_BASE+27, "ar27" },
997 { REG_AR_BASE+28, "ar28" },
998 { REG_AR_BASE+29, "ar29" },
999 { REG_AR_BASE+30, "ar30" },
1000 { REG_AR_BASE+31, "ar31" },
1001 { REG_AR_BASE+32, "ar32" },
1002 { REG_AR_BASE+33, "ar33" },
1003 { REG_AR_BASE+34, "ar34" },
1004 { REG_AR_BASE+35, "ar35" },
1005 { REG_AR_BASE+36, "ar36" },
1006 { REG_AR_BASE+37, "ar37" },
1007 { REG_AR_BASE+38, "ar38" },
1008 { REG_AR_BASE+39, "ar39" },
1009 { REG_AR_BASE+40, "ar40" },
1010 { REG_AR_BASE+41, "ar41" },
1011 { REG_AR_BASE+42, "ar42" },
1012 { REG_AR_BASE+43, "ar43" },
1013 { REG_AR_BASE+44, "ar44" },
1014 { REG_AR_BASE+45, "ar45" },
1015 { REG_AR_BASE+46, "ar46" },
1016 { REG_AR_BASE+47, "ar47" },
1017 { REG_AR_BASE+48, "ar48" },
1018 { REG_AR_BASE+49, "ar49" },
1019 { REG_AR_BASE+50, "ar50" },
1020 { REG_AR_BASE+51, "ar51" },
1021 { REG_AR_BASE+52, "ar52" },
1022 { REG_AR_BASE+53, "ar53" },
1023 { REG_AR_BASE+54, "ar54" },
1024 { REG_AR_BASE+55, "ar55" },
1025 { REG_AR_BASE+56, "ar56" },
1026 { REG_AR_BASE+57, "ar57" },
1027 { REG_AR_BASE+58, "ar58" },
1028 { REG_AR_BASE+59, "ar59" },
1029 { REG_AR_BASE+60, "ar60" },
1030 { REG_AR_BASE+61, "ar61" },
1031 { REG_AR_BASE+62, "ar62" },
1032 { REG_AR_BASE+63, "ar63" },
1033 { REG_LBEG, "lbeg" },
1034 { REG_LEND, "lend" },
1035 { REG_LCOUNT, "lcount" },
1036 { REG_SAR, "sar" },
1037 { REG_WB, "wb" },
1038 { REG_WS, "ws" },
1039 { REG_PS, "ps" },
Chris Zankel8f636ed2013-03-25 10:22:07 -07001040#endif
1041
Denys Vlasenko729e18d2013-02-12 15:51:58 +01001042 /* Other fields in "struct user" */
1043#if defined(S390) || defined(S390X)
Dmitry V. Levinc6ce4fd2014-12-11 19:25:02 +00001044 XLAT_UOFF(u_tsize),
1045 XLAT_UOFF(u_dsize),
1046 XLAT_UOFF(u_ssize),
1047 XLAT_UOFF(start_code),
Denys Vlasenko74307a62013-02-12 17:10:05 +01001048 /* S390[X] has no start_data */
Dmitry V. Levinc6ce4fd2014-12-11 19:25:02 +00001049 XLAT_UOFF(start_stack),
1050 XLAT_UOFF(signal),
1051 XLAT_UOFF(u_ar0),
1052 XLAT_UOFF(magic),
1053 XLAT_UOFF(u_comm),
Denys Vlasenko729e18d2013-02-12 15:51:58 +01001054 { sizeof(struct user), "sizeof(struct user)" },
1055#elif defined(POWERPC)
1056 { sizeof(struct user), "sizeof(struct user)" },
1057#elif defined(I386) || defined(X86_64) || defined(X32)
Dmitry V. Levinc6ce4fd2014-12-11 19:25:02 +00001058 XLAT_UOFF(u_fpvalid),
1059 XLAT_UOFF(i387),
1060 XLAT_UOFF(u_tsize),
1061 XLAT_UOFF(u_dsize),
1062 XLAT_UOFF(u_ssize),
1063 XLAT_UOFF(start_code),
1064 XLAT_UOFF(start_stack),
1065 XLAT_UOFF(signal),
1066 XLAT_UOFF(reserved),
1067 XLAT_UOFF(u_ar0),
1068 XLAT_UOFF(u_fpstate),
1069 XLAT_UOFF(magic),
1070 XLAT_UOFF(u_comm),
1071 XLAT_UOFF(u_debugreg),
Denys Vlasenko729e18d2013-02-12 15:51:58 +01001072 { sizeof(struct user), "sizeof(struct user)" },
1073#elif defined(IA64)
1074 { sizeof(struct user), "sizeof(struct user)" },
1075#elif defined(ARM)
Dmitry V. Levinc6ce4fd2014-12-11 19:25:02 +00001076 XLAT_UOFF(u_fpvalid),
1077 XLAT_UOFF(u_tsize),
1078 XLAT_UOFF(u_dsize),
1079 XLAT_UOFF(u_ssize),
1080 XLAT_UOFF(start_code),
1081 XLAT_UOFF(start_stack),
1082 XLAT_UOFF(signal),
1083 XLAT_UOFF(reserved),
1084 XLAT_UOFF(u_ar0),
1085 XLAT_UOFF(magic),
1086 XLAT_UOFF(u_comm),
Denys Vlasenko729e18d2013-02-12 15:51:58 +01001087 { sizeof(struct user), "sizeof(struct user)" },
1088#elif defined(AARCH64)
1089 /* nothing */
1090#elif defined(M68K)
Dmitry V. Levinc6ce4fd2014-12-11 19:25:02 +00001091 XLAT_UOFF(u_fpvalid),
1092 XLAT_UOFF(m68kfp),
1093 XLAT_UOFF(u_tsize),
1094 XLAT_UOFF(u_dsize),
1095 XLAT_UOFF(u_ssize),
1096 XLAT_UOFF(start_code),
1097 XLAT_UOFF(start_stack),
1098 XLAT_UOFF(signal),
1099 XLAT_UOFF(reserved),
1100 XLAT_UOFF(u_ar0),
1101 XLAT_UOFF(u_fpstate),
1102 XLAT_UOFF(magic),
1103 XLAT_UOFF(u_comm),
Denys Vlasenko729e18d2013-02-12 15:51:58 +01001104 { sizeof(struct user), "sizeof(struct user)" },
Denys Vlasenko873e5a52013-02-12 17:15:19 +01001105#elif defined(MIPS) || defined(LINUX_MIPSN32)
Dmitry V. Levinc6ce4fd2014-12-11 19:25:02 +00001106 XLAT_UOFF(u_tsize),
1107 XLAT_UOFF(u_dsize),
1108 XLAT_UOFF(u_ssize),
1109 XLAT_UOFF(start_code),
1110 XLAT_UOFF(start_data),
1111 XLAT_UOFF(start_stack),
1112 XLAT_UOFF(signal),
1113 XLAT_UOFF(u_ar0),
1114 XLAT_UOFF(magic),
1115 XLAT_UOFF(u_comm),
Denys Vlasenko729e18d2013-02-12 15:51:58 +01001116 { sizeof(struct user), "sizeof(struct user)" },
1117#elif defined(ALPHA)
1118 { sizeof(struct user), "sizeof(struct user)" },
1119#elif defined(SPARC)
1120 { sizeof(struct user), "sizeof(struct user)" },
1121#elif defined(SPARC64)
Dmitry V. Levinc6ce4fd2014-12-11 19:25:02 +00001122 XLAT_UOFF(u_tsize),
1123 XLAT_UOFF(u_dsize),
1124 XLAT_UOFF(u_ssize),
1125 XLAT_UOFF(signal),
1126 XLAT_UOFF(magic),
1127 XLAT_UOFF(u_comm),
Denys Vlasenko729e18d2013-02-12 15:51:58 +01001128 { sizeof(struct user), "sizeof(struct user)" },
1129#elif defined(HPPA)
1130 /* nothing */
Denys Vlasenko873e5a52013-02-12 17:15:19 +01001131#elif defined(SH) || defined(SH64)
Dmitry V. Levinc6ce4fd2014-12-11 19:25:02 +00001132 XLAT_UOFF(u_fpvalid),
1133 XLAT_UOFF(u_tsize),
1134 XLAT_UOFF(u_dsize),
1135 XLAT_UOFF(u_ssize),
1136 XLAT_UOFF(start_code),
1137 XLAT_UOFF(start_data),
1138 XLAT_UOFF(start_stack),
1139 XLAT_UOFF(signal),
1140 XLAT_UOFF(u_ar0),
1141 XLAT_UOFF(u_fpstate),
1142 XLAT_UOFF(magic),
1143 XLAT_UOFF(u_comm),
Denys Vlasenko729e18d2013-02-12 15:51:58 +01001144 { sizeof(struct user), "sizeof(struct user)" },
1145#elif defined(CRISV10) || defined(CRISV32)
1146 { sizeof(struct user), "sizeof(struct user)" },
1147#elif defined(TILE)
1148 /* nothing */
1149#elif defined(MICROBLAZE)
1150 { sizeof(struct user), "sizeof(struct user)" },
1151#elif defined(AVR32)
Dmitry V. Levinc6ce4fd2014-12-11 19:25:02 +00001152 XLAT_UOFF(u_tsize),
1153 XLAT_UOFF(u_dsize),
1154 XLAT_UOFF(u_ssize),
1155 XLAT_UOFF(start_code),
1156 XLAT_UOFF(start_data),
1157 XLAT_UOFF(start_stack),
1158 XLAT_UOFF(signal),
1159 XLAT_UOFF(u_ar0),
1160 XLAT_UOFF(magic),
1161 XLAT_UOFF(u_comm),
Denys Vlasenko729e18d2013-02-12 15:51:58 +01001162 { sizeof(struct user), "sizeof(struct user)" },
1163#elif defined(BFIN)
Dmitry V. Levinc6ce4fd2014-12-11 19:25:02 +00001164 XLAT_UOFF(u_tsize),
1165 XLAT_UOFF(u_dsize),
1166 XLAT_UOFF(u_ssize),
1167 XLAT_UOFF(start_code),
1168 XLAT_UOFF(signal),
1169 XLAT_UOFF(u_ar0),
1170 XLAT_UOFF(magic),
1171 XLAT_UOFF(u_comm),
Wichert Akkerman76baf7c1999-02-19 00:21:36 +00001172 { sizeof(struct user), "sizeof(struct user)" },
Christian Svensson492f81f2013-02-14 13:26:27 +01001173#elif defined(OR1K)
1174 /* nothing */
James Hogan5f999a82013-02-22 14:44:10 +00001175#elif defined(METAG)
1176 /* nothing */
Chris Zankel8f636ed2013-03-25 10:22:07 -07001177#elif defined(XTENSA)
1178 /* nothing */
Vineet Gupta7daacbb2013-08-16 12:47:06 +05301179#elif defined(ARC)
1180 /* nothing */
Denys Vlasenko3e3490a2012-03-17 01:27:37 +01001181#endif
Dmitry V. Levin59452732014-02-05 02:20:51 +00001182 XLAT_END
Wichert Akkerman76baf7c1999-02-19 00:21:36 +00001183};
1184
1185int
Denys Vlasenkoc7e83712009-02-24 12:59:47 +00001186sys_ptrace(struct tcb *tcp)
Wichert Akkerman76baf7c1999-02-19 00:21:36 +00001187{
Roland McGrathd9f816f2004-09-04 03:39:20 +00001188 const struct xlat *x;
Dmitry V. Levin3ed5d022014-09-10 13:46:04 +00001189 unsigned long addr;
Wichert Akkerman76baf7c1999-02-19 00:21:36 +00001190
Wichert Akkerman76baf7c1999-02-19 00:21:36 +00001191 if (entering(tcp)) {
Denys Vlasenkob7a6dae2012-03-20 16:48:35 +01001192 printxval(ptrace_cmds, tcp->u_arg[0], "PTRACE_???");
Roland McGrathbf621d42003-01-14 09:46:21 +00001193 tprintf(", %lu, ", tcp->u_arg[1]);
Denys Vlasenkobe994972013-02-13 16:10:10 +01001194
Wichert Akkerman76baf7c1999-02-19 00:21:36 +00001195 addr = tcp->u_arg[2];
1196 if (tcp->u_arg[0] == PTRACE_PEEKUSER
Denys Vlasenkobe994972013-02-13 16:10:10 +01001197 || tcp->u_arg[0] == PTRACE_POKEUSER
1198 ) {
Wichert Akkerman76baf7c1999-02-19 00:21:36 +00001199 for (x = struct_user_offsets; x->str; x++) {
1200 if (x->val >= addr)
1201 break;
1202 }
1203 if (!x->str)
1204 tprintf("%#lx, ", addr);
1205 else if (x->val > addr && x != struct_user_offsets) {
1206 x--;
1207 tprintf("%s + %ld, ", x->str, addr - x->val);
1208 }
1209 else
1210 tprintf("%s, ", x->str);
Denys Vlasenkobe994972013-02-13 16:10:10 +01001211 } else
1212#ifdef PTRACE_GETREGSET
Dmitry V. Levinc41808b2013-03-18 00:52:29 +00001213 if (tcp->u_arg[0] == PTRACE_GETREGSET
1214 || tcp->u_arg[0] == PTRACE_SETREGSET
1215 ) {
1216 printxval(nt_descriptor_types, tcp->u_arg[2], "NT_???");
1217 tprints(", ");
1218 } else
Denys Vlasenkobe994972013-02-13 16:10:10 +01001219#endif
1220 tprintf("%#lx, ", addr);
1221
1222
Wichert Akkerman76baf7c1999-02-19 00:21:36 +00001223 switch (tcp->u_arg[0]) {
Denys Vlasenko3e3490a2012-03-17 01:27:37 +01001224#ifndef IA64
Wichert Akkerman76baf7c1999-02-19 00:21:36 +00001225 case PTRACE_PEEKDATA:
1226 case PTRACE_PEEKTEXT:
1227 case PTRACE_PEEKUSER:
1228 break;
Denys Vlasenko3e3490a2012-03-17 01:27:37 +01001229#endif
Wichert Akkerman76baf7c1999-02-19 00:21:36 +00001230 case PTRACE_CONT:
1231 case PTRACE_SINGLESTEP:
1232 case PTRACE_SYSCALL:
1233 case PTRACE_DETACH:
1234 printsignal(tcp->u_arg[3]);
1235 break;
Denys Vlasenko3e3490a2012-03-17 01:27:37 +01001236#ifdef PTRACE_SETOPTIONS
Denys Vlasenkof535b542009-01-13 18:30:55 +00001237 case PTRACE_SETOPTIONS:
1238 printflags(ptrace_setoptions_flags, tcp->u_arg[3], "PTRACE_O_???");
1239 break;
Denys Vlasenko3e3490a2012-03-17 01:27:37 +01001240#endif
1241#ifdef PTRACE_SETSIGINFO
Denys Vlasenkof535b542009-01-13 18:30:55 +00001242 case PTRACE_SETSIGINFO: {
Denys Vlasenkod4d3ede2013-02-13 16:31:32 +01001243 printsiginfo_at(tcp, tcp->u_arg[3]);
Denys Vlasenkof535b542009-01-13 18:30:55 +00001244 break;
1245 }
Denys Vlasenko3e3490a2012-03-17 01:27:37 +01001246#endif
1247#ifdef PTRACE_GETSIGINFO
Denys Vlasenkof535b542009-01-13 18:30:55 +00001248 case PTRACE_GETSIGINFO:
1249 /* Don't print anything, do it at syscall return. */
1250 break;
Denys Vlasenko3e3490a2012-03-17 01:27:37 +01001251#endif
Denys Vlasenkobe994972013-02-13 16:10:10 +01001252#ifdef PTRACE_GETREGSET
1253 case PTRACE_GETREGSET:
1254 break;
1255 case PTRACE_SETREGSET:
1256 tprint_iov(tcp, /*len:*/ 1, tcp->u_arg[3], /*as string:*/ 0);
1257 break;
1258#endif
Wichert Akkerman76baf7c1999-02-19 00:21:36 +00001259 default:
1260 tprintf("%#lx", tcp->u_arg[3]);
1261 break;
1262 }
1263 } else {
1264 switch (tcp->u_arg[0]) {
1265 case PTRACE_PEEKDATA:
1266 case PTRACE_PEEKTEXT:
1267 case PTRACE_PEEKUSER:
Denys Vlasenko3e3490a2012-03-17 01:27:37 +01001268#ifdef IA64
Roland McGrath1e868062007-11-19 22:11:45 +00001269 return RVAL_HEX;
Denys Vlasenko3e3490a2012-03-17 01:27:37 +01001270#else
Roland McGratheb285352003-01-14 09:59:00 +00001271 printnum(tcp, tcp->u_arg[3], "%#lx");
Wichert Akkerman76baf7c1999-02-19 00:21:36 +00001272 break;
Denys Vlasenko3e3490a2012-03-17 01:27:37 +01001273#endif
1274#ifdef PTRACE_GETSIGINFO
Denys Vlasenkof535b542009-01-13 18:30:55 +00001275 case PTRACE_GETSIGINFO: {
Denys Vlasenkod4d3ede2013-02-13 16:31:32 +01001276 printsiginfo_at(tcp, tcp->u_arg[3]);
Denys Vlasenkof535b542009-01-13 18:30:55 +00001277 break;
1278 }
Denys Vlasenko3e3490a2012-03-17 01:27:37 +01001279#endif
Denys Vlasenkobe994972013-02-13 16:10:10 +01001280#ifdef PTRACE_GETREGSET
1281 case PTRACE_GETREGSET:
1282 tprint_iov(tcp, /*len:*/ 1, tcp->u_arg[3], /*as string:*/ 0);
1283 break;
1284#endif
Wichert Akkerman76baf7c1999-02-19 00:21:36 +00001285 }
1286 }
Wichert Akkerman76baf7c1999-02-19 00:21:36 +00001287 return 0;
1288}