Revert "Revert "Upgrade to 5.0.71.48"" DO NOT MERGE
This reverts commit f2e3994fa5148cc3d9946666f0b0596290192b0e,
and updates the x64 makefile properly so it doesn't break that
build.
FPIIM-449
Change-Id: Ib83e35bfbae6af627451c926a9650ec57c045605
(cherry picked from commit 109988c7ccb6f3fd1a58574fa3dfb88beaef6632)
diff --git a/src/mips/assembler-mips.cc b/src/mips/assembler-mips.cc
index a8b6cc7..e50a239 100644
--- a/src/mips/assembler-mips.cc
+++ b/src/mips/assembler-mips.cc
@@ -285,10 +285,7 @@
void Assembler::GetCode(CodeDesc* desc) {
- if (IsPrevInstrCompactBranch()) {
- nop();
- ClearCompactBranchState();
- }
+ EmitForbiddenSlotInstruction();
DCHECK(pc_ <= reloc_info_writer.pos()); // No overlap.
// Set up code descriptor.
desc->buffer = buffer_;
@@ -302,10 +299,7 @@
void Assembler::Align(int m) {
DCHECK(m >= 4 && base::bits::IsPowerOfTwo32(m));
- if (IsPrevInstrCompactBranch()) {
- nop();
- ClearCompactBranchState();
- }
+ EmitForbiddenSlotInstruction();
while ((pc_offset() & (m - 1)) != 0) {
nop();
}
@@ -2092,20 +2086,7 @@
// Workaround for non-8-byte alignment of HeapNumber, convert 64-bit
// load to two 32-bit loads.
DCHECK(!src.rm().is(at));
- if (IsFp64Mode()) {
- if (is_int16(src.offset_) && is_int16(src.offset_ + kIntSize)) {
- GenInstrImmediate(LWC1, src.rm(), fd,
- src.offset_ + Register::kMantissaOffset);
- GenInstrImmediate(LW, src.rm(), at,
- src.offset_ + Register::kExponentOffset);
- mthc1(at, fd);
- } else { // Offset > 16 bits, use multiple instructions to load.
- LoadRegPlusOffsetToAt(src);
- GenInstrImmediate(LWC1, at, fd, Register::kMantissaOffset);
- GenInstrImmediate(LW, at, at, Register::kExponentOffset);
- mthc1(at, fd);
- }
- } else { // fp32 mode.
+ if (IsFp32Mode()) { // fp32 mode.
if (is_int16(src.offset_) && is_int16(src.offset_ + kIntSize)) {
GenInstrImmediate(LWC1, src.rm(), fd,
src.offset_ + Register::kMantissaOffset);
@@ -2120,6 +2101,22 @@
nextfpreg.setcode(fd.code() + 1);
GenInstrImmediate(LWC1, at, nextfpreg, Register::kExponentOffset);
}
+ } else {
+ DCHECK(IsFp64Mode() || IsFpxxMode());
+ // Currently we support FPXX and FP64 on Mips32r2 and Mips32r6
+ DCHECK(IsMipsArchVariant(kMips32r2) || IsMipsArchVariant(kMips32r6));
+ if (is_int16(src.offset_) && is_int16(src.offset_ + kIntSize)) {
+ GenInstrImmediate(LWC1, src.rm(), fd,
+ src.offset_ + Register::kMantissaOffset);
+ GenInstrImmediate(LW, src.rm(), at,
+ src.offset_ + Register::kExponentOffset);
+ mthc1(at, fd);
+ } else { // Offset > 16 bits, use multiple instructions to load.
+ LoadRegPlusOffsetToAt(src);
+ GenInstrImmediate(LWC1, at, fd, Register::kMantissaOffset);
+ GenInstrImmediate(LW, at, at, Register::kExponentOffset);
+ mthc1(at, fd);
+ }
}
}
@@ -2139,20 +2136,7 @@
// store to two 32-bit stores.
DCHECK(!src.rm().is(at));
DCHECK(!src.rm().is(t8));
- if (IsFp64Mode()) {
- if (is_int16(src.offset_) && is_int16(src.offset_ + kIntSize)) {
- GenInstrImmediate(SWC1, src.rm(), fd,
- src.offset_ + Register::kMantissaOffset);
- mfhc1(at, fd);
- GenInstrImmediate(SW, src.rm(), at,
- src.offset_ + Register::kExponentOffset);
- } else { // Offset > 16 bits, use multiple instructions to load.
- LoadRegPlusOffsetToAt(src);
- GenInstrImmediate(SWC1, at, fd, Register::kMantissaOffset);
- mfhc1(t8, fd);
- GenInstrImmediate(SW, at, t8, Register::kExponentOffset);
- }
- } else { // fp32 mode.
+ if (IsFp32Mode()) { // fp32 mode.
if (is_int16(src.offset_) && is_int16(src.offset_ + kIntSize)) {
GenInstrImmediate(SWC1, src.rm(), fd,
src.offset_ + Register::kMantissaOffset);
@@ -2167,6 +2151,22 @@
nextfpreg.setcode(fd.code() + 1);
GenInstrImmediate(SWC1, at, nextfpreg, Register::kExponentOffset);
}
+ } else {
+ DCHECK(IsFp64Mode() || IsFpxxMode());
+ // Currently we support FPXX and FP64 on Mips32r2 and Mips32r6
+ DCHECK(IsMipsArchVariant(kMips32r2) || IsMipsArchVariant(kMips32r6));
+ if (is_int16(src.offset_) && is_int16(src.offset_ + kIntSize)) {
+ GenInstrImmediate(SWC1, src.rm(), fd,
+ src.offset_ + Register::kMantissaOffset);
+ mfhc1(at, fd);
+ GenInstrImmediate(SW, src.rm(), at,
+ src.offset_ + Register::kExponentOffset);
+ } else { // Offset > 16 bits, use multiple instructions to load.
+ LoadRegPlusOffsetToAt(src);
+ GenInstrImmediate(SWC1, at, fd, Register::kMantissaOffset);
+ mfhc1(t8, fd);
+ GenInstrImmediate(SW, at, t8, Register::kExponentOffset);
+ }
}
}