tree 58c5c0c83fd997ff172dd47fc7d148fc3baa2e1b
parent 7b6942b5f764ef3f146954bef70458db6a71e25d
author Paul Lind <paul.lind@imgtec.com> 1367881769 -0700
committer Paul Lind <paul.lind@imgtec.com> 1367881807 -0700

Use kernel cacheflush for large sizes on MIPS.

This is a workaround to a deserializer bug. The bug was exposed
with a recent optimization to use user-mode cache-flushing on
MIPS. To reduce risk, we're doing a workaround in mips-specific
code so that other arch's cannot be affected.

The deserializer does this FlushICache:

  CPU::FlushICache(last_object_address_, Page::kPageSize);

However, that region includes OS guard-pages with no access
privilege. The MIPS kernel cacheflush routines work OK in this
case, but the Bionic cacheflush recently enabled user-mode flushing
using the synci instruction, which causes a segfault on MIPS when
the guard pages are reached.
(change I48fd6f2b0cbe80c3cd90f453ced97a2f154f7ad3)

The workaround just reverts to the kernel flush when the size
is Page::kPageSize or bigger.

A better fix would be to alter the deserializer so that only the
executable pages are flushed:
  CPU::FlushICache(last_object_address_,
                   isolate_->memory_allocator()->CodePageAreaSize());

However, that changes common code for all supported architectures.
There is no evidence that this bug affects the other arch's, so we
are doing a MIPS-specific workaround.

Change-Id: I30b62eb579feab1453d3ae85a5fb9b408f91756b
Signed-off-by: Paul Lind <paul.lind@imgtec.com>