Upgrade V8 to version 4.9.385.28
https://chromium.googlesource.com/v8/v8/+/4.9.385.28
FPIIM-449
Change-Id: I4b2e74289d4bf3667f2f3dc8aa2e541f63e26eb4
diff --git a/test/unittests/compiler/arm64/instruction-selector-arm64-unittest.cc b/test/unittests/compiler/arm64/instruction-selector-arm64-unittest.cc
index cd3ce09..73532aa 100644
--- a/test/unittests/compiler/arm64/instruction-selector-arm64-unittest.cc
+++ b/test/unittests/compiler/arm64/instruction-selector-arm64-unittest.cc
@@ -10,8 +10,6 @@
namespace {
-typedef RawMachineAssembler::Label MLabel;
-
template <typename T>
struct MachInst {
T constructor;
@@ -45,12 +43,12 @@
// machine type.
Node* BuildConstant(InstructionSelectorTest::StreamBuilder& m, MachineType type,
int64_t value) {
- switch (type) {
- case kMachInt32:
- return m.Int32Constant(value);
+ switch (type.representation()) {
+ case MachineRepresentation::kWord32:
+ return m.Int32Constant(static_cast<int32_t>(value));
break;
- case kMachInt64:
+ case MachineRepresentation::kWord64:
return m.Int64Constant(value);
break;
@@ -62,19 +60,25 @@
// ARM64 logical instructions.
-static const MachInst2 kLogicalInstructions[] = {
- {&RawMachineAssembler::Word32And, "Word32And", kArm64And32, kMachInt32},
- {&RawMachineAssembler::Word64And, "Word64And", kArm64And, kMachInt64},
- {&RawMachineAssembler::Word32Or, "Word32Or", kArm64Or32, kMachInt32},
- {&RawMachineAssembler::Word64Or, "Word64Or", kArm64Or, kMachInt64},
- {&RawMachineAssembler::Word32Xor, "Word32Xor", kArm64Eor32, kMachInt32},
- {&RawMachineAssembler::Word64Xor, "Word64Xor", kArm64Eor, kMachInt64}};
+const MachInst2 kLogicalInstructions[] = {
+ {&RawMachineAssembler::Word32And, "Word32And", kArm64And32,
+ MachineType::Int32()},
+ {&RawMachineAssembler::Word64And, "Word64And", kArm64And,
+ MachineType::Int64()},
+ {&RawMachineAssembler::Word32Or, "Word32Or", kArm64Or32,
+ MachineType::Int32()},
+ {&RawMachineAssembler::Word64Or, "Word64Or", kArm64Or,
+ MachineType::Int64()},
+ {&RawMachineAssembler::Word32Xor, "Word32Xor", kArm64Eor32,
+ MachineType::Int32()},
+ {&RawMachineAssembler::Word64Xor, "Word64Xor", kArm64Eor,
+ MachineType::Int64()}};
// ARM64 logical immediates: contiguous set bits, rotated about a power of two
// sized block. The block is then duplicated across the word. Below is a random
// subset of the 32-bit immediates.
-static const uint32_t kLogical32Immediates[] = {
+const uint32_t kLogical32Immediates[] = {
0x00000002, 0x00000003, 0x00000070, 0x00000080, 0x00000100, 0x000001c0,
0x00000300, 0x000007e0, 0x00003ffc, 0x00007fc0, 0x0003c000, 0x0003f000,
0x0003ffc0, 0x0003fff8, 0x0007ff00, 0x0007ffe0, 0x000e0000, 0x001e0000,
@@ -95,7 +99,7 @@
// Random subset of 64-bit logical immediates.
-static const uint64_t kLogical64Immediates[] = {
+const uint64_t kLogical64Immediates[] = {
0x0000000000000001, 0x0000000000000002, 0x0000000000000003,
0x0000000000000070, 0x0000000000000080, 0x0000000000000100,
0x00000000000001c0, 0x0000000000000300, 0x0000000000000600,
@@ -131,20 +135,24 @@
}
-static const AddSub kAddSubInstructions[] = {
- {{&RawMachineAssembler::Int32Add, "Int32Add", kArm64Add32, kMachInt32},
+const AddSub kAddSubInstructions[] = {
+ {{&RawMachineAssembler::Int32Add, "Int32Add", kArm64Add32,
+ MachineType::Int32()},
kArm64Sub32},
- {{&RawMachineAssembler::Int64Add, "Int64Add", kArm64Add, kMachInt64},
+ {{&RawMachineAssembler::Int64Add, "Int64Add", kArm64Add,
+ MachineType::Int64()},
kArm64Sub},
- {{&RawMachineAssembler::Int32Sub, "Int32Sub", kArm64Sub32, kMachInt32},
+ {{&RawMachineAssembler::Int32Sub, "Int32Sub", kArm64Sub32,
+ MachineType::Int32()},
kArm64Add32},
- {{&RawMachineAssembler::Int64Sub, "Int64Sub", kArm64Sub, kMachInt64},
+ {{&RawMachineAssembler::Int64Sub, "Int64Sub", kArm64Sub,
+ MachineType::Int64()},
kArm64Add}};
// ARM64 Add/Sub immediates: 12-bit immediate optionally shifted by 12.
// Below is a combination of a random subset and some edge values.
-static const int32_t kAddSubImmediates[] = {
+const int32_t kAddSubImmediates[] = {
0, 1, 69, 493, 599, 701, 719,
768, 818, 842, 945, 1246, 1286, 1429,
1669, 2171, 2179, 2182, 2254, 2334, 2338,
@@ -160,66 +168,85 @@
// ARM64 flag setting data processing instructions.
-static const MachInst2 kDPFlagSetInstructions[] = {
- {&RawMachineAssembler::Word32And, "Word32And", kArm64Tst32, kMachInt32},
- {&RawMachineAssembler::Int32Add, "Int32Add", kArm64Cmn32, kMachInt32},
- {&RawMachineAssembler::Int32Sub, "Int32Sub", kArm64Cmp32, kMachInt32},
- {&RawMachineAssembler::Word64And, "Word64And", kArm64Tst, kMachInt64}};
+const MachInst2 kDPFlagSetInstructions[] = {
+ {&RawMachineAssembler::Word32And, "Word32And", kArm64Tst32,
+ MachineType::Int32()},
+ {&RawMachineAssembler::Int32Add, "Int32Add", kArm64Cmn32,
+ MachineType::Int32()},
+ {&RawMachineAssembler::Int32Sub, "Int32Sub", kArm64Cmp32,
+ MachineType::Int32()},
+ {&RawMachineAssembler::Word64And, "Word64And", kArm64Tst,
+ MachineType::Int64()}};
// ARM64 arithmetic with overflow instructions.
-static const MachInst2 kOvfAddSubInstructions[] = {
+const MachInst2 kOvfAddSubInstructions[] = {
{&RawMachineAssembler::Int32AddWithOverflow, "Int32AddWithOverflow",
- kArm64Add32, kMachInt32},
+ kArm64Add32, MachineType::Int32()},
{&RawMachineAssembler::Int32SubWithOverflow, "Int32SubWithOverflow",
- kArm64Sub32, kMachInt32}};
+ kArm64Sub32, MachineType::Int32()}};
// ARM64 shift instructions.
-static const Shift kShiftInstructions[] = {
- {{&RawMachineAssembler::Word32Shl, "Word32Shl", kArm64Lsl32, kMachInt32},
+const Shift kShiftInstructions[] = {
+ {{&RawMachineAssembler::Word32Shl, "Word32Shl", kArm64Lsl32,
+ MachineType::Int32()},
kMode_Operand2_R_LSL_I},
- {{&RawMachineAssembler::Word64Shl, "Word64Shl", kArm64Lsl, kMachInt64},
+ {{&RawMachineAssembler::Word64Shl, "Word64Shl", kArm64Lsl,
+ MachineType::Int64()},
kMode_Operand2_R_LSL_I},
- {{&RawMachineAssembler::Word32Shr, "Word32Shr", kArm64Lsr32, kMachInt32},
+ {{&RawMachineAssembler::Word32Shr, "Word32Shr", kArm64Lsr32,
+ MachineType::Int32()},
kMode_Operand2_R_LSR_I},
- {{&RawMachineAssembler::Word64Shr, "Word64Shr", kArm64Lsr, kMachInt64},
+ {{&RawMachineAssembler::Word64Shr, "Word64Shr", kArm64Lsr,
+ MachineType::Int64()},
kMode_Operand2_R_LSR_I},
- {{&RawMachineAssembler::Word32Sar, "Word32Sar", kArm64Asr32, kMachInt32},
+ {{&RawMachineAssembler::Word32Sar, "Word32Sar", kArm64Asr32,
+ MachineType::Int32()},
kMode_Operand2_R_ASR_I},
- {{&RawMachineAssembler::Word64Sar, "Word64Sar", kArm64Asr, kMachInt64},
+ {{&RawMachineAssembler::Word64Sar, "Word64Sar", kArm64Asr,
+ MachineType::Int64()},
kMode_Operand2_R_ASR_I},
- {{&RawMachineAssembler::Word32Ror, "Word32Ror", kArm64Ror32, kMachInt32},
+ {{&RawMachineAssembler::Word32Ror, "Word32Ror", kArm64Ror32,
+ MachineType::Int32()},
kMode_Operand2_R_ROR_I},
- {{&RawMachineAssembler::Word64Ror, "Word64Ror", kArm64Ror, kMachInt64},
+ {{&RawMachineAssembler::Word64Ror, "Word64Ror", kArm64Ror,
+ MachineType::Int64()},
kMode_Operand2_R_ROR_I}};
// ARM64 Mul/Div instructions.
-static const MachInst2 kMulDivInstructions[] = {
- {&RawMachineAssembler::Int32Mul, "Int32Mul", kArm64Mul32, kMachInt32},
- {&RawMachineAssembler::Int64Mul, "Int64Mul", kArm64Mul, kMachInt64},
- {&RawMachineAssembler::Int32Div, "Int32Div", kArm64Idiv32, kMachInt32},
- {&RawMachineAssembler::Int64Div, "Int64Div", kArm64Idiv, kMachInt64},
- {&RawMachineAssembler::Uint32Div, "Uint32Div", kArm64Udiv32, kMachInt32},
- {&RawMachineAssembler::Uint64Div, "Uint64Div", kArm64Udiv, kMachInt64}};
+const MachInst2 kMulDivInstructions[] = {
+ {&RawMachineAssembler::Int32Mul, "Int32Mul", kArm64Mul32,
+ MachineType::Int32()},
+ {&RawMachineAssembler::Int64Mul, "Int64Mul", kArm64Mul,
+ MachineType::Int64()},
+ {&RawMachineAssembler::Int32Div, "Int32Div", kArm64Idiv32,
+ MachineType::Int32()},
+ {&RawMachineAssembler::Int64Div, "Int64Div", kArm64Idiv,
+ MachineType::Int64()},
+ {&RawMachineAssembler::Uint32Div, "Uint32Div", kArm64Udiv32,
+ MachineType::Int32()},
+ {&RawMachineAssembler::Uint64Div, "Uint64Div", kArm64Udiv,
+ MachineType::Int64()}};
// ARM64 FP arithmetic instructions.
-static const MachInst2 kFPArithInstructions[] = {
+const MachInst2 kFPArithInstructions[] = {
{&RawMachineAssembler::Float64Add, "Float64Add", kArm64Float64Add,
- kMachFloat64},
+ MachineType::Float64()},
{&RawMachineAssembler::Float64Sub, "Float64Sub", kArm64Float64Sub,
- kMachFloat64},
+ MachineType::Float64()},
{&RawMachineAssembler::Float64Mul, "Float64Mul", kArm64Float64Mul,
- kMachFloat64},
+ MachineType::Float64()},
{&RawMachineAssembler::Float64Div, "Float64Div", kArm64Float64Div,
- kMachFloat64}};
+ MachineType::Float64()}};
struct FPCmp {
MachInst2 mi;
FlagsCondition cond;
+ FlagsCondition commuted_cond;
};
@@ -229,16 +256,31 @@
// ARM64 FP comparison instructions.
-static const FPCmp kFPCmpInstructions[] = {
+const FPCmp kFPCmpInstructions[] = {
{{&RawMachineAssembler::Float64Equal, "Float64Equal", kArm64Float64Cmp,
- kMachFloat64},
- kUnorderedEqual},
+ MachineType::Float64()},
+ kEqual,
+ kEqual},
{{&RawMachineAssembler::Float64LessThan, "Float64LessThan",
- kArm64Float64Cmp, kMachFloat64},
- kUnorderedLessThan},
+ kArm64Float64Cmp, MachineType::Float64()},
+ kFloatLessThan,
+ kFloatGreaterThan},
{{&RawMachineAssembler::Float64LessThanOrEqual, "Float64LessThanOrEqual",
- kArm64Float64Cmp, kMachFloat64},
- kUnorderedLessThanOrEqual}};
+ kArm64Float64Cmp, MachineType::Float64()},
+ kFloatLessThanOrEqual,
+ kFloatGreaterThanOrEqual},
+ {{&RawMachineAssembler::Float32Equal, "Float32Equal", kArm64Float32Cmp,
+ MachineType::Float32()},
+ kEqual,
+ kEqual},
+ {{&RawMachineAssembler::Float32LessThan, "Float32LessThan",
+ kArm64Float32Cmp, MachineType::Float32()},
+ kFloatLessThan,
+ kFloatGreaterThan},
+ {{&RawMachineAssembler::Float32LessThanOrEqual, "Float32LessThanOrEqual",
+ kArm64Float32Cmp, MachineType::Float32()},
+ kFloatLessThanOrEqual,
+ kFloatGreaterThanOrEqual}};
struct Conversion {
@@ -254,34 +296,35 @@
// ARM64 type conversion instructions.
-static const Conversion kConversionInstructions[] = {
+const Conversion kConversionInstructions[] = {
{{&RawMachineAssembler::ChangeFloat32ToFloat64, "ChangeFloat32ToFloat64",
- kArm64Float32ToFloat64, kMachFloat64},
- kMachFloat32},
+ kArm64Float32ToFloat64, MachineType::Float64()},
+ MachineType::Float32()},
{{&RawMachineAssembler::TruncateFloat64ToFloat32,
- "TruncateFloat64ToFloat32", kArm64Float64ToFloat32, kMachFloat32},
- kMachFloat64},
+ "TruncateFloat64ToFloat32", kArm64Float64ToFloat32,
+ MachineType::Float32()},
+ MachineType::Float64()},
{{&RawMachineAssembler::ChangeInt32ToInt64, "ChangeInt32ToInt64",
- kArm64Sxtw, kMachInt64},
- kMachInt32},
+ kArm64Sxtw, MachineType::Int64()},
+ MachineType::Int32()},
{{&RawMachineAssembler::ChangeUint32ToUint64, "ChangeUint32ToUint64",
- kArm64Mov32, kMachUint64},
- kMachUint32},
+ kArm64Mov32, MachineType::Uint64()},
+ MachineType::Uint32()},
{{&RawMachineAssembler::TruncateInt64ToInt32, "TruncateInt64ToInt32",
- kArm64Mov32, kMachInt32},
- kMachInt64},
+ kArm64Mov32, MachineType::Int32()},
+ MachineType::Int64()},
{{&RawMachineAssembler::ChangeInt32ToFloat64, "ChangeInt32ToFloat64",
- kArm64Int32ToFloat64, kMachFloat64},
- kMachInt32},
+ kArm64Int32ToFloat64, MachineType::Float64()},
+ MachineType::Int32()},
{{&RawMachineAssembler::ChangeUint32ToFloat64, "ChangeUint32ToFloat64",
- kArm64Uint32ToFloat64, kMachFloat64},
- kMachUint32},
+ kArm64Uint32ToFloat64, MachineType::Float64()},
+ MachineType::Uint32()},
{{&RawMachineAssembler::ChangeFloat64ToInt32, "ChangeFloat64ToInt32",
- kArm64Float64ToInt32, kMachInt32},
- kMachFloat64},
+ kArm64Float64ToInt32, MachineType::Int32()},
+ MachineType::Float64()},
{{&RawMachineAssembler::ChangeFloat64ToUint32, "ChangeFloat64ToUint32",
- kArm64Float64ToUint32, kMachUint32},
- kMachFloat64}};
+ kArm64Float64ToUint32, MachineType::Uint32()},
+ MachineType::Float64()}};
} // namespace
@@ -311,7 +354,7 @@
const MachInst2 dpi = GetParam();
const MachineType type = dpi.machine_type;
// TODO(all): Add support for testing 64-bit immediates.
- if (type == kMachInt32) {
+ if (type == MachineType::Int32()) {
// Immediate on the right.
TRACED_FOREACH(int32_t, imm, kLogical32Immediates) {
StreamBuilder m(this, type, type);
@@ -348,7 +391,7 @@
// Only test 64-bit shifted operands with 64-bit instructions.
if (shift.mi.machine_type != type) continue;
- TRACED_FORRANGE(int, imm, 0, ((type == kMachInt32) ? 31 : 63)) {
+ TRACED_FORRANGE(int, imm, 0, ((type == MachineType::Int32()) ? 31 : 63)) {
StreamBuilder m(this, type, type, type);
m.Return((m.*dpi.constructor)(
m.Parameter(0),
@@ -363,7 +406,7 @@
EXPECT_EQ(1U, s[0]->OutputCount());
}
- TRACED_FORRANGE(int, imm, 0, ((type == kMachInt32) ? 31 : 63)) {
+ TRACED_FORRANGE(int, imm, 0, ((type == MachineType::Int32()) ? 31 : 63)) {
StreamBuilder m(this, type, type, type);
m.Return((m.*dpi.constructor)(
(m.*shift.mi.constructor)(m.Parameter(1),
@@ -454,7 +497,7 @@
continue;
}
- TRACED_FORRANGE(int, imm, 0, ((type == kMachInt32) ? 31 : 63)) {
+ TRACED_FORRANGE(int, imm, 0, ((type == MachineType::Int32()) ? 31 : 63)) {
StreamBuilder m(this, type, type, type);
m.Return((m.*dpi.mi.constructor)(
m.Parameter(0),
@@ -472,6 +515,70 @@
}
+TEST_P(InstructionSelectorAddSubTest, UnsignedExtendByte) {
+ const AddSub dpi = GetParam();
+ const MachineType type = dpi.mi.machine_type;
+ StreamBuilder m(this, type, type, type);
+ m.Return((m.*dpi.mi.constructor)(
+ m.Parameter(0), m.Word32And(m.Parameter(1), m.Int32Constant(0xff))));
+ Stream s = m.Build();
+ ASSERT_EQ(1U, s.size());
+ EXPECT_EQ(dpi.mi.arch_opcode, s[0]->arch_opcode());
+ EXPECT_EQ(kMode_Operand2_R_UXTB, s[0]->addressing_mode());
+ ASSERT_EQ(2U, s[0]->InputCount());
+ ASSERT_EQ(1U, s[0]->OutputCount());
+}
+
+
+TEST_P(InstructionSelectorAddSubTest, UnsignedExtendHalfword) {
+ const AddSub dpi = GetParam();
+ const MachineType type = dpi.mi.machine_type;
+ StreamBuilder m(this, type, type, type);
+ m.Return((m.*dpi.mi.constructor)(
+ m.Parameter(0), m.Word32And(m.Parameter(1), m.Int32Constant(0xffff))));
+ Stream s = m.Build();
+ ASSERT_EQ(1U, s.size());
+ EXPECT_EQ(dpi.mi.arch_opcode, s[0]->arch_opcode());
+ EXPECT_EQ(kMode_Operand2_R_UXTH, s[0]->addressing_mode());
+ ASSERT_EQ(2U, s[0]->InputCount());
+ ASSERT_EQ(1U, s[0]->OutputCount());
+}
+
+
+TEST_P(InstructionSelectorAddSubTest, SignedExtendByte) {
+ const AddSub dpi = GetParam();
+ const MachineType type = dpi.mi.machine_type;
+ StreamBuilder m(this, type, type, type);
+ m.Return((m.*dpi.mi.constructor)(
+ m.Parameter(0),
+ m.Word32Sar(m.Word32Shl(m.Parameter(1), m.Int32Constant(24)),
+ m.Int32Constant(24))));
+ Stream s = m.Build();
+ ASSERT_EQ(1U, s.size());
+ EXPECT_EQ(dpi.mi.arch_opcode, s[0]->arch_opcode());
+ EXPECT_EQ(kMode_Operand2_R_SXTB, s[0]->addressing_mode());
+ ASSERT_EQ(2U, s[0]->InputCount());
+ ASSERT_EQ(1U, s[0]->OutputCount());
+}
+
+
+TEST_P(InstructionSelectorAddSubTest, SignedExtendHalfword) {
+ const AddSub dpi = GetParam();
+ const MachineType type = dpi.mi.machine_type;
+ StreamBuilder m(this, type, type, type);
+ m.Return((m.*dpi.mi.constructor)(
+ m.Parameter(0),
+ m.Word32Sar(m.Word32Shl(m.Parameter(1), m.Int32Constant(16)),
+ m.Int32Constant(16))));
+ Stream s = m.Build();
+ ASSERT_EQ(1U, s.size());
+ EXPECT_EQ(dpi.mi.arch_opcode, s[0]->arch_opcode());
+ EXPECT_EQ(kMode_Operand2_R_SXTH, s[0]->addressing_mode());
+ ASSERT_EQ(2U, s[0]->InputCount());
+ ASSERT_EQ(1U, s[0]->OutputCount());
+}
+
+
INSTANTIATE_TEST_CASE_P(InstructionSelectorTest, InstructionSelectorAddSubTest,
::testing::ValuesIn(kAddSubInstructions));
@@ -480,7 +587,7 @@
{
// 32-bit add.
TRACED_FOREACH(int32_t, imm, kAddSubImmediates) {
- StreamBuilder m(this, kMachInt32, kMachInt32);
+ StreamBuilder m(this, MachineType::Int32(), MachineType::Int32());
m.Return(m.Int32Add(m.Int32Constant(imm), m.Parameter(0)));
Stream s = m.Build();
ASSERT_EQ(1U, s.size());
@@ -494,7 +601,7 @@
{
// 64-bit add.
TRACED_FOREACH(int32_t, imm, kAddSubImmediates) {
- StreamBuilder m(this, kMachInt64, kMachInt64);
+ StreamBuilder m(this, MachineType::Int64(), MachineType::Int64());
m.Return(m.Int64Add(m.Int64Constant(imm), m.Parameter(0)));
Stream s = m.Build();
ASSERT_EQ(1U, s.size());
@@ -509,38 +616,101 @@
TEST_F(InstructionSelectorTest, SubZeroOnLeft) {
- // Subtraction with zero on the left maps to Neg.
{
// 32-bit subtract.
- StreamBuilder m(this, kMachInt32, kMachInt32, kMachInt32);
+ StreamBuilder m(this, MachineType::Int32(), MachineType::Int32(),
+ MachineType::Int32());
m.Return(m.Int32Sub(m.Int32Constant(0), m.Parameter(0)));
Stream s = m.Build();
ASSERT_EQ(1U, s.size());
- EXPECT_EQ(kArm64Neg32, s[0]->arch_opcode());
- EXPECT_EQ(1U, s[0]->InputCount());
+ EXPECT_EQ(kArm64Sub32, s[0]->arch_opcode());
+ ASSERT_EQ(2U, s[0]->InputCount());
+ EXPECT_TRUE(s[0]->InputAt(0)->IsImmediate());
+ EXPECT_EQ(0, s.ToInt32(s[0]->InputAt(0)));
EXPECT_EQ(1U, s[0]->OutputCount());
}
{
// 64-bit subtract.
- StreamBuilder m(this, kMachInt64, kMachInt64, kMachInt64);
+ StreamBuilder m(this, MachineType::Int64(), MachineType::Int64(),
+ MachineType::Int64());
m.Return(m.Int64Sub(m.Int64Constant(0), m.Parameter(0)));
Stream s = m.Build();
ASSERT_EQ(1U, s.size());
- EXPECT_EQ(kArm64Neg, s[0]->arch_opcode());
- EXPECT_EQ(1U, s[0]->InputCount());
+ EXPECT_EQ(kArm64Sub, s[0]->arch_opcode());
+ ASSERT_EQ(2U, s[0]->InputCount());
+ EXPECT_TRUE(s[0]->InputAt(0)->IsImmediate());
+ EXPECT_EQ(0, s.ToInt64(s[0]->InputAt(0)));
EXPECT_EQ(1U, s[0]->OutputCount());
}
}
+TEST_F(InstructionSelectorTest, SubZeroOnLeftWithShift) {
+ TRACED_FOREACH(Shift, shift, kShiftInstructions) {
+ {
+ // Test 32-bit operations. Ignore ROR shifts, as subtract does not
+ // support them.
+ if ((shift.mi.machine_type != MachineType::Int32()) ||
+ (shift.mi.arch_opcode == kArm64Ror32) ||
+ (shift.mi.arch_opcode == kArm64Ror))
+ continue;
+
+ TRACED_FORRANGE(int, imm, -32, 63) {
+ StreamBuilder m(this, MachineType::Int32(), MachineType::Int32(),
+ MachineType::Int32());
+ m.Return(m.Int32Sub(
+ m.Int32Constant(0),
+ (m.*shift.mi.constructor)(m.Parameter(1), m.Int32Constant(imm))));
+ Stream s = m.Build();
+
+ ASSERT_EQ(1U, s.size());
+ EXPECT_EQ(kArm64Sub32, s[0]->arch_opcode());
+ ASSERT_EQ(3U, s[0]->InputCount());
+ EXPECT_TRUE(s[0]->InputAt(0)->IsImmediate());
+ EXPECT_EQ(0, s.ToInt32(s[0]->InputAt(0)));
+ EXPECT_EQ(shift.mode, s[0]->addressing_mode());
+ EXPECT_EQ(imm, s.ToInt32(s[0]->InputAt(2)));
+ EXPECT_EQ(1U, s[0]->OutputCount());
+ }
+ }
+ {
+ // Test 64-bit operations. Ignore ROR shifts, as subtract does not
+ // support them.
+ if ((shift.mi.machine_type != MachineType::Int64()) ||
+ (shift.mi.arch_opcode == kArm64Ror32) ||
+ (shift.mi.arch_opcode == kArm64Ror))
+ continue;
+
+ TRACED_FORRANGE(int, imm, -32, 127) {
+ StreamBuilder m(this, MachineType::Int64(), MachineType::Int64(),
+ MachineType::Int64());
+ m.Return(m.Int64Sub(
+ m.Int64Constant(0),
+ (m.*shift.mi.constructor)(m.Parameter(1), m.Int64Constant(imm))));
+ Stream s = m.Build();
+
+ ASSERT_EQ(1U, s.size());
+ EXPECT_EQ(kArm64Sub, s[0]->arch_opcode());
+ ASSERT_EQ(3U, s[0]->InputCount());
+ EXPECT_TRUE(s[0]->InputAt(0)->IsImmediate());
+ EXPECT_EQ(0, s.ToInt32(s[0]->InputAt(0)));
+ EXPECT_EQ(shift.mode, s[0]->addressing_mode());
+ EXPECT_EQ(imm, s.ToInt32(s[0]->InputAt(2)));
+ EXPECT_EQ(1U, s[0]->OutputCount());
+ }
+ }
+ }
+}
+
+
TEST_F(InstructionSelectorTest, AddNegImmediateOnLeft) {
{
// 32-bit add.
TRACED_FOREACH(int32_t, imm, kAddSubImmediates) {
if (imm == 0) continue;
- StreamBuilder m(this, kMachInt32, kMachInt32);
+ StreamBuilder m(this, MachineType::Int32(), MachineType::Int32());
m.Return(m.Int32Add(m.Int32Constant(-imm), m.Parameter(0)));
Stream s = m.Build();
@@ -556,7 +726,7 @@
// 64-bit add.
TRACED_FOREACH(int32_t, imm, kAddSubImmediates) {
if (imm == 0) continue;
- StreamBuilder m(this, kMachInt64, kMachInt64);
+ StreamBuilder m(this, MachineType::Int64(), MachineType::Int64());
m.Return(m.Int64Add(m.Int64Constant(-imm), m.Parameter(0)));
Stream s = m.Build();
@@ -575,11 +745,14 @@
// 32-bit add.
TRACED_FOREACH(Shift, shift, kShiftInstructions) {
// Only test relevant shifted operands.
- if (shift.mi.machine_type != kMachInt32) continue;
+ if (shift.mi.machine_type != MachineType::Int32()) continue;
if (shift.mi.arch_opcode == kArm64Ror32) continue;
- TRACED_FORRANGE(int, imm, 0, 31) {
- StreamBuilder m(this, kMachInt32, kMachInt32, kMachInt32);
+ // The available shift operand range is `0 <= imm < 32`, but we also test
+ // that immediates outside this range are handled properly (modulo-32).
+ TRACED_FORRANGE(int, imm, -32, 63) {
+ StreamBuilder m(this, MachineType::Int32(), MachineType::Int32(),
+ MachineType::Int32());
m.Return((m.Int32Add)(
(m.*shift.mi.constructor)(m.Parameter(1), m.Int32Constant(imm)),
m.Parameter(0)));
@@ -596,11 +769,14 @@
// 64-bit add.
TRACED_FOREACH(Shift, shift, kShiftInstructions) {
// Only test relevant shifted operands.
- if (shift.mi.machine_type != kMachInt64) continue;
+ if (shift.mi.machine_type != MachineType::Int64()) continue;
if (shift.mi.arch_opcode == kArm64Ror) continue;
- TRACED_FORRANGE(int, imm, 0, 63) {
- StreamBuilder m(this, kMachInt64, kMachInt64, kMachInt64);
+ // The available shift operand range is `0 <= imm < 64`, but we also test
+ // that immediates outside this range are handled properly (modulo-64).
+ TRACED_FORRANGE(int, imm, -64, 127) {
+ StreamBuilder m(this, MachineType::Int64(), MachineType::Int64(),
+ MachineType::Int64());
m.Return((m.Int64Add)(
(m.*shift.mi.constructor)(m.Parameter(1), m.Int64Constant(imm)),
m.Parameter(0)));
@@ -616,6 +792,126 @@
}
+TEST_F(InstructionSelectorTest, AddUnsignedExtendByteOnLeft) {
+ {
+ StreamBuilder m(this, MachineType::Int32(), MachineType::Int32(),
+ MachineType::Int32());
+ m.Return(m.Int32Add(m.Word32And(m.Parameter(0), m.Int32Constant(0xff)),
+ m.Parameter(1)));
+ Stream s = m.Build();
+ ASSERT_EQ(1U, s.size());
+ EXPECT_EQ(kArm64Add32, s[0]->arch_opcode());
+ EXPECT_EQ(kMode_Operand2_R_UXTB, s[0]->addressing_mode());
+ ASSERT_EQ(2U, s[0]->InputCount());
+ ASSERT_EQ(1U, s[0]->OutputCount());
+ }
+ {
+ StreamBuilder m(this, MachineType::Int64(), MachineType::Int32(),
+ MachineType::Int64());
+ m.Return(m.Int64Add(m.Word32And(m.Parameter(0), m.Int32Constant(0xff)),
+ m.Parameter(1)));
+ Stream s = m.Build();
+ ASSERT_EQ(1U, s.size());
+ EXPECT_EQ(kArm64Add, s[0]->arch_opcode());
+ EXPECT_EQ(kMode_Operand2_R_UXTB, s[0]->addressing_mode());
+ ASSERT_EQ(2U, s[0]->InputCount());
+ ASSERT_EQ(1U, s[0]->OutputCount());
+ }
+}
+
+
+TEST_F(InstructionSelectorTest, AddUnsignedExtendHalfwordOnLeft) {
+ {
+ StreamBuilder m(this, MachineType::Int32(), MachineType::Int32(),
+ MachineType::Int32());
+ m.Return(m.Int32Add(m.Word32And(m.Parameter(0), m.Int32Constant(0xffff)),
+ m.Parameter(1)));
+ Stream s = m.Build();
+ ASSERT_EQ(1U, s.size());
+ EXPECT_EQ(kArm64Add32, s[0]->arch_opcode());
+ EXPECT_EQ(kMode_Operand2_R_UXTH, s[0]->addressing_mode());
+ ASSERT_EQ(2U, s[0]->InputCount());
+ ASSERT_EQ(1U, s[0]->OutputCount());
+ }
+ {
+ StreamBuilder m(this, MachineType::Int64(), MachineType::Int32(),
+ MachineType::Int64());
+ m.Return(m.Int64Add(m.Word32And(m.Parameter(0), m.Int32Constant(0xffff)),
+ m.Parameter(1)));
+ Stream s = m.Build();
+ ASSERT_EQ(1U, s.size());
+ EXPECT_EQ(kArm64Add, s[0]->arch_opcode());
+ EXPECT_EQ(kMode_Operand2_R_UXTH, s[0]->addressing_mode());
+ ASSERT_EQ(2U, s[0]->InputCount());
+ ASSERT_EQ(1U, s[0]->OutputCount());
+ }
+}
+
+
+TEST_F(InstructionSelectorTest, AddSignedExtendByteOnLeft) {
+ {
+ StreamBuilder m(this, MachineType::Int32(), MachineType::Int32(),
+ MachineType::Int32());
+ m.Return(
+ m.Int32Add(m.Word32Sar(m.Word32Shl(m.Parameter(0), m.Int32Constant(24)),
+ m.Int32Constant(24)),
+ m.Parameter(1)));
+ Stream s = m.Build();
+ ASSERT_EQ(1U, s.size());
+ EXPECT_EQ(kArm64Add32, s[0]->arch_opcode());
+ EXPECT_EQ(kMode_Operand2_R_SXTB, s[0]->addressing_mode());
+ ASSERT_EQ(2U, s[0]->InputCount());
+ ASSERT_EQ(1U, s[0]->OutputCount());
+ }
+ {
+ StreamBuilder m(this, MachineType::Int64(), MachineType::Int32(),
+ MachineType::Int64());
+ m.Return(
+ m.Int64Add(m.Word32Sar(m.Word32Shl(m.Parameter(0), m.Int32Constant(24)),
+ m.Int32Constant(24)),
+ m.Parameter(1)));
+ Stream s = m.Build();
+ ASSERT_EQ(1U, s.size());
+ EXPECT_EQ(kArm64Add, s[0]->arch_opcode());
+ EXPECT_EQ(kMode_Operand2_R_SXTB, s[0]->addressing_mode());
+ ASSERT_EQ(2U, s[0]->InputCount());
+ ASSERT_EQ(1U, s[0]->OutputCount());
+ }
+}
+
+
+TEST_F(InstructionSelectorTest, AddSignedExtendHalfwordOnLeft) {
+ {
+ StreamBuilder m(this, MachineType::Int32(), MachineType::Int32(),
+ MachineType::Int32());
+ m.Return(
+ m.Int32Add(m.Word32Sar(m.Word32Shl(m.Parameter(0), m.Int32Constant(16)),
+ m.Int32Constant(16)),
+ m.Parameter(1)));
+ Stream s = m.Build();
+ ASSERT_EQ(1U, s.size());
+ EXPECT_EQ(kArm64Add32, s[0]->arch_opcode());
+ EXPECT_EQ(kMode_Operand2_R_SXTH, s[0]->addressing_mode());
+ ASSERT_EQ(2U, s[0]->InputCount());
+ ASSERT_EQ(1U, s[0]->OutputCount());
+ }
+ {
+ StreamBuilder m(this, MachineType::Int64(), MachineType::Int32(),
+ MachineType::Int64());
+ m.Return(
+ m.Int64Add(m.Word32Sar(m.Word32Shl(m.Parameter(0), m.Int32Constant(16)),
+ m.Int32Constant(16)),
+ m.Parameter(1)));
+ Stream s = m.Build();
+ ASSERT_EQ(1U, s.size());
+ EXPECT_EQ(kArm64Add, s[0]->arch_opcode());
+ EXPECT_EQ(kMode_Operand2_R_SXTH, s[0]->addressing_mode());
+ ASSERT_EQ(2U, s[0]->InputCount());
+ ASSERT_EQ(1U, s[0]->OutputCount());
+ }
+}
+
+
// -----------------------------------------------------------------------------
// Data processing controlled branches.
@@ -628,7 +924,7 @@
const MachInst2 dpi = GetParam();
const MachineType type = dpi.machine_type;
StreamBuilder m(this, type, type, type);
- MLabel a, b;
+ RawMachineLabel a, b;
m.Branch((m.*dpi.constructor)(m.Parameter(0), m.Parameter(1)), &a, &b);
m.Bind(&a);
m.Return(m.Int32Constant(1));
@@ -652,8 +948,8 @@
// Skip the cases where the instruction selector would use tbz/tbnz.
if (base::bits::CountPopulation32(imm) == 1) continue;
- StreamBuilder m(this, kMachInt32, kMachInt32);
- MLabel a, b;
+ StreamBuilder m(this, MachineType::Int32(), MachineType::Int32());
+ RawMachineLabel a, b;
m.Branch(m.Word32And(m.Parameter(0), m.Int32Constant(imm)), &a, &b);
m.Bind(&a);
m.Return(m.Int32Constant(1));
@@ -675,8 +971,8 @@
// Skip the cases where the instruction selector would use tbz/tbnz.
if (base::bits::CountPopulation64(imm) == 1) continue;
- StreamBuilder m(this, kMachInt64, kMachInt64);
- MLabel a, b;
+ StreamBuilder m(this, MachineType::Int64(), MachineType::Int64());
+ RawMachineLabel a, b;
m.Branch(m.Word64And(m.Parameter(0), m.Int64Constant(imm)), &a, &b);
m.Bind(&a);
m.Return(m.Int32Constant(1));
@@ -695,8 +991,8 @@
TEST_F(InstructionSelectorTest, AddBranchWithImmediateOnRight) {
TRACED_FOREACH(int32_t, imm, kAddSubImmediates) {
- StreamBuilder m(this, kMachInt32, kMachInt32);
- MLabel a, b;
+ StreamBuilder m(this, MachineType::Int32(), MachineType::Int32());
+ RawMachineLabel a, b;
m.Branch(m.Int32Add(m.Parameter(0), m.Int32Constant(imm)), &a, &b);
m.Bind(&a);
m.Return(m.Int32Constant(1));
@@ -713,8 +1009,8 @@
TEST_F(InstructionSelectorTest, SubBranchWithImmediateOnRight) {
TRACED_FOREACH(int32_t, imm, kAddSubImmediates) {
- StreamBuilder m(this, kMachInt32, kMachInt32);
- MLabel a, b;
+ StreamBuilder m(this, MachineType::Int32(), MachineType::Int32());
+ RawMachineLabel a, b;
m.Branch(m.Int32Sub(m.Parameter(0), m.Int32Constant(imm)), &a, &b);
m.Bind(&a);
m.Return(m.Int32Constant(1));
@@ -734,8 +1030,8 @@
// Skip the cases where the instruction selector would use tbz/tbnz.
if (base::bits::CountPopulation32(imm) == 1) continue;
- StreamBuilder m(this, kMachInt32, kMachInt32);
- MLabel a, b;
+ StreamBuilder m(this, MachineType::Int32(), MachineType::Int32());
+ RawMachineLabel a, b;
m.Branch(m.Word32And(m.Int32Constant(imm), m.Parameter(0)), &a, &b);
m.Bind(&a);
m.Return(m.Int32Constant(1));
@@ -758,8 +1054,8 @@
// Skip the cases where the instruction selector would use tbz/tbnz.
if (base::bits::CountPopulation64(imm) == 1) continue;
- StreamBuilder m(this, kMachInt64, kMachInt64);
- MLabel a, b;
+ StreamBuilder m(this, MachineType::Int64(), MachineType::Int64());
+ RawMachineLabel a, b;
m.Branch(m.Word64And(m.Int64Constant(imm), m.Parameter(0)), &a, &b);
m.Bind(&a);
m.Return(m.Int32Constant(1));
@@ -779,8 +1075,8 @@
TEST_F(InstructionSelectorTest, AddBranchWithImmediateOnLeft) {
TRACED_FOREACH(int32_t, imm, kAddSubImmediates) {
- StreamBuilder m(this, kMachInt32, kMachInt32);
- MLabel a, b;
+ StreamBuilder m(this, MachineType::Int32(), MachineType::Int32());
+ RawMachineLabel a, b;
m.Branch(m.Int32Add(m.Int32Constant(imm), m.Parameter(0)), &a, &b);
m.Bind(&a);
m.Return(m.Int32Constant(1));
@@ -799,8 +1095,8 @@
TEST_F(InstructionSelectorTest, Word32AndBranchWithOneBitMaskOnRight) {
TRACED_FORRANGE(int, bit, 0, 31) {
uint32_t mask = 1 << bit;
- StreamBuilder m(this, kMachInt32, kMachInt32);
- MLabel a, b;
+ StreamBuilder m(this, MachineType::Int32(), MachineType::Int32());
+ RawMachineLabel a, b;
m.Branch(m.Word32And(m.Parameter(0), m.Int32Constant(mask)), &a, &b);
m.Bind(&a);
m.Return(m.Int32Constant(1));
@@ -817,8 +1113,8 @@
TRACED_FORRANGE(int, bit, 0, 31) {
uint32_t mask = 1 << bit;
- StreamBuilder m(this, kMachInt32, kMachInt32);
- MLabel a, b;
+ StreamBuilder m(this, MachineType::Int32(), MachineType::Int32());
+ RawMachineLabel a, b;
m.Branch(
m.Word32BinaryNot(m.Word32And(m.Parameter(0), m.Int32Constant(mask))),
&a, &b);
@@ -840,8 +1136,8 @@
TEST_F(InstructionSelectorTest, Word32AndBranchWithOneBitMaskOnLeft) {
TRACED_FORRANGE(int, bit, 0, 31) {
uint32_t mask = 1 << bit;
- StreamBuilder m(this, kMachInt32, kMachInt32);
- MLabel a, b;
+ StreamBuilder m(this, MachineType::Int32(), MachineType::Int32());
+ RawMachineLabel a, b;
m.Branch(m.Word32And(m.Int32Constant(mask), m.Parameter(0)), &a, &b);
m.Bind(&a);
m.Return(m.Int32Constant(1));
@@ -858,8 +1154,8 @@
TRACED_FORRANGE(int, bit, 0, 31) {
uint32_t mask = 1 << bit;
- StreamBuilder m(this, kMachInt32, kMachInt32);
- MLabel a, b;
+ StreamBuilder m(this, MachineType::Int32(), MachineType::Int32());
+ RawMachineLabel a, b;
m.Branch(
m.Word32BinaryNot(m.Word32And(m.Int32Constant(mask), m.Parameter(0))),
&a, &b);
@@ -881,8 +1177,8 @@
TEST_F(InstructionSelectorTest, Word64AndBranchWithOneBitMaskOnRight) {
TRACED_FORRANGE(int, bit, 0, 63) {
uint64_t mask = 1L << bit;
- StreamBuilder m(this, kMachInt64, kMachInt64);
- MLabel a, b;
+ StreamBuilder m(this, MachineType::Int64(), MachineType::Int64());
+ RawMachineLabel a, b;
m.Branch(m.Word64And(m.Parameter(0), m.Int64Constant(mask)), &a, &b);
m.Bind(&a);
m.Return(m.Int32Constant(1));
@@ -896,34 +1192,14 @@
EXPECT_EQ(InstructionOperand::IMMEDIATE, s[0]->InputAt(1)->kind());
EXPECT_EQ(bit, s.ToInt64(s[0]->InputAt(1)));
}
-
- TRACED_FORRANGE(int, bit, 0, 63) {
- uint64_t mask = 1L << bit;
- StreamBuilder m(this, kMachInt64, kMachInt64);
- MLabel a, b;
- m.Branch(
- m.Word64BinaryNot(m.Word64And(m.Parameter(0), m.Int64Constant(mask))),
- &a, &b);
- m.Bind(&a);
- m.Return(m.Int32Constant(1));
- m.Bind(&b);
- m.Return(m.Int32Constant(0));
- Stream s = m.Build();
- ASSERT_EQ(1U, s.size());
- EXPECT_EQ(kArm64TestAndBranch, s[0]->arch_opcode());
- EXPECT_EQ(kEqual, s[0]->flags_condition());
- EXPECT_EQ(4U, s[0]->InputCount());
- EXPECT_EQ(InstructionOperand::IMMEDIATE, s[0]->InputAt(1)->kind());
- EXPECT_EQ(bit, s.ToInt64(s[0]->InputAt(1)));
- }
}
TEST_F(InstructionSelectorTest, Word64AndBranchWithOneBitMaskOnLeft) {
TRACED_FORRANGE(int, bit, 0, 63) {
uint64_t mask = 1L << bit;
- StreamBuilder m(this, kMachInt64, kMachInt64);
- MLabel a, b;
+ StreamBuilder m(this, MachineType::Int64(), MachineType::Int64());
+ RawMachineLabel a, b;
m.Branch(m.Word64And(m.Int64Constant(mask), m.Parameter(0)), &a, &b);
m.Bind(&a);
m.Return(m.Int32Constant(1));
@@ -937,33 +1213,13 @@
EXPECT_EQ(InstructionOperand::IMMEDIATE, s[0]->InputAt(1)->kind());
EXPECT_EQ(bit, s.ToInt64(s[0]->InputAt(1)));
}
-
- TRACED_FORRANGE(int, bit, 0, 63) {
- uint64_t mask = 1L << bit;
- StreamBuilder m(this, kMachInt64, kMachInt64);
- MLabel a, b;
- m.Branch(
- m.Word64BinaryNot(m.Word64And(m.Int64Constant(mask), m.Parameter(0))),
- &a, &b);
- m.Bind(&a);
- m.Return(m.Int32Constant(1));
- m.Bind(&b);
- m.Return(m.Int32Constant(0));
- Stream s = m.Build();
- ASSERT_EQ(1U, s.size());
- EXPECT_EQ(kArm64TestAndBranch, s[0]->arch_opcode());
- EXPECT_EQ(kEqual, s[0]->flags_condition());
- EXPECT_EQ(4U, s[0]->InputCount());
- EXPECT_EQ(InstructionOperand::IMMEDIATE, s[0]->InputAt(1)->kind());
- EXPECT_EQ(bit, s.ToInt64(s[0]->InputAt(1)));
- }
}
TEST_F(InstructionSelectorTest, CompareAgainstZeroAndBranch) {
{
- StreamBuilder m(this, kMachInt32, kMachInt32);
- MLabel a, b;
+ StreamBuilder m(this, MachineType::Int32(), MachineType::Int32());
+ RawMachineLabel a, b;
Node* p0 = m.Parameter(0);
m.Branch(p0, &a, &b);
m.Bind(&a);
@@ -979,8 +1235,8 @@
}
{
- StreamBuilder m(this, kMachInt32, kMachInt32);
- MLabel a, b;
+ StreamBuilder m(this, MachineType::Int32(), MachineType::Int32());
+ RawMachineLabel a, b;
Node* p0 = m.Parameter(0);
m.Branch(m.Word32BinaryNot(p0), &a, &b);
m.Bind(&a);
@@ -1112,7 +1368,7 @@
const MachInst2 dpi = GetParam();
const MachineType type = dpi.machine_type;
StreamBuilder m(this, type, type, type);
- MLabel a, b;
+ RawMachineLabel a, b;
Node* n = (m.*dpi.constructor)(m.Parameter(0), m.Parameter(1));
m.Branch(m.Projection(1, n), &a, &b);
m.Bind(&a);
@@ -1134,7 +1390,7 @@
const MachineType type = dpi.machine_type;
TRACED_FOREACH(int32_t, imm, kAddSubImmediates) {
StreamBuilder m(this, type, type);
- MLabel a, b;
+ RawMachineLabel a, b;
Node* n = (m.*dpi.constructor)(m.Parameter(0), m.Int32Constant(imm));
m.Branch(m.Projection(1, n), &a, &b);
m.Bind(&a);
@@ -1159,7 +1415,7 @@
TEST_F(InstructionSelectorTest, OvfFlagAddImmediateOnLeft) {
TRACED_FOREACH(int32_t, imm, kAddSubImmediates) {
- StreamBuilder m(this, kMachInt32, kMachInt32);
+ StreamBuilder m(this, MachineType::Int32(), MachineType::Int32());
m.Return(m.Projection(
1, m.Int32AddWithOverflow(m.Int32Constant(imm), m.Parameter(0))));
Stream s = m.Build();
@@ -1177,7 +1433,7 @@
TEST_F(InstructionSelectorTest, OvfValAddImmediateOnLeft) {
TRACED_FOREACH(int32_t, imm, kAddSubImmediates) {
- StreamBuilder m(this, kMachInt32, kMachInt32);
+ StreamBuilder m(this, MachineType::Int32(), MachineType::Int32());
m.Return(m.Projection(
0, m.Int32AddWithOverflow(m.Int32Constant(imm), m.Parameter(0))));
Stream s = m.Build();
@@ -1194,7 +1450,7 @@
TEST_F(InstructionSelectorTest, OvfBothAddImmediateOnLeft) {
TRACED_FOREACH(int32_t, imm, kAddSubImmediates) {
- StreamBuilder m(this, kMachInt32, kMachInt32);
+ StreamBuilder m(this, MachineType::Int32(), MachineType::Int32());
Node* n = m.Int32AddWithOverflow(m.Int32Constant(imm), m.Parameter(0));
m.Return(m.Word32Equal(m.Projection(0, n), m.Projection(1, n)));
Stream s = m.Build();
@@ -1212,8 +1468,8 @@
TEST_F(InstructionSelectorTest, OvfBranchWithImmediateOnLeft) {
TRACED_FOREACH(int32_t, imm, kAddSubImmediates) {
- StreamBuilder m(this, kMachInt32, kMachInt32);
- MLabel a, b;
+ StreamBuilder m(this, MachineType::Int32(), MachineType::Int32());
+ RawMachineLabel a, b;
Node* n = m.Int32AddWithOverflow(m.Int32Constant(imm), m.Parameter(0));
m.Branch(m.Projection(1, n), &a, &b);
m.Bind(&a);
@@ -1256,7 +1512,8 @@
TEST_P(InstructionSelectorShiftTest, Immediate) {
const Shift shift = GetParam();
const MachineType type = shift.mi.machine_type;
- TRACED_FORRANGE(int32_t, imm, 0, (ElementSizeOf(type) * 8) - 1) {
+ TRACED_FORRANGE(int32_t, imm, 0,
+ ((1 << ElementSizeLog2Of(type.representation())) * 8) - 1) {
StreamBuilder m(this, type, type);
m.Return((m.*shift.mi.constructor)(m.Parameter(0), m.Int32Constant(imm)));
Stream s = m.Build();
@@ -1276,7 +1533,7 @@
TEST_F(InstructionSelectorTest, Word64ShlWithChangeInt32ToInt64) {
TRACED_FORRANGE(int64_t, x, 32, 63) {
- StreamBuilder m(this, kMachInt64, kMachInt32);
+ StreamBuilder m(this, MachineType::Int64(), MachineType::Int32());
Node* const p0 = m.Parameter(0);
Node* const n = m.Word64Shl(m.ChangeInt32ToInt64(p0), m.Int64Constant(x));
m.Return(n);
@@ -1294,7 +1551,7 @@
TEST_F(InstructionSelectorTest, Word64ShlWithChangeUint32ToUint64) {
TRACED_FORRANGE(int64_t, x, 32, 63) {
- StreamBuilder m(this, kMachInt64, kMachUint32);
+ StreamBuilder m(this, MachineType::Int64(), MachineType::Uint32());
Node* const p0 = m.Parameter(0);
Node* const n = m.Word64Shl(m.ChangeUint32ToUint64(p0), m.Int64Constant(x));
m.Return(n);
@@ -1311,7 +1568,7 @@
TEST_F(InstructionSelectorTest, TruncateInt64ToInt32WithWord64Sar) {
- StreamBuilder m(this, kMachInt32, kMachInt64);
+ StreamBuilder m(this, MachineType::Int32(), MachineType::Int64());
Node* const p = m.Parameter(0);
Node* const t = m.TruncateInt64ToInt32(m.Word64Sar(p, m.Int64Constant(32)));
m.Return(t);
@@ -1328,7 +1585,7 @@
TEST_F(InstructionSelectorTest, TruncateInt64ToInt32WithWord64Shr) {
TRACED_FORRANGE(int64_t, x, 32, 63) {
- StreamBuilder m(this, kMachInt32, kMachInt64);
+ StreamBuilder m(this, MachineType::Int32(), MachineType::Int64());
Node* const p = m.Parameter(0);
Node* const t = m.TruncateInt64ToInt32(m.Word64Shr(p, m.Int64Constant(x)));
m.Return(t);
@@ -1393,10 +1650,10 @@
static const MulDPInst kMulDPInstructions[] = {
{"Int32Mul", &RawMachineAssembler::Int32Mul, &RawMachineAssembler::Int32Add,
&RawMachineAssembler::Int32Sub, kArm64Madd32, kArm64Msub32, kArm64Mneg32,
- kMachInt32},
+ MachineType::Int32()},
{"Int64Mul", &RawMachineAssembler::Int64Mul, &RawMachineAssembler::Int64Add,
&RawMachineAssembler::Int64Sub, kArm64Madd, kArm64Msub, kArm64Mneg,
- kMachInt64}};
+ MachineType::Int64()}};
typedef InstructionSelectorTestWithParam<MulDPInst>
@@ -1478,6 +1735,270 @@
::testing::ValuesIn(kMulDPInstructions));
+TEST_F(InstructionSelectorTest, Int32MulWithImmediate) {
+ // x * (2^k + 1) -> x + (x << k)
+ TRACED_FORRANGE(int32_t, k, 1, 30) {
+ StreamBuilder m(this, MachineType::Int32(), MachineType::Int32());
+ m.Return(m.Int32Mul(m.Parameter(0), m.Int32Constant((1 << k) + 1)));
+ Stream s = m.Build();
+ ASSERT_EQ(1U, s.size());
+ EXPECT_EQ(kArm64Add32, s[0]->arch_opcode());
+ EXPECT_EQ(kMode_Operand2_R_LSL_I, s[0]->addressing_mode());
+ ASSERT_EQ(3U, s[0]->InputCount());
+ EXPECT_EQ(s.ToVreg(s[0]->InputAt(0)), s.ToVreg(s[0]->InputAt(1)));
+ EXPECT_EQ(k, s.ToInt32(s[0]->InputAt(2)));
+ EXPECT_EQ(1U, s[0]->OutputCount());
+ }
+ // (2^k + 1) * x -> x + (x << k)
+ TRACED_FORRANGE(int32_t, k, 1, 30) {
+ StreamBuilder m(this, MachineType::Int32(), MachineType::Int32());
+ m.Return(m.Int32Mul(m.Int32Constant((1 << k) + 1), m.Parameter(0)));
+ Stream s = m.Build();
+ ASSERT_EQ(1U, s.size());
+ EXPECT_EQ(kArm64Add32, s[0]->arch_opcode());
+ EXPECT_EQ(kMode_Operand2_R_LSL_I, s[0]->addressing_mode());
+ ASSERT_EQ(3U, s[0]->InputCount());
+ EXPECT_EQ(s.ToVreg(s[0]->InputAt(0)), s.ToVreg(s[0]->InputAt(1)));
+ EXPECT_EQ(k, s.ToInt32(s[0]->InputAt(2)));
+ EXPECT_EQ(1U, s[0]->OutputCount());
+ }
+ // x * (2^k + 1) + c -> x + (x << k) + c
+ TRACED_FORRANGE(int32_t, k, 1, 30) {
+ StreamBuilder m(this, MachineType::Int32(), MachineType::Int32(),
+ MachineType::Int32());
+ m.Return(
+ m.Int32Add(m.Int32Mul(m.Parameter(0), m.Int32Constant((1 << k) + 1)),
+ m.Parameter(1)));
+ Stream s = m.Build();
+ ASSERT_EQ(2U, s.size());
+ EXPECT_EQ(kArm64Add32, s[0]->arch_opcode());
+ EXPECT_EQ(kArm64Add32, s[1]->arch_opcode());
+ EXPECT_EQ(kMode_Operand2_R_LSL_I, s[0]->addressing_mode());
+ ASSERT_EQ(3U, s[0]->InputCount());
+ EXPECT_EQ(s.ToVreg(s[0]->InputAt(0)), s.ToVreg(s[0]->InputAt(1)));
+ EXPECT_EQ(k, s.ToInt32(s[0]->InputAt(2)));
+ EXPECT_EQ(1U, s[0]->OutputCount());
+ }
+ // (2^k + 1) * x + c -> x + (x << k) + c
+ TRACED_FORRANGE(int32_t, k, 1, 30) {
+ StreamBuilder m(this, MachineType::Int32(), MachineType::Int32(),
+ MachineType::Int32());
+ m.Return(
+ m.Int32Add(m.Int32Mul(m.Int32Constant((1 << k) + 1), m.Parameter(0)),
+ m.Parameter(1)));
+ Stream s = m.Build();
+ ASSERT_EQ(2U, s.size());
+ EXPECT_EQ(kArm64Add32, s[0]->arch_opcode());
+ EXPECT_EQ(kArm64Add32, s[1]->arch_opcode());
+ EXPECT_EQ(kMode_Operand2_R_LSL_I, s[0]->addressing_mode());
+ ASSERT_EQ(3U, s[0]->InputCount());
+ EXPECT_EQ(s.ToVreg(s[0]->InputAt(0)), s.ToVreg(s[0]->InputAt(1)));
+ EXPECT_EQ(k, s.ToInt32(s[0]->InputAt(2)));
+ EXPECT_EQ(1U, s[0]->OutputCount());
+ }
+ // c + x * (2^k + 1) -> c + x + (x << k)
+ TRACED_FORRANGE(int32_t, k, 1, 30) {
+ StreamBuilder m(this, MachineType::Int32(), MachineType::Int32(),
+ MachineType::Int32());
+ m.Return(
+ m.Int32Add(m.Parameter(0),
+ m.Int32Mul(m.Parameter(1), m.Int32Constant((1 << k) + 1))));
+ Stream s = m.Build();
+ ASSERT_EQ(2U, s.size());
+ EXPECT_EQ(kArm64Add32, s[0]->arch_opcode());
+ EXPECT_EQ(kArm64Add32, s[1]->arch_opcode());
+ EXPECT_EQ(kMode_Operand2_R_LSL_I, s[0]->addressing_mode());
+ ASSERT_EQ(3U, s[0]->InputCount());
+ EXPECT_EQ(s.ToVreg(s[0]->InputAt(1)), s.ToVreg(s[0]->InputAt(1)));
+ EXPECT_EQ(k, s.ToInt32(s[0]->InputAt(2)));
+ EXPECT_EQ(1U, s[0]->OutputCount());
+ }
+ // c + (2^k + 1) * x -> c + x + (x << k)
+ TRACED_FORRANGE(int32_t, k, 1, 30) {
+ StreamBuilder m(this, MachineType::Int32(), MachineType::Int32(),
+ MachineType::Int32());
+ m.Return(
+ m.Int32Add(m.Parameter(0),
+ m.Int32Mul(m.Int32Constant((1 << k) + 1), m.Parameter(1))));
+ Stream s = m.Build();
+ ASSERT_EQ(2U, s.size());
+ EXPECT_EQ(kArm64Add32, s[0]->arch_opcode());
+ EXPECT_EQ(kArm64Add32, s[1]->arch_opcode());
+ EXPECT_EQ(kMode_Operand2_R_LSL_I, s[0]->addressing_mode());
+ ASSERT_EQ(3U, s[0]->InputCount());
+ EXPECT_EQ(s.ToVreg(s[0]->InputAt(1)), s.ToVreg(s[0]->InputAt(1)));
+ EXPECT_EQ(k, s.ToInt32(s[0]->InputAt(2)));
+ EXPECT_EQ(1U, s[0]->OutputCount());
+ }
+ // c - x * (2^k + 1) -> c - x + (x << k)
+ TRACED_FORRANGE(int32_t, k, 1, 30) {
+ StreamBuilder m(this, MachineType::Int32(), MachineType::Int32(),
+ MachineType::Int32());
+ m.Return(
+ m.Int32Sub(m.Parameter(0),
+ m.Int32Mul(m.Parameter(1), m.Int32Constant((1 << k) + 1))));
+ Stream s = m.Build();
+ ASSERT_EQ(2U, s.size());
+ EXPECT_EQ(kArm64Add32, s[0]->arch_opcode());
+ EXPECT_EQ(kArm64Sub32, s[1]->arch_opcode());
+ EXPECT_EQ(kMode_Operand2_R_LSL_I, s[0]->addressing_mode());
+ ASSERT_EQ(3U, s[0]->InputCount());
+ EXPECT_EQ(s.ToVreg(s[0]->InputAt(1)), s.ToVreg(s[0]->InputAt(1)));
+ EXPECT_EQ(k, s.ToInt32(s[0]->InputAt(2)));
+ EXPECT_EQ(1U, s[0]->OutputCount());
+ }
+ // c - (2^k + 1) * x -> c - x + (x << k)
+ TRACED_FORRANGE(int32_t, k, 1, 30) {
+ StreamBuilder m(this, MachineType::Int32(), MachineType::Int32(),
+ MachineType::Int32());
+ m.Return(
+ m.Int32Sub(m.Parameter(0),
+ m.Int32Mul(m.Int32Constant((1 << k) + 1), m.Parameter(1))));
+ Stream s = m.Build();
+ ASSERT_EQ(2U, s.size());
+ EXPECT_EQ(kArm64Add32, s[0]->arch_opcode());
+ EXPECT_EQ(kArm64Sub32, s[1]->arch_opcode());
+ EXPECT_EQ(kMode_Operand2_R_LSL_I, s[0]->addressing_mode());
+ ASSERT_EQ(3U, s[0]->InputCount());
+ EXPECT_EQ(s.ToVreg(s[0]->InputAt(1)), s.ToVreg(s[0]->InputAt(1)));
+ EXPECT_EQ(k, s.ToInt32(s[0]->InputAt(2)));
+ EXPECT_EQ(1U, s[0]->OutputCount());
+ }
+}
+
+
+TEST_F(InstructionSelectorTest, Int64MulWithImmediate) {
+ // x * (2^k + 1) -> x + (x << k)
+ TRACED_FORRANGE(int64_t, k, 1, 62) {
+ StreamBuilder m(this, MachineType::Int64(), MachineType::Int64());
+ m.Return(m.Int64Mul(m.Parameter(0), m.Int64Constant((1L << k) + 1)));
+ Stream s = m.Build();
+ ASSERT_EQ(1U, s.size());
+ EXPECT_EQ(kArm64Add, s[0]->arch_opcode());
+ EXPECT_EQ(kMode_Operand2_R_LSL_I, s[0]->addressing_mode());
+ ASSERT_EQ(3U, s[0]->InputCount());
+ EXPECT_EQ(s.ToVreg(s[0]->InputAt(0)), s.ToVreg(s[0]->InputAt(1)));
+ EXPECT_EQ(k, s.ToInt64(s[0]->InputAt(2)));
+ EXPECT_EQ(1U, s[0]->OutputCount());
+ }
+ // (2^k + 1) * x -> x + (x << k)
+ TRACED_FORRANGE(int64_t, k, 1, 62) {
+ StreamBuilder m(this, MachineType::Int64(), MachineType::Int64());
+ m.Return(m.Int64Mul(m.Int64Constant((1L << k) + 1), m.Parameter(0)));
+ Stream s = m.Build();
+ ASSERT_EQ(1U, s.size());
+ EXPECT_EQ(kArm64Add, s[0]->arch_opcode());
+ EXPECT_EQ(kMode_Operand2_R_LSL_I, s[0]->addressing_mode());
+ ASSERT_EQ(3U, s[0]->InputCount());
+ EXPECT_EQ(s.ToVreg(s[0]->InputAt(0)), s.ToVreg(s[0]->InputAt(1)));
+ EXPECT_EQ(k, s.ToInt64(s[0]->InputAt(2)));
+ EXPECT_EQ(1U, s[0]->OutputCount());
+ }
+ // x * (2^k + 1) + c -> x + (x << k) + c
+ TRACED_FORRANGE(int64_t, k, 1, 62) {
+ StreamBuilder m(this, MachineType::Int64(), MachineType::Int64(),
+ MachineType::Int64());
+ m.Return(
+ m.Int64Add(m.Int64Mul(m.Parameter(0), m.Int64Constant((1L << k) + 1)),
+ m.Parameter(1)));
+ Stream s = m.Build();
+ ASSERT_EQ(2U, s.size());
+ EXPECT_EQ(kArm64Add, s[0]->arch_opcode());
+ EXPECT_EQ(kArm64Add, s[1]->arch_opcode());
+ EXPECT_EQ(kMode_Operand2_R_LSL_I, s[0]->addressing_mode());
+ ASSERT_EQ(3U, s[0]->InputCount());
+ EXPECT_EQ(s.ToVreg(s[0]->InputAt(0)), s.ToVreg(s[0]->InputAt(1)));
+ EXPECT_EQ(k, s.ToInt64(s[0]->InputAt(2)));
+ EXPECT_EQ(1U, s[0]->OutputCount());
+ }
+ // (2^k + 1) * x + c -> x + (x << k) + c
+ TRACED_FORRANGE(int64_t, k, 1, 62) {
+ StreamBuilder m(this, MachineType::Int64(), MachineType::Int64(),
+ MachineType::Int64());
+ m.Return(
+ m.Int64Add(m.Int64Mul(m.Int64Constant((1L << k) + 1), m.Parameter(0)),
+ m.Parameter(1)));
+ Stream s = m.Build();
+ ASSERT_EQ(2U, s.size());
+ EXPECT_EQ(kArm64Add, s[0]->arch_opcode());
+ EXPECT_EQ(kArm64Add, s[1]->arch_opcode());
+ EXPECT_EQ(kMode_Operand2_R_LSL_I, s[0]->addressing_mode());
+ ASSERT_EQ(3U, s[0]->InputCount());
+ EXPECT_EQ(s.ToVreg(s[0]->InputAt(0)), s.ToVreg(s[0]->InputAt(1)));
+ EXPECT_EQ(k, s.ToInt64(s[0]->InputAt(2)));
+ EXPECT_EQ(1U, s[0]->OutputCount());
+ }
+ // c + x * (2^k + 1) -> c + x + (x << k)
+ TRACED_FORRANGE(int64_t, k, 1, 62) {
+ StreamBuilder m(this, MachineType::Int64(), MachineType::Int64(),
+ MachineType::Int64());
+ m.Return(
+ m.Int64Add(m.Parameter(0),
+ m.Int64Mul(m.Parameter(1), m.Int64Constant((1L << k) + 1))));
+ Stream s = m.Build();
+ ASSERT_EQ(2U, s.size());
+ EXPECT_EQ(kArm64Add, s[0]->arch_opcode());
+ EXPECT_EQ(kArm64Add, s[1]->arch_opcode());
+ EXPECT_EQ(kMode_Operand2_R_LSL_I, s[0]->addressing_mode());
+ ASSERT_EQ(3U, s[0]->InputCount());
+ EXPECT_EQ(s.ToVreg(s[0]->InputAt(0)), s.ToVreg(s[0]->InputAt(1)));
+ EXPECT_EQ(k, s.ToInt64(s[0]->InputAt(2)));
+ EXPECT_EQ(1U, s[0]->OutputCount());
+ }
+ // c + (2^k + 1) * x -> c + x + (x << k)
+ TRACED_FORRANGE(int64_t, k, 1, 62) {
+ StreamBuilder m(this, MachineType::Int64(), MachineType::Int64(),
+ MachineType::Int64());
+ m.Return(
+ m.Int64Add(m.Parameter(0),
+ m.Int64Mul(m.Int64Constant((1L << k) + 1), m.Parameter(1))));
+ Stream s = m.Build();
+ ASSERT_EQ(2U, s.size());
+ EXPECT_EQ(kArm64Add, s[0]->arch_opcode());
+ EXPECT_EQ(kArm64Add, s[1]->arch_opcode());
+ EXPECT_EQ(kMode_Operand2_R_LSL_I, s[0]->addressing_mode());
+ ASSERT_EQ(3U, s[0]->InputCount());
+ EXPECT_EQ(s.ToVreg(s[0]->InputAt(0)), s.ToVreg(s[0]->InputAt(1)));
+ EXPECT_EQ(k, s.ToInt64(s[0]->InputAt(2)));
+ EXPECT_EQ(1U, s[0]->OutputCount());
+ }
+ // c - x * (2^k + 1) -> c - x + (x << k)
+ TRACED_FORRANGE(int64_t, k, 1, 62) {
+ StreamBuilder m(this, MachineType::Int64(), MachineType::Int64(),
+ MachineType::Int64());
+ m.Return(
+ m.Int64Sub(m.Parameter(0),
+ m.Int64Mul(m.Parameter(1), m.Int64Constant((1L << k) + 1))));
+ Stream s = m.Build();
+ ASSERT_EQ(2U, s.size());
+ EXPECT_EQ(kArm64Add, s[0]->arch_opcode());
+ EXPECT_EQ(kArm64Sub, s[1]->arch_opcode());
+ EXPECT_EQ(kMode_Operand2_R_LSL_I, s[0]->addressing_mode());
+ ASSERT_EQ(3U, s[0]->InputCount());
+ EXPECT_EQ(s.ToVreg(s[0]->InputAt(0)), s.ToVreg(s[0]->InputAt(1)));
+ EXPECT_EQ(k, s.ToInt64(s[0]->InputAt(2)));
+ EXPECT_EQ(1U, s[0]->OutputCount());
+ }
+ // c - (2^k + 1) * x -> c - x + (x << k)
+ TRACED_FORRANGE(int64_t, k, 1, 62) {
+ StreamBuilder m(this, MachineType::Int64(), MachineType::Int64(),
+ MachineType::Int64());
+ m.Return(
+ m.Int64Sub(m.Parameter(0),
+ m.Int64Mul(m.Int64Constant((1L << k) + 1), m.Parameter(1))));
+ Stream s = m.Build();
+ ASSERT_EQ(2U, s.size());
+ EXPECT_EQ(kArm64Add, s[0]->arch_opcode());
+ EXPECT_EQ(kArm64Sub, s[1]->arch_opcode());
+ EXPECT_EQ(kMode_Operand2_R_LSL_I, s[0]->addressing_mode());
+ ASSERT_EQ(3U, s[0]->InputCount());
+ EXPECT_EQ(s.ToVreg(s[0]->InputAt(0)), s.ToVreg(s[0]->InputAt(1)));
+ EXPECT_EQ(k, s.ToInt64(s[0]->InputAt(2)));
+ EXPECT_EQ(1U, s[0]->OutputCount());
+ }
+}
+
+
// -----------------------------------------------------------------------------
// Floating point instructions.
@@ -1506,7 +2027,8 @@
TEST_P(InstructionSelectorFPCmpTest, Parameter) {
const FPCmp cmp = GetParam();
- StreamBuilder m(this, kMachInt32, cmp.mi.machine_type, cmp.mi.machine_type);
+ StreamBuilder m(this, MachineType::Int32(), cmp.mi.machine_type,
+ cmp.mi.machine_type);
m.Return((m.*cmp.mi.constructor)(m.Parameter(0), m.Parameter(1)));
Stream s = m.Build();
ASSERT_EQ(1U, s.size());
@@ -1518,6 +2040,44 @@
}
+TEST_P(InstructionSelectorFPCmpTest, WithImmediateZeroOnRight) {
+ const FPCmp cmp = GetParam();
+ StreamBuilder m(this, MachineType::Int32(), cmp.mi.machine_type);
+ if (cmp.mi.machine_type == MachineType::Float64()) {
+ m.Return((m.*cmp.mi.constructor)(m.Parameter(0), m.Float64Constant(0.0)));
+ } else {
+ m.Return((m.*cmp.mi.constructor)(m.Parameter(0), m.Float32Constant(0.0f)));
+ }
+ Stream s = m.Build();
+ ASSERT_EQ(1U, s.size());
+ EXPECT_EQ(cmp.mi.arch_opcode, s[0]->arch_opcode());
+ EXPECT_EQ(2U, s[0]->InputCount());
+ EXPECT_TRUE(s[0]->InputAt(1)->IsImmediate());
+ EXPECT_EQ(1U, s[0]->OutputCount());
+ EXPECT_EQ(kFlags_set, s[0]->flags_mode());
+ EXPECT_EQ(cmp.cond, s[0]->flags_condition());
+}
+
+
+TEST_P(InstructionSelectorFPCmpTest, WithImmediateZeroOnLeft) {
+ const FPCmp cmp = GetParam();
+ StreamBuilder m(this, MachineType::Int32(), cmp.mi.machine_type);
+ if (cmp.mi.machine_type == MachineType::Float64()) {
+ m.Return((m.*cmp.mi.constructor)(m.Float64Constant(0.0), m.Parameter(0)));
+ } else {
+ m.Return((m.*cmp.mi.constructor)(m.Float32Constant(0.0f), m.Parameter(0)));
+ }
+ Stream s = m.Build();
+ ASSERT_EQ(1U, s.size());
+ EXPECT_EQ(cmp.mi.arch_opcode, s[0]->arch_opcode());
+ EXPECT_EQ(2U, s[0]->InputCount());
+ EXPECT_TRUE(s[0]->InputAt(1)->IsImmediate());
+ EXPECT_EQ(1U, s[0]->OutputCount());
+ EXPECT_EQ(kFlags_set, s[0]->flags_mode());
+ EXPECT_EQ(cmp.commuted_cond, s[0]->flags_condition());
+}
+
+
INSTANTIATE_TEST_CASE_P(InstructionSelectorTest, InstructionSelectorFPCmpTest,
::testing::ValuesIn(kFPCmpInstructions));
@@ -1568,52 +2128,52 @@
static const MemoryAccess kMemoryAccesses[] = {
- {kMachInt8,
+ {MachineType::Int8(),
kArm64Ldrsb,
kArm64Strb,
{-256, -255, -3, -2, -1, 0, 1, 2, 3, 255, 256, 257, 258, 1000, 1001, 2121,
2442, 4093, 4094, 4095}},
- {kMachUint8,
+ {MachineType::Uint8(),
kArm64Ldrb,
kArm64Strb,
{-256, -255, -3, -2, -1, 0, 1, 2, 3, 255, 256, 257, 258, 1000, 1001, 2121,
2442, 4093, 4094, 4095}},
- {kMachInt16,
+ {MachineType::Int16(),
kArm64Ldrsh,
kArm64Strh,
{-256, -255, -3, -2, -1, 0, 1, 2, 3, 255, 256, 258, 260, 4096, 4098, 4100,
4242, 6786, 8188, 8190}},
- {kMachUint16,
+ {MachineType::Uint16(),
kArm64Ldrh,
kArm64Strh,
{-256, -255, -3, -2, -1, 0, 1, 2, 3, 255, 256, 258, 260, 4096, 4098, 4100,
4242, 6786, 8188, 8190}},
- {kMachInt32,
+ {MachineType::Int32(),
kArm64LdrW,
kArm64StrW,
{-256, -255, -3, -2, -1, 0, 1, 2, 3, 255, 256, 260, 4096, 4100, 8192, 8196,
3276, 3280, 16376, 16380}},
- {kMachUint32,
+ {MachineType::Uint32(),
kArm64LdrW,
kArm64StrW,
{-256, -255, -3, -2, -1, 0, 1, 2, 3, 255, 256, 260, 4096, 4100, 8192, 8196,
3276, 3280, 16376, 16380}},
- {kMachInt64,
+ {MachineType::Int64(),
kArm64Ldr,
kArm64Str,
{-256, -255, -3, -2, -1, 0, 1, 2, 3, 255, 256, 264, 4096, 4104, 8192, 8200,
16384, 16392, 32752, 32760}},
- {kMachUint64,
+ {MachineType::Uint64(),
kArm64Ldr,
kArm64Str,
{-256, -255, -3, -2, -1, 0, 1, 2, 3, 255, 256, 264, 4096, 4104, 8192, 8200,
16384, 16392, 32752, 32760}},
- {kMachFloat32,
+ {MachineType::Float32(),
kArm64LdrS,
kArm64StrS,
{-256, -255, -3, -2, -1, 0, 1, 2, 3, 255, 256, 260, 4096, 4100, 8192, 8196,
3276, 3280, 16376, 16380}},
- {kMachFloat64,
+ {MachineType::Float64(),
kArm64LdrD,
kArm64StrD,
{-256, -255, -3, -2, -1, 0, 1, 2, 3, 255, 256, 264, 4096, 4104, 8192, 8200,
@@ -1626,7 +2186,8 @@
TEST_P(InstructionSelectorMemoryAccessTest, LoadWithParameters) {
const MemoryAccess memacc = GetParam();
- StreamBuilder m(this, memacc.type, kMachPtr, kMachInt32);
+ StreamBuilder m(this, memacc.type, MachineType::Pointer(),
+ MachineType::Int32());
m.Return(m.Load(memacc.type, m.Parameter(0), m.Parameter(1)));
Stream s = m.Build();
ASSERT_EQ(1U, s.size());
@@ -1640,7 +2201,7 @@
TEST_P(InstructionSelectorMemoryAccessTest, LoadWithImmediateIndex) {
const MemoryAccess memacc = GetParam();
TRACED_FOREACH(int32_t, index, memacc.immediates) {
- StreamBuilder m(this, memacc.type, kMachPtr);
+ StreamBuilder m(this, memacc.type, MachineType::Pointer());
m.Return(m.Load(memacc.type, m.Parameter(0), m.Int32Constant(index)));
Stream s = m.Build();
ASSERT_EQ(1U, s.size());
@@ -1656,8 +2217,10 @@
TEST_P(InstructionSelectorMemoryAccessTest, StoreWithParameters) {
const MemoryAccess memacc = GetParam();
- StreamBuilder m(this, kMachInt32, kMachPtr, kMachInt32, memacc.type);
- m.Store(memacc.type, m.Parameter(0), m.Parameter(1), m.Parameter(2));
+ StreamBuilder m(this, MachineType::Int32(), MachineType::Pointer(),
+ MachineType::Int32(), memacc.type);
+ m.Store(memacc.type.representation(), m.Parameter(0), m.Parameter(1),
+ m.Parameter(2), kNoWriteBarrier);
m.Return(m.Int32Constant(0));
Stream s = m.Build();
ASSERT_EQ(1U, s.size());
@@ -1671,9 +2234,10 @@
TEST_P(InstructionSelectorMemoryAccessTest, StoreWithImmediateIndex) {
const MemoryAccess memacc = GetParam();
TRACED_FOREACH(int32_t, index, memacc.immediates) {
- StreamBuilder m(this, kMachInt32, kMachPtr, memacc.type);
- m.Store(memacc.type, m.Parameter(0), m.Int32Constant(index),
- m.Parameter(1));
+ StreamBuilder m(this, MachineType::Int32(), MachineType::Pointer(),
+ memacc.type);
+ m.Store(memacc.type.representation(), m.Parameter(0),
+ m.Int32Constant(index), m.Parameter(1), kNoWriteBarrier);
m.Return(m.Int32Constant(0));
Stream s = m.Build();
ASSERT_EQ(1U, s.size());
@@ -1696,8 +2260,10 @@
// Comparison instructions.
static const MachInst2 kComparisonInstructions[] = {
- {&RawMachineAssembler::Word32Equal, "Word32Equal", kArm64Cmp32, kMachInt32},
- {&RawMachineAssembler::Word64Equal, "Word64Equal", kArm64Cmp, kMachInt64},
+ {&RawMachineAssembler::Word32Equal, "Word32Equal", kArm64Cmp32,
+ MachineType::Int32()},
+ {&RawMachineAssembler::Word64Equal, "Word64Equal", kArm64Cmp,
+ MachineType::Int64()},
};
@@ -1762,7 +2328,7 @@
TEST_F(InstructionSelectorTest, Word32EqualWithZero) {
{
- StreamBuilder m(this, kMachInt32, kMachInt32);
+ StreamBuilder m(this, MachineType::Int32(), MachineType::Int32());
m.Return(m.Word32Equal(m.Parameter(0), m.Int32Constant(0)));
Stream s = m.Build();
ASSERT_EQ(1U, s.size());
@@ -1774,7 +2340,7 @@
EXPECT_EQ(kEqual, s[0]->flags_condition());
}
{
- StreamBuilder m(this, kMachInt32, kMachInt32);
+ StreamBuilder m(this, MachineType::Int32(), MachineType::Int32());
m.Return(m.Word32Equal(m.Int32Constant(0), m.Parameter(0)));
Stream s = m.Build();
ASSERT_EQ(1U, s.size());
@@ -1790,7 +2356,7 @@
TEST_F(InstructionSelectorTest, Word64EqualWithZero) {
{
- StreamBuilder m(this, kMachInt64, kMachInt64);
+ StreamBuilder m(this, MachineType::Int64(), MachineType::Int64());
m.Return(m.Word64Equal(m.Parameter(0), m.Int64Constant(0)));
Stream s = m.Build();
ASSERT_EQ(1U, s.size());
@@ -1802,7 +2368,7 @@
EXPECT_EQ(kEqual, s[0]->flags_condition());
}
{
- StreamBuilder m(this, kMachInt64, kMachInt64);
+ StreamBuilder m(this, MachineType::Int64(), MachineType::Int64());
m.Return(m.Word64Equal(m.Int64Constant(0), m.Parameter(0)));
Stream s = m.Build();
ASSERT_EQ(1U, s.size());
@@ -1816,17 +2382,319 @@
}
+TEST_F(InstructionSelectorTest, Word32EqualWithWord32Shift) {
+ TRACED_FOREACH(Shift, shift, kShiftInstructions) {
+ // Skip non 32-bit shifts or ror operations.
+ if (shift.mi.machine_type != MachineType::Int32() ||
+ shift.mi.arch_opcode == kArm64Ror32) {
+ continue;
+ }
+
+ TRACED_FORRANGE(int32_t, imm, -32, 63) {
+ StreamBuilder m(this, MachineType::Int32(), MachineType::Int32(),
+ MachineType::Int32());
+ Node* const p0 = m.Parameter(0);
+ Node* const p1 = m.Parameter(1);
+ Node* r = (m.*shift.mi.constructor)(p1, m.Int32Constant(imm));
+ m.Return(m.Word32Equal(p0, r));
+ Stream s = m.Build();
+ ASSERT_EQ(1U, s.size());
+ EXPECT_EQ(kArm64Cmp32, s[0]->arch_opcode());
+ EXPECT_EQ(shift.mode, s[0]->addressing_mode());
+ ASSERT_EQ(3U, s[0]->InputCount());
+ EXPECT_EQ(s.ToVreg(p0), s.ToVreg(s[0]->InputAt(0)));
+ EXPECT_EQ(s.ToVreg(p1), s.ToVreg(s[0]->InputAt(1)));
+ EXPECT_EQ(imm, s.ToInt32(s[0]->InputAt(2)));
+ ASSERT_EQ(1U, s[0]->OutputCount());
+ }
+ TRACED_FORRANGE(int32_t, imm, -32, 63) {
+ StreamBuilder m(this, MachineType::Int32(), MachineType::Int32(),
+ MachineType::Int32());
+ Node* const p0 = m.Parameter(0);
+ Node* const p1 = m.Parameter(1);
+ Node* r = (m.*shift.mi.constructor)(p1, m.Int32Constant(imm));
+ m.Return(m.Word32Equal(r, p0));
+ Stream s = m.Build();
+ ASSERT_EQ(1U, s.size());
+ EXPECT_EQ(kArm64Cmp32, s[0]->arch_opcode());
+ EXPECT_EQ(shift.mode, s[0]->addressing_mode());
+ ASSERT_EQ(3U, s[0]->InputCount());
+ EXPECT_EQ(s.ToVreg(p0), s.ToVreg(s[0]->InputAt(0)));
+ EXPECT_EQ(s.ToVreg(p1), s.ToVreg(s[0]->InputAt(1)));
+ EXPECT_EQ(imm, s.ToInt32(s[0]->InputAt(2)));
+ ASSERT_EQ(1U, s[0]->OutputCount());
+ }
+ }
+}
+
+
+TEST_F(InstructionSelectorTest, Word32EqualWithUnsignedExtendByte) {
+ {
+ StreamBuilder m(this, MachineType::Int32(), MachineType::Int32(),
+ MachineType::Int32());
+ Node* const p0 = m.Parameter(0);
+ Node* const p1 = m.Parameter(1);
+ Node* r = m.Word32And(p1, m.Int32Constant(0xff));
+ m.Return(m.Word32Equal(p0, r));
+ Stream s = m.Build();
+ ASSERT_EQ(1U, s.size());
+ EXPECT_EQ(kArm64Cmp32, s[0]->arch_opcode());
+ EXPECT_EQ(kMode_Operand2_R_UXTB, s[0]->addressing_mode());
+ ASSERT_EQ(2U, s[0]->InputCount());
+ EXPECT_EQ(s.ToVreg(p0), s.ToVreg(s[0]->InputAt(0)));
+ EXPECT_EQ(s.ToVreg(p1), s.ToVreg(s[0]->InputAt(1)));
+ ASSERT_EQ(1U, s[0]->OutputCount());
+ }
+ {
+ StreamBuilder m(this, MachineType::Int32(), MachineType::Int32(),
+ MachineType::Int32());
+ Node* const p0 = m.Parameter(0);
+ Node* const p1 = m.Parameter(1);
+ Node* r = m.Word32And(p1, m.Int32Constant(0xff));
+ m.Return(m.Word32Equal(r, p0));
+ Stream s = m.Build();
+ ASSERT_EQ(1U, s.size());
+ EXPECT_EQ(kArm64Cmp32, s[0]->arch_opcode());
+ EXPECT_EQ(kMode_Operand2_R_UXTB, s[0]->addressing_mode());
+ ASSERT_EQ(2U, s[0]->InputCount());
+ EXPECT_EQ(s.ToVreg(p0), s.ToVreg(s[0]->InputAt(0)));
+ EXPECT_EQ(s.ToVreg(p1), s.ToVreg(s[0]->InputAt(1)));
+ ASSERT_EQ(1U, s[0]->OutputCount());
+ }
+}
+
+
+TEST_F(InstructionSelectorTest, Word32EqualWithUnsignedExtendHalfword) {
+ {
+ StreamBuilder m(this, MachineType::Int32(), MachineType::Int32(),
+ MachineType::Int32());
+ Node* const p0 = m.Parameter(0);
+ Node* const p1 = m.Parameter(1);
+ Node* r = m.Word32And(p1, m.Int32Constant(0xffff));
+ m.Return(m.Word32Equal(p0, r));
+ Stream s = m.Build();
+ ASSERT_EQ(1U, s.size());
+ EXPECT_EQ(kArm64Cmp32, s[0]->arch_opcode());
+ EXPECT_EQ(kMode_Operand2_R_UXTH, s[0]->addressing_mode());
+ ASSERT_EQ(2U, s[0]->InputCount());
+ EXPECT_EQ(s.ToVreg(p0), s.ToVreg(s[0]->InputAt(0)));
+ EXPECT_EQ(s.ToVreg(p1), s.ToVreg(s[0]->InputAt(1)));
+ ASSERT_EQ(1U, s[0]->OutputCount());
+ }
+ {
+ StreamBuilder m(this, MachineType::Int32(), MachineType::Int32(),
+ MachineType::Int32());
+ Node* const p0 = m.Parameter(0);
+ Node* const p1 = m.Parameter(1);
+ Node* r = m.Word32And(p1, m.Int32Constant(0xffff));
+ m.Return(m.Word32Equal(r, p0));
+ Stream s = m.Build();
+ ASSERT_EQ(1U, s.size());
+ EXPECT_EQ(kArm64Cmp32, s[0]->arch_opcode());
+ EXPECT_EQ(kMode_Operand2_R_UXTH, s[0]->addressing_mode());
+ ASSERT_EQ(2U, s[0]->InputCount());
+ EXPECT_EQ(s.ToVreg(p0), s.ToVreg(s[0]->InputAt(0)));
+ EXPECT_EQ(s.ToVreg(p1), s.ToVreg(s[0]->InputAt(1)));
+ ASSERT_EQ(1U, s[0]->OutputCount());
+ }
+}
+
+
+TEST_F(InstructionSelectorTest, Word32EqualWithSignedExtendByte) {
+ {
+ StreamBuilder m(this, MachineType::Int32(), MachineType::Int32(),
+ MachineType::Int32());
+ Node* const p0 = m.Parameter(0);
+ Node* const p1 = m.Parameter(1);
+ Node* r =
+ m.Word32Sar(m.Word32Shl(p1, m.Int32Constant(24)), m.Int32Constant(24));
+ m.Return(m.Word32Equal(p0, r));
+ Stream s = m.Build();
+ ASSERT_EQ(1U, s.size());
+ EXPECT_EQ(kArm64Cmp32, s[0]->arch_opcode());
+ EXPECT_EQ(kMode_Operand2_R_SXTB, s[0]->addressing_mode());
+ ASSERT_EQ(2U, s[0]->InputCount());
+ EXPECT_EQ(s.ToVreg(p0), s.ToVreg(s[0]->InputAt(0)));
+ EXPECT_EQ(s.ToVreg(p1), s.ToVreg(s[0]->InputAt(1)));
+ ASSERT_EQ(1U, s[0]->OutputCount());
+ }
+ {
+ StreamBuilder m(this, MachineType::Int32(), MachineType::Int32(),
+ MachineType::Int32());
+ Node* const p0 = m.Parameter(0);
+ Node* const p1 = m.Parameter(1);
+ Node* r =
+ m.Word32Sar(m.Word32Shl(p1, m.Int32Constant(24)), m.Int32Constant(24));
+ m.Return(m.Word32Equal(r, p0));
+ Stream s = m.Build();
+ ASSERT_EQ(1U, s.size());
+ EXPECT_EQ(kArm64Cmp32, s[0]->arch_opcode());
+ EXPECT_EQ(kMode_Operand2_R_SXTB, s[0]->addressing_mode());
+ ASSERT_EQ(2U, s[0]->InputCount());
+ EXPECT_EQ(s.ToVreg(p0), s.ToVreg(s[0]->InputAt(0)));
+ EXPECT_EQ(s.ToVreg(p1), s.ToVreg(s[0]->InputAt(1)));
+ ASSERT_EQ(1U, s[0]->OutputCount());
+ }
+}
+
+
+TEST_F(InstructionSelectorTest, Word32EqualWithSignedExtendHalfword) {
+ {
+ StreamBuilder m(this, MachineType::Int32(), MachineType::Int32(),
+ MachineType::Int32());
+ Node* const p0 = m.Parameter(0);
+ Node* const p1 = m.Parameter(1);
+ Node* r =
+ m.Word32Sar(m.Word32Shl(p1, m.Int32Constant(16)), m.Int32Constant(16));
+ m.Return(m.Word32Equal(p0, r));
+ Stream s = m.Build();
+ ASSERT_EQ(1U, s.size());
+ EXPECT_EQ(kArm64Cmp32, s[0]->arch_opcode());
+ EXPECT_EQ(kMode_Operand2_R_SXTH, s[0]->addressing_mode());
+ ASSERT_EQ(2U, s[0]->InputCount());
+ EXPECT_EQ(s.ToVreg(p0), s.ToVreg(s[0]->InputAt(0)));
+ EXPECT_EQ(s.ToVreg(p1), s.ToVreg(s[0]->InputAt(1)));
+ ASSERT_EQ(1U, s[0]->OutputCount());
+ }
+ {
+ StreamBuilder m(this, MachineType::Int32(), MachineType::Int32(),
+ MachineType::Int32());
+ Node* const p0 = m.Parameter(0);
+ Node* const p1 = m.Parameter(1);
+ Node* r =
+ m.Word32Sar(m.Word32Shl(p1, m.Int32Constant(16)), m.Int32Constant(16));
+ m.Return(m.Word32Equal(r, p0));
+ Stream s = m.Build();
+ ASSERT_EQ(1U, s.size());
+ EXPECT_EQ(kArm64Cmp32, s[0]->arch_opcode());
+ EXPECT_EQ(kMode_Operand2_R_SXTH, s[0]->addressing_mode());
+ ASSERT_EQ(2U, s[0]->InputCount());
+ EXPECT_EQ(s.ToVreg(p0), s.ToVreg(s[0]->InputAt(0)));
+ EXPECT_EQ(s.ToVreg(p1), s.ToVreg(s[0]->InputAt(1)));
+ ASSERT_EQ(1U, s[0]->OutputCount());
+ }
+}
+
+
+TEST_F(InstructionSelectorTest, Word32EqualZeroWithWord32Equal) {
+ {
+ StreamBuilder m(this, MachineType::Int32(), MachineType::Int32(),
+ MachineType::Int32());
+ Node* const p0 = m.Parameter(0);
+ Node* const p1 = m.Parameter(1);
+ m.Return(m.Word32Equal(m.Word32Equal(p0, p1), m.Int32Constant(0)));
+ Stream s = m.Build();
+ ASSERT_EQ(1U, s.size());
+ EXPECT_EQ(kArm64Cmp32, s[0]->arch_opcode());
+ ASSERT_EQ(2U, s[0]->InputCount());
+ EXPECT_EQ(s.ToVreg(p0), s.ToVreg(s[0]->InputAt(0)));
+ EXPECT_EQ(s.ToVreg(p1), s.ToVreg(s[0]->InputAt(1)));
+ EXPECT_EQ(1U, s[0]->OutputCount());
+ EXPECT_EQ(kFlags_set, s[0]->flags_mode());
+ EXPECT_EQ(kNotEqual, s[0]->flags_condition());
+ }
+ {
+ StreamBuilder m(this, MachineType::Int32(), MachineType::Int32(),
+ MachineType::Int32());
+ Node* const p0 = m.Parameter(0);
+ Node* const p1 = m.Parameter(1);
+ m.Return(m.Word32Equal(m.Int32Constant(0), m.Word32Equal(p0, p1)));
+ Stream s = m.Build();
+ ASSERT_EQ(1U, s.size());
+ EXPECT_EQ(kArm64Cmp32, s[0]->arch_opcode());
+ ASSERT_EQ(2U, s[0]->InputCount());
+ EXPECT_EQ(s.ToVreg(p0), s.ToVreg(s[0]->InputAt(0)));
+ EXPECT_EQ(s.ToVreg(p1), s.ToVreg(s[0]->InputAt(1)));
+ EXPECT_EQ(1U, s[0]->OutputCount());
+ EXPECT_EQ(kFlags_set, s[0]->flags_mode());
+ EXPECT_EQ(kNotEqual, s[0]->flags_condition());
+ }
+}
+
+namespace {
+
+struct IntegerCmp {
+ MachInst2 mi;
+ FlagsCondition cond;
+};
+
+
+std::ostream& operator<<(std::ostream& os, const IntegerCmp& cmp) {
+ return os << cmp.mi;
+}
+
+
+// ARM64 32-bit integer comparison instructions.
+const IntegerCmp kIntegerCmpInstructions[] = {
+ {{&RawMachineAssembler::Word32Equal, "Word32Equal", kArm64Cmp32,
+ MachineType::Int32()},
+ kEqual},
+ {{&RawMachineAssembler::Int32LessThan, "Int32LessThan", kArm64Cmp32,
+ MachineType::Int32()},
+ kSignedLessThan},
+ {{&RawMachineAssembler::Int32LessThanOrEqual, "Int32LessThanOrEqual",
+ kArm64Cmp32, MachineType::Int32()},
+ kSignedLessThanOrEqual},
+ {{&RawMachineAssembler::Uint32LessThan, "Uint32LessThan", kArm64Cmp32,
+ MachineType::Uint32()},
+ kUnsignedLessThan},
+ {{&RawMachineAssembler::Uint32LessThanOrEqual, "Uint32LessThanOrEqual",
+ kArm64Cmp32, MachineType::Uint32()},
+ kUnsignedLessThanOrEqual}};
+
+} // namespace
+
+
+TEST_F(InstructionSelectorTest, Word32CompareNegateWithWord32Shift) {
+ TRACED_FOREACH(IntegerCmp, cmp, kIntegerCmpInstructions) {
+ TRACED_FOREACH(Shift, shift, kShiftInstructions) {
+ // Test 32-bit operations. Ignore ROR shifts, as compare-negate does not
+ // support them.
+ if (shift.mi.machine_type != MachineType::Int32() ||
+ shift.mi.arch_opcode == kArm64Ror32) {
+ continue;
+ }
+
+ TRACED_FORRANGE(int32_t, imm, -32, 63) {
+ StreamBuilder m(this, MachineType::Int32(), MachineType::Int32(),
+ MachineType::Int32());
+ Node* const p0 = m.Parameter(0);
+ Node* const p1 = m.Parameter(1);
+ Node* r = (m.*shift.mi.constructor)(p1, m.Int32Constant(imm));
+ m.Return(
+ (m.*cmp.mi.constructor)(p0, m.Int32Sub(m.Int32Constant(0), r)));
+ Stream s = m.Build();
+ ASSERT_EQ(1U, s.size());
+ EXPECT_EQ(kArm64Cmn32, s[0]->arch_opcode());
+ EXPECT_EQ(3U, s[0]->InputCount());
+ EXPECT_EQ(shift.mode, s[0]->addressing_mode());
+ EXPECT_EQ(imm, s.ToInt32(s[0]->InputAt(2)));
+ EXPECT_EQ(1U, s[0]->OutputCount());
+ EXPECT_EQ(kFlags_set, s[0]->flags_mode());
+ EXPECT_EQ(cmp.cond, s[0]->flags_condition());
+ }
+ }
+ }
+}
+
+
// -----------------------------------------------------------------------------
// Miscellaneous
static const MachInst2 kLogicalWithNotRHSs[] = {
- {&RawMachineAssembler::Word32And, "Word32And", kArm64Bic32, kMachInt32},
- {&RawMachineAssembler::Word64And, "Word64And", kArm64Bic, kMachInt64},
- {&RawMachineAssembler::Word32Or, "Word32Or", kArm64Orn32, kMachInt32},
- {&RawMachineAssembler::Word64Or, "Word64Or", kArm64Orn, kMachInt64},
- {&RawMachineAssembler::Word32Xor, "Word32Xor", kArm64Eon32, kMachInt32},
- {&RawMachineAssembler::Word64Xor, "Word64Xor", kArm64Eon, kMachInt64}};
+ {&RawMachineAssembler::Word32And, "Word32And", kArm64Bic32,
+ MachineType::Int32()},
+ {&RawMachineAssembler::Word64And, "Word64And", kArm64Bic,
+ MachineType::Int64()},
+ {&RawMachineAssembler::Word32Or, "Word32Or", kArm64Orn32,
+ MachineType::Int32()},
+ {&RawMachineAssembler::Word64Or, "Word64Or", kArm64Orn,
+ MachineType::Int64()},
+ {&RawMachineAssembler::Word32Xor, "Word32Xor", kArm64Eon32,
+ MachineType::Int32()},
+ {&RawMachineAssembler::Word64Xor, "Word64Xor", kArm64Eon,
+ MachineType::Int64()}};
typedef InstructionSelectorTestWithParam<MachInst2>
@@ -1839,11 +2707,11 @@
// Test cases where RHS is Xor(x, -1).
{
StreamBuilder m(this, type, type, type);
- if (type == kMachInt32) {
+ if (type == MachineType::Int32()) {
m.Return((m.*inst.constructor)(
m.Parameter(0), m.Word32Xor(m.Parameter(1), m.Int32Constant(-1))));
} else {
- ASSERT_EQ(kMachInt64, type);
+ ASSERT_EQ(MachineType::Int64(), type);
m.Return((m.*inst.constructor)(
m.Parameter(0), m.Word64Xor(m.Parameter(1), m.Int64Constant(-1))));
}
@@ -1855,11 +2723,11 @@
}
{
StreamBuilder m(this, type, type, type);
- if (type == kMachInt32) {
+ if (type == MachineType::Int32()) {
m.Return((m.*inst.constructor)(
m.Word32Xor(m.Parameter(0), m.Int32Constant(-1)), m.Parameter(1)));
} else {
- ASSERT_EQ(kMachInt64, type);
+ ASSERT_EQ(MachineType::Int64(), type);
m.Return((m.*inst.constructor)(
m.Word64Xor(m.Parameter(0), m.Int64Constant(-1)), m.Parameter(1)));
}
@@ -1872,11 +2740,11 @@
// Test cases where RHS is Not(x).
{
StreamBuilder m(this, type, type, type);
- if (type == kMachInt32) {
+ if (type == MachineType::Int32()) {
m.Return(
(m.*inst.constructor)(m.Parameter(0), m.Word32Not(m.Parameter(1))));
} else {
- ASSERT_EQ(kMachInt64, type);
+ ASSERT_EQ(MachineType::Int64(), type);
m.Return(
(m.*inst.constructor)(m.Parameter(0), m.Word64Not(m.Parameter(1))));
}
@@ -1888,11 +2756,11 @@
}
{
StreamBuilder m(this, type, type, type);
- if (type == kMachInt32) {
+ if (type == MachineType::Int32()) {
m.Return(
(m.*inst.constructor)(m.Word32Not(m.Parameter(0)), m.Parameter(1)));
} else {
- ASSERT_EQ(kMachInt64, type);
+ ASSERT_EQ(MachineType::Int64(), type);
m.Return(
(m.*inst.constructor)(m.Word64Not(m.Parameter(0)), m.Parameter(1)));
}
@@ -1911,7 +2779,7 @@
TEST_F(InstructionSelectorTest, Word32NotWithParameter) {
- StreamBuilder m(this, kMachInt32, kMachInt32);
+ StreamBuilder m(this, MachineType::Int32(), MachineType::Int32());
m.Return(m.Word32Not(m.Parameter(0)));
Stream s = m.Build();
ASSERT_EQ(1U, s.size());
@@ -1922,7 +2790,7 @@
TEST_F(InstructionSelectorTest, Word64NotWithParameter) {
- StreamBuilder m(this, kMachInt64, kMachInt64);
+ StreamBuilder m(this, MachineType::Int64(), MachineType::Int64());
m.Return(m.Word64Not(m.Parameter(0)));
Stream s = m.Build();
ASSERT_EQ(1U, s.size());
@@ -1934,7 +2802,7 @@
TEST_F(InstructionSelectorTest, Word32XorMinusOneWithParameter) {
{
- StreamBuilder m(this, kMachInt32, kMachInt32);
+ StreamBuilder m(this, MachineType::Int32(), MachineType::Int32());
m.Return(m.Word32Xor(m.Parameter(0), m.Int32Constant(-1)));
Stream s = m.Build();
ASSERT_EQ(1U, s.size());
@@ -1943,7 +2811,7 @@
EXPECT_EQ(1U, s[0]->OutputCount());
}
{
- StreamBuilder m(this, kMachInt32, kMachInt32);
+ StreamBuilder m(this, MachineType::Int32(), MachineType::Int32());
m.Return(m.Word32Xor(m.Int32Constant(-1), m.Parameter(0)));
Stream s = m.Build();
ASSERT_EQ(1U, s.size());
@@ -1956,7 +2824,7 @@
TEST_F(InstructionSelectorTest, Word64XorMinusOneWithParameter) {
{
- StreamBuilder m(this, kMachInt64, kMachInt64);
+ StreamBuilder m(this, MachineType::Int64(), MachineType::Int64());
m.Return(m.Word64Xor(m.Parameter(0), m.Int64Constant(-1)));
Stream s = m.Build();
ASSERT_EQ(1U, s.size());
@@ -1965,7 +2833,7 @@
EXPECT_EQ(1U, s[0]->OutputCount());
}
{
- StreamBuilder m(this, kMachInt64, kMachInt64);
+ StreamBuilder m(this, MachineType::Int64(), MachineType::Int64());
m.Return(m.Word64Xor(m.Int64Constant(-1), m.Parameter(0)));
Stream s = m.Build();
ASSERT_EQ(1U, s.size());
@@ -1977,14 +2845,17 @@
TEST_F(InstructionSelectorTest, Word32ShrWithWord32AndWithImmediate) {
- TRACED_FORRANGE(int32_t, lsb, 1, 31) {
+ // The available shift operand range is `0 <= imm < 32`, but we also test
+ // that immediates outside this range are handled properly (modulo-32).
+ TRACED_FORRANGE(int32_t, shift, -32, 63) {
+ int32_t lsb = shift & 0x1f;
TRACED_FORRANGE(int32_t, width, 1, 32 - lsb) {
uint32_t jnk = rng()->NextInt();
- jnk >>= 32 - lsb;
+ jnk = (lsb > 0) ? (jnk >> (32 - lsb)) : 0;
uint32_t msk = ((0xffffffffu >> (32 - width)) << lsb) | jnk;
- StreamBuilder m(this, kMachInt32, kMachInt32);
+ StreamBuilder m(this, MachineType::Int32(), MachineType::Int32());
m.Return(m.Word32Shr(m.Word32And(m.Parameter(0), m.Int32Constant(msk)),
- m.Int32Constant(lsb)));
+ m.Int32Constant(shift)));
Stream s = m.Build();
ASSERT_EQ(1U, s.size());
EXPECT_EQ(kArm64Ubfx32, s[0]->arch_opcode());
@@ -1993,14 +2864,15 @@
EXPECT_EQ(width, s.ToInt32(s[0]->InputAt(2)));
}
}
- TRACED_FORRANGE(int32_t, lsb, 1, 31) {
+ TRACED_FORRANGE(int32_t, shift, -32, 63) {
+ int32_t lsb = shift & 0x1f;
TRACED_FORRANGE(int32_t, width, 1, 32 - lsb) {
uint32_t jnk = rng()->NextInt();
- jnk >>= 32 - lsb;
+ jnk = (lsb > 0) ? (jnk >> (32 - lsb)) : 0;
uint32_t msk = ((0xffffffffu >> (32 - width)) << lsb) | jnk;
- StreamBuilder m(this, kMachInt32, kMachInt32);
+ StreamBuilder m(this, MachineType::Int32(), MachineType::Int32());
m.Return(m.Word32Shr(m.Word32And(m.Int32Constant(msk), m.Parameter(0)),
- m.Int32Constant(lsb)));
+ m.Int32Constant(shift)));
Stream s = m.Build();
ASSERT_EQ(1U, s.size());
EXPECT_EQ(kArm64Ubfx32, s[0]->arch_opcode());
@@ -2013,15 +2885,18 @@
TEST_F(InstructionSelectorTest, Word64ShrWithWord64AndWithImmediate) {
- TRACED_FORRANGE(int32_t, lsb, 1, 63) {
+ // The available shift operand range is `0 <= imm < 64`, but we also test
+ // that immediates outside this range are handled properly (modulo-64).
+ TRACED_FORRANGE(int32_t, shift, -64, 127) {
+ int32_t lsb = shift & 0x3f;
TRACED_FORRANGE(int32_t, width, 1, 64 - lsb) {
uint64_t jnk = rng()->NextInt64();
- jnk >>= 64 - lsb;
+ jnk = (lsb > 0) ? (jnk >> (64 - lsb)) : 0;
uint64_t msk =
((V8_UINT64_C(0xffffffffffffffff) >> (64 - width)) << lsb) | jnk;
- StreamBuilder m(this, kMachInt64, kMachInt64);
+ StreamBuilder m(this, MachineType::Int64(), MachineType::Int64());
m.Return(m.Word64Shr(m.Word64And(m.Parameter(0), m.Int64Constant(msk)),
- m.Int64Constant(lsb)));
+ m.Int64Constant(shift)));
Stream s = m.Build();
ASSERT_EQ(1U, s.size());
EXPECT_EQ(kArm64Ubfx, s[0]->arch_opcode());
@@ -2030,15 +2905,16 @@
EXPECT_EQ(width, s.ToInt64(s[0]->InputAt(2)));
}
}
- TRACED_FORRANGE(int32_t, lsb, 1, 63) {
+ TRACED_FORRANGE(int32_t, shift, -64, 127) {
+ int32_t lsb = shift & 0x3f;
TRACED_FORRANGE(int32_t, width, 1, 64 - lsb) {
uint64_t jnk = rng()->NextInt64();
- jnk >>= 64 - lsb;
+ jnk = (lsb > 0) ? (jnk >> (64 - lsb)) : 0;
uint64_t msk =
((V8_UINT64_C(0xffffffffffffffff) >> (64 - width)) << lsb) | jnk;
- StreamBuilder m(this, kMachInt64, kMachInt64);
+ StreamBuilder m(this, MachineType::Int64(), MachineType::Int64());
m.Return(m.Word64Shr(m.Word64And(m.Int64Constant(msk), m.Parameter(0)),
- m.Int64Constant(lsb)));
+ m.Int64Constant(shift)));
Stream s = m.Build();
ASSERT_EQ(1U, s.size());
EXPECT_EQ(kArm64Ubfx, s[0]->arch_opcode());
@@ -2051,11 +2927,14 @@
TEST_F(InstructionSelectorTest, Word32AndWithImmediateWithWord32Shr) {
- TRACED_FORRANGE(int32_t, lsb, 1, 31) {
+ // The available shift operand range is `0 <= imm < 32`, but we also test
+ // that immediates outside this range are handled properly (modulo-32).
+ TRACED_FORRANGE(int32_t, shift, -32, 63) {
+ int32_t lsb = shift & 0x1f;
TRACED_FORRANGE(int32_t, width, 1, 31) {
uint32_t msk = (1 << width) - 1;
- StreamBuilder m(this, kMachInt32, kMachInt32);
- m.Return(m.Word32And(m.Word32Shr(m.Parameter(0), m.Int32Constant(lsb)),
+ StreamBuilder m(this, MachineType::Int32(), MachineType::Int32());
+ m.Return(m.Word32And(m.Word32Shr(m.Parameter(0), m.Int32Constant(shift)),
m.Int32Constant(msk)));
Stream s = m.Build();
ASSERT_EQ(1U, s.size());
@@ -2066,12 +2945,14 @@
EXPECT_EQ(actual_width, s.ToInt32(s[0]->InputAt(2)));
}
}
- TRACED_FORRANGE(int32_t, lsb, 1, 31) {
+ TRACED_FORRANGE(int32_t, shift, -32, 63) {
+ int32_t lsb = shift & 0x1f;
TRACED_FORRANGE(int32_t, width, 1, 31) {
uint32_t msk = (1 << width) - 1;
- StreamBuilder m(this, kMachInt32, kMachInt32);
- m.Return(m.Word32And(m.Int32Constant(msk),
- m.Word32Shr(m.Parameter(0), m.Int32Constant(lsb))));
+ StreamBuilder m(this, MachineType::Int32(), MachineType::Int32());
+ m.Return(
+ m.Word32And(m.Int32Constant(msk),
+ m.Word32Shr(m.Parameter(0), m.Int32Constant(shift))));
Stream s = m.Build();
ASSERT_EQ(1U, s.size());
EXPECT_EQ(kArm64Ubfx32, s[0]->arch_opcode());
@@ -2085,11 +2966,14 @@
TEST_F(InstructionSelectorTest, Word64AndWithImmediateWithWord64Shr) {
- TRACED_FORRANGE(int64_t, lsb, 1, 63) {
+ // The available shift operand range is `0 <= imm < 64`, but we also test
+ // that immediates outside this range are handled properly (modulo-64).
+ TRACED_FORRANGE(int64_t, shift, -64, 127) {
+ int64_t lsb = shift & 0x3f;
TRACED_FORRANGE(int64_t, width, 1, 63) {
uint64_t msk = (V8_UINT64_C(1) << width) - 1;
- StreamBuilder m(this, kMachInt64, kMachInt64);
- m.Return(m.Word64And(m.Word64Shr(m.Parameter(0), m.Int64Constant(lsb)),
+ StreamBuilder m(this, MachineType::Int64(), MachineType::Int64());
+ m.Return(m.Word64And(m.Word64Shr(m.Parameter(0), m.Int64Constant(shift)),
m.Int64Constant(msk)));
Stream s = m.Build();
ASSERT_EQ(1U, s.size());
@@ -2100,12 +2984,14 @@
EXPECT_EQ(actual_width, s.ToInt64(s[0]->InputAt(2)));
}
}
- TRACED_FORRANGE(int64_t, lsb, 1, 63) {
+ TRACED_FORRANGE(int64_t, shift, -64, 127) {
+ int64_t lsb = shift & 0x3f;
TRACED_FORRANGE(int64_t, width, 1, 63) {
uint64_t msk = (V8_UINT64_C(1) << width) - 1;
- StreamBuilder m(this, kMachInt64, kMachInt64);
- m.Return(m.Word64And(m.Int64Constant(msk),
- m.Word64Shr(m.Parameter(0), m.Int64Constant(lsb))));
+ StreamBuilder m(this, MachineType::Int64(), MachineType::Int64());
+ m.Return(
+ m.Word64And(m.Int64Constant(msk),
+ m.Word64Shr(m.Parameter(0), m.Int64Constant(shift))));
Stream s = m.Build();
ASSERT_EQ(1U, s.size());
EXPECT_EQ(kArm64Ubfx, s[0]->arch_opcode());
@@ -2119,7 +3005,8 @@
TEST_F(InstructionSelectorTest, Int32MulHighWithParameters) {
- StreamBuilder m(this, kMachInt32, kMachInt32, kMachInt32);
+ StreamBuilder m(this, MachineType::Int32(), MachineType::Int32(),
+ MachineType::Int32());
Node* const p0 = m.Parameter(0);
Node* const p1 = m.Parameter(1);
Node* const n = m.Int32MulHigh(p0, p1);
@@ -2140,37 +3027,323 @@
}
+TEST_F(InstructionSelectorTest, Int32MulHighWithSar) {
+ TRACED_FORRANGE(int32_t, shift, -32, 63) {
+ StreamBuilder m(this, MachineType::Int32(), MachineType::Int32(),
+ MachineType::Int32());
+ Node* const p0 = m.Parameter(0);
+ Node* const p1 = m.Parameter(1);
+ Node* const n = m.Word32Sar(m.Int32MulHigh(p0, p1), m.Int32Constant(shift));
+ m.Return(n);
+ Stream s = m.Build();
+ ASSERT_EQ(2U, s.size());
+ EXPECT_EQ(kArm64Smull, s[0]->arch_opcode());
+ ASSERT_EQ(2U, s[0]->InputCount());
+ EXPECT_EQ(s.ToVreg(p0), s.ToVreg(s[0]->InputAt(0)));
+ EXPECT_EQ(s.ToVreg(p1), s.ToVreg(s[0]->InputAt(1)));
+ ASSERT_EQ(1U, s[0]->OutputCount());
+ EXPECT_EQ(kArm64Asr, s[1]->arch_opcode());
+ ASSERT_EQ(2U, s[1]->InputCount());
+ EXPECT_EQ(s.ToVreg(s[0]->Output()), s.ToVreg(s[1]->InputAt(0)));
+ EXPECT_EQ((shift & 0x1f) + 32, s.ToInt64(s[1]->InputAt(1)));
+ ASSERT_EQ(1U, s[1]->OutputCount());
+ EXPECT_EQ(s.ToVreg(n), s.ToVreg(s[1]->Output()));
+ }
+}
+
+
+TEST_F(InstructionSelectorTest, Int32MulHighWithAdd) {
+ StreamBuilder m(this, MachineType::Int32(), MachineType::Int32(),
+ MachineType::Int32());
+ Node* const p0 = m.Parameter(0);
+ Node* const p1 = m.Parameter(1);
+ Node* const a = m.Int32Add(m.Int32MulHigh(p0, p1), p0);
+ // Test only one shift constant here, as we're only interested in it being a
+ // 32-bit operation; the shift amount is irrelevant.
+ Node* const n = m.Word32Sar(a, m.Int32Constant(1));
+ m.Return(n);
+ Stream s = m.Build();
+ ASSERT_EQ(3U, s.size());
+ EXPECT_EQ(kArm64Smull, s[0]->arch_opcode());
+ ASSERT_EQ(2U, s[0]->InputCount());
+ EXPECT_EQ(s.ToVreg(p0), s.ToVreg(s[0]->InputAt(0)));
+ EXPECT_EQ(s.ToVreg(p1), s.ToVreg(s[0]->InputAt(1)));
+ ASSERT_EQ(1U, s[0]->OutputCount());
+ EXPECT_EQ(kArm64Add, s[1]->arch_opcode());
+ EXPECT_EQ(kMode_Operand2_R_ASR_I, s[1]->addressing_mode());
+ ASSERT_EQ(3U, s[1]->InputCount());
+ EXPECT_EQ(s.ToVreg(p0), s.ToVreg(s[1]->InputAt(0)));
+ EXPECT_EQ(s.ToVreg(s[0]->Output()), s.ToVreg(s[1]->InputAt(1)));
+ EXPECT_EQ(32, s.ToInt64(s[1]->InputAt(2)));
+ ASSERT_EQ(1U, s[1]->OutputCount());
+ EXPECT_EQ(kArm64Asr32, s[2]->arch_opcode());
+ ASSERT_EQ(2U, s[2]->InputCount());
+ EXPECT_EQ(s.ToVreg(s[1]->Output()), s.ToVreg(s[2]->InputAt(0)));
+ EXPECT_EQ(1, s.ToInt64(s[2]->InputAt(1)));
+ ASSERT_EQ(1U, s[2]->OutputCount());
+ EXPECT_EQ(s.ToVreg(n), s.ToVreg(s[2]->Output()));
+}
+
+
+TEST_F(InstructionSelectorTest, Uint32MulHighWithShr) {
+ TRACED_FORRANGE(int32_t, shift, -32, 63) {
+ StreamBuilder m(this, MachineType::Int32(), MachineType::Int32(),
+ MachineType::Int32());
+ Node* const p0 = m.Parameter(0);
+ Node* const p1 = m.Parameter(1);
+ Node* const n =
+ m.Word32Shr(m.Uint32MulHigh(p0, p1), m.Int32Constant(shift));
+ m.Return(n);
+ Stream s = m.Build();
+ ASSERT_EQ(2U, s.size());
+ EXPECT_EQ(kArm64Umull, s[0]->arch_opcode());
+ ASSERT_EQ(2U, s[0]->InputCount());
+ EXPECT_EQ(s.ToVreg(p0), s.ToVreg(s[0]->InputAt(0)));
+ EXPECT_EQ(s.ToVreg(p1), s.ToVreg(s[0]->InputAt(1)));
+ ASSERT_EQ(1U, s[0]->OutputCount());
+ EXPECT_EQ(kArm64Lsr, s[1]->arch_opcode());
+ ASSERT_EQ(2U, s[1]->InputCount());
+ EXPECT_EQ(s.ToVreg(s[0]->Output()), s.ToVreg(s[1]->InputAt(0)));
+ EXPECT_EQ((shift & 0x1f) + 32, s.ToInt64(s[1]->InputAt(1)));
+ ASSERT_EQ(1U, s[1]->OutputCount());
+ EXPECT_EQ(s.ToVreg(n), s.ToVreg(s[1]->Output()));
+ }
+}
+
+
TEST_F(InstructionSelectorTest, Word32SarWithWord32Shl) {
- {
- StreamBuilder m(this, kMachInt32, kMachInt32);
+ TRACED_FORRANGE(int32_t, shift, 1, 31) {
+ StreamBuilder m(this, MachineType::Int32(), MachineType::Int32());
Node* const p0 = m.Parameter(0);
- Node* const r =
- m.Word32Sar(m.Word32Shl(p0, m.Int32Constant(24)), m.Int32Constant(24));
+ Node* const r = m.Word32Sar(m.Word32Shl(p0, m.Int32Constant(shift)),
+ m.Int32Constant(shift));
m.Return(r);
Stream s = m.Build();
ASSERT_EQ(1U, s.size());
- EXPECT_EQ(kArm64Sxtb32, s[0]->arch_opcode());
- ASSERT_EQ(1U, s[0]->InputCount());
+ EXPECT_EQ(kArm64Sbfx32, s[0]->arch_opcode());
+ ASSERT_EQ(3U, s[0]->InputCount());
EXPECT_EQ(s.ToVreg(p0), s.ToVreg(s[0]->InputAt(0)));
ASSERT_EQ(1U, s[0]->OutputCount());
EXPECT_EQ(s.ToVreg(r), s.ToVreg(s[0]->Output()));
}
- {
- StreamBuilder m(this, kMachInt32, kMachInt32);
+ TRACED_FORRANGE(int32_t, shift, 1, 31) {
+ StreamBuilder m(this, MachineType::Int32(), MachineType::Int32());
Node* const p0 = m.Parameter(0);
- Node* const r =
- m.Word32Sar(m.Word32Shl(p0, m.Int32Constant(16)), m.Int32Constant(16));
+ Node* const r = m.Word32Sar(m.Word32Shl(p0, m.Int32Constant(shift + 32)),
+ m.Int32Constant(shift + 64));
m.Return(r);
Stream s = m.Build();
ASSERT_EQ(1U, s.size());
- EXPECT_EQ(kArm64Sxth32, s[0]->arch_opcode());
- ASSERT_EQ(1U, s[0]->InputCount());
+ EXPECT_EQ(kArm64Sbfx32, s[0]->arch_opcode());
+ ASSERT_EQ(3U, s[0]->InputCount());
EXPECT_EQ(s.ToVreg(p0), s.ToVreg(s[0]->InputAt(0)));
ASSERT_EQ(1U, s[0]->OutputCount());
EXPECT_EQ(s.ToVreg(r), s.ToVreg(s[0]->Output()));
}
}
+
+TEST_F(InstructionSelectorTest, Word32ShrWithWord32Shl) {
+ TRACED_FORRANGE(int32_t, shift, 1, 31) {
+ StreamBuilder m(this, MachineType::Int32(), MachineType::Int32());
+ Node* const p0 = m.Parameter(0);
+ Node* const r = m.Word32Shr(m.Word32Shl(p0, m.Int32Constant(shift)),
+ m.Int32Constant(shift));
+ m.Return(r);
+ Stream s = m.Build();
+ ASSERT_EQ(1U, s.size());
+ EXPECT_EQ(kArm64Ubfx32, s[0]->arch_opcode());
+ ASSERT_EQ(3U, s[0]->InputCount());
+ EXPECT_EQ(s.ToVreg(p0), s.ToVreg(s[0]->InputAt(0)));
+ ASSERT_EQ(1U, s[0]->OutputCount());
+ EXPECT_EQ(s.ToVreg(r), s.ToVreg(s[0]->Output()));
+ }
+ TRACED_FORRANGE(int32_t, shift, 1, 31) {
+ StreamBuilder m(this, MachineType::Int32(), MachineType::Int32());
+ Node* const p0 = m.Parameter(0);
+ Node* const r = m.Word32Shr(m.Word32Shl(p0, m.Int32Constant(shift + 32)),
+ m.Int32Constant(shift + 64));
+ m.Return(r);
+ Stream s = m.Build();
+ ASSERT_EQ(1U, s.size());
+ EXPECT_EQ(kArm64Ubfx32, s[0]->arch_opcode());
+ ASSERT_EQ(3U, s[0]->InputCount());
+ EXPECT_EQ(s.ToVreg(p0), s.ToVreg(s[0]->InputAt(0)));
+ ASSERT_EQ(1U, s[0]->OutputCount());
+ EXPECT_EQ(s.ToVreg(r), s.ToVreg(s[0]->Output()));
+ }
+}
+
+
+TEST_F(InstructionSelectorTest, Word32ShlWithWord32And) {
+ TRACED_FORRANGE(int32_t, shift, 1, 30) {
+ StreamBuilder m(this, MachineType::Int32(), MachineType::Int32());
+ Node* const p0 = m.Parameter(0);
+ Node* const r =
+ m.Word32Shl(m.Word32And(p0, m.Int32Constant((1 << (31 - shift)) - 1)),
+ m.Int32Constant(shift));
+ m.Return(r);
+ Stream s = m.Build();
+ ASSERT_EQ(1U, s.size());
+ EXPECT_EQ(kArm64Ubfiz32, s[0]->arch_opcode());
+ ASSERT_EQ(3U, s[0]->InputCount());
+ EXPECT_EQ(s.ToVreg(p0), s.ToVreg(s[0]->InputAt(0)));
+ ASSERT_EQ(1U, s[0]->OutputCount());
+ EXPECT_EQ(s.ToVreg(r), s.ToVreg(s[0]->Output()));
+ }
+ TRACED_FORRANGE(int32_t, shift, 0, 30) {
+ StreamBuilder m(this, MachineType::Int32(), MachineType::Int32());
+ Node* const p0 = m.Parameter(0);
+ Node* const r =
+ m.Word32Shl(m.Word32And(p0, m.Int32Constant((1 << (31 - shift)) - 1)),
+ m.Int32Constant(shift + 1));
+ m.Return(r);
+ Stream s = m.Build();
+ ASSERT_EQ(1U, s.size());
+ EXPECT_EQ(kArm64Lsl32, s[0]->arch_opcode());
+ ASSERT_EQ(2U, s[0]->InputCount());
+ EXPECT_EQ(s.ToVreg(p0), s.ToVreg(s[0]->InputAt(0)));
+ ASSERT_EQ(1U, s[0]->OutputCount());
+ EXPECT_EQ(s.ToVreg(r), s.ToVreg(s[0]->Output()));
+ }
+}
+
+
+TEST_F(InstructionSelectorTest, Word32Clz) {
+ StreamBuilder m(this, MachineType::Uint32(), MachineType::Uint32());
+ Node* const p0 = m.Parameter(0);
+ Node* const n = m.Word32Clz(p0);
+ m.Return(n);
+ Stream s = m.Build();
+ ASSERT_EQ(1U, s.size());
+ EXPECT_EQ(kArm64Clz32, s[0]->arch_opcode());
+ ASSERT_EQ(1U, s[0]->InputCount());
+ EXPECT_EQ(s.ToVreg(p0), s.ToVreg(s[0]->InputAt(0)));
+ ASSERT_EQ(1U, s[0]->OutputCount());
+ EXPECT_EQ(s.ToVreg(n), s.ToVreg(s[0]->Output()));
+}
+
+
+TEST_F(InstructionSelectorTest, Float32Abs) {
+ StreamBuilder m(this, MachineType::Float32(), MachineType::Float32());
+ Node* const p0 = m.Parameter(0);
+ Node* const n = m.Float32Abs(p0);
+ m.Return(n);
+ Stream s = m.Build();
+ ASSERT_EQ(1U, s.size());
+ EXPECT_EQ(kArm64Float32Abs, s[0]->arch_opcode());
+ ASSERT_EQ(1U, s[0]->InputCount());
+ EXPECT_EQ(s.ToVreg(p0), s.ToVreg(s[0]->InputAt(0)));
+ ASSERT_EQ(1U, s[0]->OutputCount());
+ EXPECT_EQ(s.ToVreg(n), s.ToVreg(s[0]->Output()));
+}
+
+
+TEST_F(InstructionSelectorTest, Float64Abs) {
+ StreamBuilder m(this, MachineType::Float64(), MachineType::Float64());
+ Node* const p0 = m.Parameter(0);
+ Node* const n = m.Float64Abs(p0);
+ m.Return(n);
+ Stream s = m.Build();
+ ASSERT_EQ(1U, s.size());
+ EXPECT_EQ(kArm64Float64Abs, s[0]->arch_opcode());
+ ASSERT_EQ(1U, s[0]->InputCount());
+ EXPECT_EQ(s.ToVreg(p0), s.ToVreg(s[0]->InputAt(0)));
+ ASSERT_EQ(1U, s[0]->OutputCount());
+ EXPECT_EQ(s.ToVreg(n), s.ToVreg(s[0]->Output()));
+}
+
+
+TEST_F(InstructionSelectorTest, Float64SubWithMinusZero) {
+ StreamBuilder m(this, MachineType::Float64(), MachineType::Float64());
+ Node* const p0 = m.Parameter(0);
+ Node* const n = m.Float64Sub(m.Float64Constant(-0.0), p0);
+ m.Return(n);
+ Stream s = m.Build();
+ ASSERT_EQ(1U, s.size());
+ EXPECT_EQ(kArm64Float64Neg, s[0]->arch_opcode());
+ ASSERT_EQ(1U, s[0]->InputCount());
+ EXPECT_EQ(s.ToVreg(p0), s.ToVreg(s[0]->InputAt(0)));
+ ASSERT_EQ(1U, s[0]->OutputCount());
+ EXPECT_EQ(s.ToVreg(n), s.ToVreg(s[0]->Output()));
+}
+
+
+TEST_F(InstructionSelectorTest, Float32Max) {
+ StreamBuilder m(this, MachineType::Float32(), MachineType::Float32(),
+ MachineType::Float32());
+ Node* const p0 = m.Parameter(0);
+ Node* const p1 = m.Parameter(1);
+ Node* const n = m.Float32Max(p0, p1);
+ m.Return(n);
+ Stream s = m.Build();
+ // Float32Max is `(b < a) ? a : b`.
+ ASSERT_EQ(1U, s.size());
+ EXPECT_EQ(kArm64Float32Max, s[0]->arch_opcode());
+ ASSERT_EQ(2U, s[0]->InputCount());
+ EXPECT_EQ(s.ToVreg(p0), s.ToVreg(s[0]->InputAt(0)));
+ EXPECT_EQ(s.ToVreg(p1), s.ToVreg(s[0]->InputAt(1)));
+ ASSERT_EQ(1U, s[0]->OutputCount());
+ EXPECT_EQ(s.ToVreg(n), s.ToVreg(s[0]->Output()));
+}
+
+
+TEST_F(InstructionSelectorTest, Float32Min) {
+ StreamBuilder m(this, MachineType::Float32(), MachineType::Float32(),
+ MachineType::Float32());
+ Node* const p0 = m.Parameter(0);
+ Node* const p1 = m.Parameter(1);
+ Node* const n = m.Float32Min(p0, p1);
+ m.Return(n);
+ Stream s = m.Build();
+ // Float32Min is `(a < b) ? a : b`.
+ ASSERT_EQ(1U, s.size());
+ EXPECT_EQ(kArm64Float32Min, s[0]->arch_opcode());
+ ASSERT_EQ(2U, s[0]->InputCount());
+ EXPECT_EQ(s.ToVreg(p0), s.ToVreg(s[0]->InputAt(0)));
+ EXPECT_EQ(s.ToVreg(p1), s.ToVreg(s[0]->InputAt(1)));
+ ASSERT_EQ(1U, s[0]->OutputCount());
+ EXPECT_EQ(s.ToVreg(n), s.ToVreg(s[0]->Output()));
+}
+
+
+TEST_F(InstructionSelectorTest, Float64Max) {
+ StreamBuilder m(this, MachineType::Float64(), MachineType::Float64(),
+ MachineType::Float64());
+ Node* const p0 = m.Parameter(0);
+ Node* const p1 = m.Parameter(1);
+ Node* const n = m.Float64Max(p0, p1);
+ m.Return(n);
+ Stream s = m.Build();
+ // Float64Max is `(b < a) ? a : b`.
+ ASSERT_EQ(1U, s.size());
+ EXPECT_EQ(kArm64Float64Max, s[0]->arch_opcode());
+ ASSERT_EQ(2U, s[0]->InputCount());
+ EXPECT_EQ(s.ToVreg(p0), s.ToVreg(s[0]->InputAt(0)));
+ EXPECT_EQ(s.ToVreg(p1), s.ToVreg(s[0]->InputAt(1)));
+ ASSERT_EQ(1U, s[0]->OutputCount());
+ EXPECT_EQ(s.ToVreg(n), s.ToVreg(s[0]->Output()));
+}
+
+
+TEST_F(InstructionSelectorTest, Float64Min) {
+ StreamBuilder m(this, MachineType::Float64(), MachineType::Float64(),
+ MachineType::Float64());
+ Node* const p0 = m.Parameter(0);
+ Node* const p1 = m.Parameter(1);
+ Node* const n = m.Float64Min(p0, p1);
+ m.Return(n);
+ Stream s = m.Build();
+ // Float64Min is `(a < b) ? a : b`.
+ ASSERT_EQ(1U, s.size());
+ EXPECT_EQ(kArm64Float64Min, s[0]->arch_opcode());
+ ASSERT_EQ(2U, s[0]->InputCount());
+ EXPECT_EQ(s.ToVreg(p0), s.ToVreg(s[0]->InputAt(0)));
+ EXPECT_EQ(s.ToVreg(p1), s.ToVreg(s[0]->InputAt(1)));
+ ASSERT_EQ(1U, s[0]->OutputCount());
+ EXPECT_EQ(s.ToVreg(n), s.ToVreg(s[0]->Output()));
+}
+
} // namespace compiler
} // namespace internal
} // namespace v8