Merge V8 5.3.332.45. DO NOT MERGE
Test: Manual
FPIIM-449
Change-Id: Id3254828b068abdea3cb10442e0172a8c9a98e03
(cherry picked from commit 13e2dadd00298019ed862f2b2fc5068bba730bcf)
diff --git a/src/arm/macro-assembler-arm.cc b/src/arm/macro-assembler-arm.cc
index d723251..4feadb7 100644
--- a/src/arm/macro-assembler-arm.cc
+++ b/src/arm/macro-assembler-arm.cc
@@ -89,17 +89,6 @@
}
-int MacroAssembler::CallSizeNotPredictableCodeSize(Isolate* isolate,
- Address target,
- RelocInfo::Mode rmode,
- Condition cond) {
- Instr mov_instr = cond | MOV | LeaveCC;
- Operand mov_operand = Operand(reinterpret_cast<intptr_t>(target), rmode);
- return kInstrSize +
- mov_operand.instructions_required(NULL, mov_instr) * kInstrSize;
-}
-
-
void MacroAssembler::Call(Address target,
RelocInfo::Mode rmode,
Condition cond,
@@ -131,12 +120,6 @@
// blx ip
// @ return address
- // Statement positions are expected to be recorded when the target
- // address is loaded. The mov method will automatically record
- // positions when pc is the target, since this is not the case here
- // we have to do it explicitly.
- positions_recorder()->WriteRecordedPositions();
-
mov(ip, Operand(reinterpret_cast<int32_t>(target), rmode));
blx(ip, cond);
@@ -173,6 +156,40 @@
Call(reinterpret_cast<Address>(code.location()), rmode, cond, mode);
}
+void MacroAssembler::CallDeoptimizer(Address target) {
+ BlockConstPoolScope block_const_pool(this);
+
+ uintptr_t target_raw = reinterpret_cast<uintptr_t>(target);
+
+ // We use blx, like a call, but it does not return here. The link register is
+ // used by the deoptimizer to work out what called it.
+ if (CpuFeatures::IsSupported(ARMv7)) {
+ CpuFeatureScope scope(this, ARMv7);
+ movw(ip, target_raw & 0xffff);
+ movt(ip, (target_raw >> 16) & 0xffff);
+ blx(ip);
+ } else {
+ // We need to load a literal, but we can't use the usual constant pool
+ // because we call this from a patcher, and cannot afford the guard
+ // instruction and other administrative overhead.
+ ldr(ip, MemOperand(pc, (2 * kInstrSize) - kPcLoadDelta));
+ blx(ip);
+ dd(target_raw);
+ }
+}
+
+int MacroAssembler::CallDeoptimizerSize() {
+ // ARMv7+:
+ // movw ip, ...
+ // movt ip, ...
+ // blx ip @ This never returns.
+ //
+ // ARMv6:
+ // ldr ip, =address
+ // blx ip @ This never returns.
+ // .word address
+ return 3 * kInstrSize;
+}
void MacroAssembler::Ret(Condition cond) {
bx(lr, cond);
@@ -245,6 +262,11 @@
}
}
+void MacroAssembler::Move(SwVfpRegister dst, SwVfpRegister src) {
+ if (!dst.is(src)) {
+ vmov(dst, src);
+ }
+}
void MacroAssembler::Move(DwVfpRegister dst, DwVfpRegister src) {
if (!dst.is(src)) {
@@ -252,11 +274,10 @@
}
}
-
void MacroAssembler::Mls(Register dst, Register src1, Register src2,
Register srcA, Condition cond) {
- if (CpuFeatures::IsSupported(MLS)) {
- CpuFeatureScope scope(this, MLS);
+ if (CpuFeatures::IsSupported(ARMv7)) {
+ CpuFeatureScope scope(this, ARMv7);
mls(dst, src1, src2, srcA, cond);
} else {
DCHECK(!srcA.is(ip));
@@ -841,8 +862,7 @@
// Number of d-regs not known at snapshot time.
DCHECK(!serializer_enabled());
// General purpose registers are pushed last on the stack.
- const RegisterConfiguration* config =
- RegisterConfiguration::ArchDefault(RegisterConfiguration::CRANKSHAFT);
+ const RegisterConfiguration* config = RegisterConfiguration::Crankshaft();
int doubles_size = config->num_allocatable_double_registers() * kDoubleSize;
int register_offset = SafepointRegisterStackIndex(reg.code()) * kPointerSize;
return MemOperand(sp, doubles_size + register_offset);
@@ -1237,9 +1257,8 @@
void MacroAssembler::EmitLoadTypeFeedbackVector(Register vector) {
ldr(vector, MemOperand(fp, JavaScriptFrameConstants::kFunctionOffset));
- ldr(vector, FieldMemOperand(vector, JSFunction::kSharedFunctionInfoOffset));
- ldr(vector,
- FieldMemOperand(vector, SharedFunctionInfo::kFeedbackVectorOffset));
+ ldr(vector, FieldMemOperand(vector, JSFunction::kLiteralsOffset));
+ ldr(vector, FieldMemOperand(vector, LiteralsArray::kFeedbackVectorOffset));
}
@@ -1553,12 +1572,13 @@
const ParameterCount& expected,
const ParameterCount& actual) {
Label skip_flooding;
- ExternalReference step_in_enabled =
- ExternalReference::debug_step_in_enabled_address(isolate());
- mov(r4, Operand(step_in_enabled));
- ldrb(r4, MemOperand(r4));
- cmp(r4, Operand(0));
- b(eq, &skip_flooding);
+ ExternalReference last_step_action =
+ ExternalReference::debug_last_step_action_address(isolate());
+ STATIC_ASSERT(StepFrame > StepIn);
+ mov(r4, Operand(last_step_action));
+ ldrsb(r4, MemOperand(r4));
+ cmp(r4, Operand(StepIn));
+ b(lt, &skip_flooding);
{
FrameScope frame(this,
has_frame() ? StackFrame::NONE : StackFrame::INTERNAL);
@@ -3870,8 +3890,7 @@
if (reg5.is_valid()) regs |= reg5.bit();
if (reg6.is_valid()) regs |= reg6.bit();
- const RegisterConfiguration* config =
- RegisterConfiguration::ArchDefault(RegisterConfiguration::CRANKSHAFT);
+ const RegisterConfiguration* config = RegisterConfiguration::Crankshaft();
for (int i = 0; i < config->num_allocatable_general_registers(); ++i) {
int code = config->GetAllocatableGeneralCode(i);
Register candidate = Register::from_code(code);
@@ -3969,6 +3988,10 @@
Assembler::FlushICache(masm_.isolate(), address_, size_);
}
+ // Check that we don't have any pending constant pools.
+ DCHECK(masm_.pending_32_bit_constants_.empty());
+ DCHECK(masm_.pending_64_bit_constants_.empty());
+
// Check that the code was patched as expected.
DCHECK(masm_.pc_ == address_ + size_);
DCHECK(masm_.reloc_info_writer.pos() == address_ + size_ + Assembler::kGap);