Merge V8 5.3.332.45. DO NOT MERGE
Test: Manual
FPIIM-449
Change-Id: Id3254828b068abdea3cb10442e0172a8c9a98e03
(cherry picked from commit 13e2dadd00298019ed862f2b2fc5068bba730bcf)
diff --git a/src/arm64/assembler-arm64.h b/src/arm64/assembler-arm64.h
index fac7a70..cc26278 100644
--- a/src/arm64/assembler-arm64.h
+++ b/src/arm64/assembler-arm64.h
@@ -154,8 +154,6 @@
DCHECK(IsValidOrNone());
}
- const char* ToString();
- bool IsAllocatable() const;
bool IsValid() const {
DCHECK(IsRegister() || IsNone());
return IsValidRegister();
@@ -195,6 +193,7 @@
// End of V8 compatibility section -----------------------
};
+static const bool kSimpleFPAliasing = true;
struct FPRegister : public CPURegister {
enum Code {
@@ -230,8 +229,6 @@
DCHECK(IsValidOrNone());
}
- const char* ToString();
- bool IsAllocatable() const;
bool IsValid() const {
DCHECK(IsFPRegister() || IsNone());
return IsValidFPRegister();
@@ -1401,6 +1398,42 @@
// Load literal to register.
void ldr(const CPURegister& rt, const Immediate& imm);
+ // Load-acquire word.
+ void ldar(const Register& rt, const Register& rn);
+
+ // Load-acquire exclusive word.
+ void ldaxr(const Register& rt, const Register& rn);
+
+ // Store-release word.
+ void stlr(const Register& rt, const Register& rn);
+
+ // Store-release exclusive word.
+ void stlxr(const Register& rs, const Register& rt, const Register& rn);
+
+ // Load-acquire byte.
+ void ldarb(const Register& rt, const Register& rn);
+
+ // Load-acquire exclusive byte.
+ void ldaxrb(const Register& rt, const Register& rn);
+
+ // Store-release byte.
+ void stlrb(const Register& rt, const Register& rn);
+
+ // Store-release exclusive byte.
+ void stlxrb(const Register& rs, const Register& rt, const Register& rn);
+
+ // Load-acquire half-word.
+ void ldarh(const Register& rt, const Register& rn);
+
+ // Load-acquire exclusive half-word.
+ void ldaxrh(const Register& rt, const Register& rn);
+
+ // Store-release half-word.
+ void stlrh(const Register& rt, const Register& rn);
+
+ // Store-release exclusive half-word.
+ void stlxrh(const Register& rs, const Register& rt, const Register& rn);
+
// Move instructions. The default shift of -1 indicates that the move
// instruction will calculate an appropriate 16-bit immediate and left shift
// that is equal to the 64-bit immediate argument. If an explicit left shift
@@ -1695,6 +1728,11 @@
return rt2.code() << Rt2_offset;
}
+ static Instr Rs(CPURegister rs) {
+ DCHECK(rs.code() != kSPRegInternalCode);
+ return rs.code() << Rs_offset;
+ }
+
// These encoding functions allow the stack pointer to be encoded, and
// disallow the zero register.
static Instr RdSP(Register rd) {