Merge V8 5.3.332.45. DO NOT MERGE
Test: Manual
FPIIM-449
Change-Id: Id3254828b068abdea3cb10442e0172a8c9a98e03
(cherry picked from commit 13e2dadd00298019ed862f2b2fc5068bba730bcf)
diff --git a/src/compiler/instruction-selector.cc b/src/compiler/instruction-selector.cc
index ea68c78..558aff3 100644
--- a/src/compiler/instruction-selector.cc
+++ b/src/compiler/instruction-selector.cc
@@ -906,6 +906,12 @@
case IrOpcode::kStateValues:
case IrOpcode::kObjectState:
return;
+ case IrOpcode::kDebugBreak:
+ VisitDebugBreak(node);
+ return;
+ case IrOpcode::kComment:
+ VisitComment(node);
+ return;
case IrOpcode::kLoad: {
LoadRepresentation type = LoadRepresentationOf(node->op());
MarkAsRepresentation(type.representation(), node);
@@ -1029,6 +1035,13 @@
return MarkAsWord32(node), VisitChangeFloat64ToInt32(node);
case IrOpcode::kChangeFloat64ToUint32:
return MarkAsWord32(node), VisitChangeFloat64ToUint32(node);
+ case IrOpcode::kFloat64SilenceNaN:
+ MarkAsFloat64(node);
+ if (CanProduceSignalingNaN(node->InputAt(0))) {
+ return VisitFloat64SilenceNaN(node);
+ } else {
+ return EmitIdentity(node);
+ }
case IrOpcode::kTruncateFloat64ToUint32:
return MarkAsWord32(node), VisitTruncateFloat64ToUint32(node);
case IrOpcode::kTruncateFloat32ToInt32:
@@ -1081,6 +1094,8 @@
return MarkAsFloat32(node), VisitFloat32Sub(node);
case IrOpcode::kFloat32SubPreserveNan:
return MarkAsFloat32(node), VisitFloat32SubPreserveNan(node);
+ case IrOpcode::kFloat32Neg:
+ return MarkAsFloat32(node), VisitFloat32Neg(node);
case IrOpcode::kFloat32Mul:
return MarkAsFloat32(node), VisitFloat32Mul(node);
case IrOpcode::kFloat32Div:
@@ -1105,6 +1120,8 @@
return MarkAsFloat64(node), VisitFloat64Sub(node);
case IrOpcode::kFloat64SubPreserveNan:
return MarkAsFloat64(node), VisitFloat64SubPreserveNan(node);
+ case IrOpcode::kFloat64Neg:
+ return MarkAsFloat64(node), VisitFloat64Neg(node);
case IrOpcode::kFloat64Mul:
return MarkAsFloat64(node), VisitFloat64Mul(node);
case IrOpcode::kFloat64Div:
@@ -1117,8 +1134,34 @@
return MarkAsFloat64(node), VisitFloat64Max(node);
case IrOpcode::kFloat64Abs:
return MarkAsFloat64(node), VisitFloat64Abs(node);
+ case IrOpcode::kFloat64Atan:
+ return MarkAsFloat64(node), VisitFloat64Atan(node);
+ case IrOpcode::kFloat64Atan2:
+ return MarkAsFloat64(node), VisitFloat64Atan2(node);
+ case IrOpcode::kFloat64Atanh:
+ return MarkAsFloat64(node), VisitFloat64Atanh(node);
+ case IrOpcode::kFloat64Cbrt:
+ return MarkAsFloat64(node), VisitFloat64Cbrt(node);
+ case IrOpcode::kFloat64Cos:
+ return MarkAsFloat64(node), VisitFloat64Cos(node);
+ case IrOpcode::kFloat64Exp:
+ return MarkAsFloat64(node), VisitFloat64Exp(node);
+ case IrOpcode::kFloat64Expm1:
+ return MarkAsFloat64(node), VisitFloat64Expm1(node);
+ case IrOpcode::kFloat64Log:
+ return MarkAsFloat64(node), VisitFloat64Log(node);
+ case IrOpcode::kFloat64Log1p:
+ return MarkAsFloat64(node), VisitFloat64Log1p(node);
+ case IrOpcode::kFloat64Log10:
+ return MarkAsFloat64(node), VisitFloat64Log10(node);
+ case IrOpcode::kFloat64Log2:
+ return MarkAsFloat64(node), VisitFloat64Log2(node);
+ case IrOpcode::kFloat64Sin:
+ return MarkAsFloat64(node), VisitFloat64Sin(node);
case IrOpcode::kFloat64Sqrt:
return MarkAsFloat64(node), VisitFloat64Sqrt(node);
+ case IrOpcode::kFloat64Tan:
+ return MarkAsFloat64(node), VisitFloat64Tan(node);
case IrOpcode::kFloat64Equal:
return VisitFloat64Equal(node);
case IrOpcode::kFloat64LessThan:
@@ -1222,6 +1265,58 @@
Emit(kArchParentFramePointer, g.DefineAsRegister(node));
}
+void InstructionSelector::VisitFloat64Atan(Node* node) {
+ VisitFloat64Ieee754Unop(node, kIeee754Float64Atan);
+}
+
+void InstructionSelector::VisitFloat64Atan2(Node* node) {
+ VisitFloat64Ieee754Binop(node, kIeee754Float64Atan2);
+}
+
+void InstructionSelector::VisitFloat64Atanh(Node* node) {
+ VisitFloat64Ieee754Unop(node, kIeee754Float64Atanh);
+}
+
+void InstructionSelector::VisitFloat64Cbrt(Node* node) {
+ VisitFloat64Ieee754Unop(node, kIeee754Float64Cbrt);
+}
+
+void InstructionSelector::VisitFloat64Cos(Node* node) {
+ VisitFloat64Ieee754Unop(node, kIeee754Float64Cos);
+}
+
+void InstructionSelector::VisitFloat64Exp(Node* node) {
+ VisitFloat64Ieee754Unop(node, kIeee754Float64Exp);
+}
+
+void InstructionSelector::VisitFloat64Expm1(Node* node) {
+ VisitFloat64Ieee754Unop(node, kIeee754Float64Expm1);
+}
+
+void InstructionSelector::VisitFloat64Log(Node* node) {
+ VisitFloat64Ieee754Unop(node, kIeee754Float64Log);
+}
+
+void InstructionSelector::VisitFloat64Log1p(Node* node) {
+ VisitFloat64Ieee754Unop(node, kIeee754Float64Log1p);
+}
+
+void InstructionSelector::VisitFloat64Log2(Node* node) {
+ VisitFloat64Ieee754Unop(node, kIeee754Float64Log2);
+}
+
+void InstructionSelector::VisitFloat64Log10(Node* node) {
+ VisitFloat64Ieee754Unop(node, kIeee754Float64Log10);
+}
+
+void InstructionSelector::VisitFloat64Sin(Node* node) {
+ VisitFloat64Ieee754Unop(node, kIeee754Float64Sin);
+}
+
+void InstructionSelector::VisitFloat64Tan(Node* node) {
+ VisitFloat64Ieee754Unop(node, kIeee754Float64Tan);
+}
+
void InstructionSelector::EmitTableSwitch(const SwitchInfo& sw,
InstructionOperand& index_operand) {
OperandGenerator g(this);
@@ -1267,9 +1362,7 @@
}
void InstructionSelector::VisitBitcastWordToTagged(Node* node) {
- OperandGenerator g(this);
- Node* value = node->InputAt(0);
- Emit(kArchNop, g.DefineSameAsFirst(node), g.Use(value));
+ EmitIdentity(node);
}
// 32 bit targets do not implement the following instructions.
@@ -1441,12 +1534,7 @@
void InstructionSelector::VisitWord32PairSar(Node* node) { UNIMPLEMENTED(); }
#endif // V8_TARGET_ARCH_64_BIT
-void InstructionSelector::VisitFinishRegion(Node* node) {
- OperandGenerator g(this);
- Node* value = node->InputAt(0);
- Emit(kArchNop, g.DefineSameAsFirst(node), g.Use(value));
-}
-
+void InstructionSelector::VisitFinishRegion(Node* node) { EmitIdentity(node); }
void InstructionSelector::VisitParameter(Node* node) {
OperandGenerator g(this);
@@ -1772,6 +1860,12 @@
nullptr);
}
+void InstructionSelector::EmitIdentity(Node* node) {
+ OperandGenerator g(this);
+ Node* value = node->InputAt(0);
+ Emit(kArchNop, g.DefineSameAsFirst(node), g.Use(value));
+}
+
void InstructionSelector::VisitDeoptimize(DeoptimizeKind kind, Node* value) {
InstructionCode opcode = kArchDeoptimize;
switch (kind) {
@@ -1791,6 +1885,26 @@
Emit(kArchThrowTerminator, g.NoOutput());
}
+void InstructionSelector::VisitDebugBreak(Node* node) {
+ OperandGenerator g(this);
+ Emit(kArchDebugBreak, g.NoOutput());
+}
+
+void InstructionSelector::VisitComment(Node* node) {
+ OperandGenerator g(this);
+ InstructionOperand operand(g.UseImmediate(node));
+ Emit(kArchComment, 0, nullptr, 1, &operand);
+}
+
+bool InstructionSelector::CanProduceSignalingNaN(Node* node) {
+ // TODO(jarin) Improve the heuristic here.
+ if (node->opcode() == IrOpcode::kFloat64Add ||
+ node->opcode() == IrOpcode::kFloat64Sub ||
+ node->opcode() == IrOpcode::kFloat64Mul) {
+ return false;
+ }
+ return true;
+}
FrameStateDescriptor* InstructionSelector::GetFrameStateDescriptor(
Node* state) {