Merge V8 5.3.332.45. DO NOT MERGE
Test: Manual
FPIIM-449
Change-Id: Id3254828b068abdea3cb10442e0172a8c9a98e03
(cherry picked from commit 13e2dadd00298019ed862f2b2fc5068bba730bcf)
diff --git a/src/compiler/mips/code-generator-mips.cc b/src/compiler/mips/code-generator-mips.cc
index c437d5e..5e30e34 100644
--- a/src/compiler/mips/code-generator-mips.cc
+++ b/src/compiler/mips/code-generator-mips.cc
@@ -485,6 +485,29 @@
__ sync(); \
} while (0)
+#define ASSEMBLE_IEEE754_BINOP(name) \
+ do { \
+ FrameScope scope(masm(), StackFrame::MANUAL); \
+ __ PrepareCallCFunction(0, 2, kScratchReg); \
+ __ MovToFloatParameters(i.InputDoubleRegister(0), \
+ i.InputDoubleRegister(1)); \
+ __ CallCFunction(ExternalReference::ieee754_##name##_function(isolate()), \
+ 0, 2); \
+ /* Move the result in the double result register. */ \
+ __ MovFromFloatResult(i.OutputDoubleRegister()); \
+ } while (0)
+
+#define ASSEMBLE_IEEE754_UNOP(name) \
+ do { \
+ FrameScope scope(masm(), StackFrame::MANUAL); \
+ __ PrepareCallCFunction(0, 1, kScratchReg); \
+ __ MovToFloatParameter(i.InputDoubleRegister(0)); \
+ __ CallCFunction(ExternalReference::ieee754_##name##_function(isolate()), \
+ 0, 1); \
+ /* Move the result in the double result register. */ \
+ __ MovFromFloatResult(i.OutputDoubleRegister()); \
+ } while (0)
+
void CodeGenerator::AssembleDeconstructFrame() {
__ mov(sp, fp);
__ Pop(ra, fp);
@@ -652,6 +675,14 @@
case kArchTableSwitch:
AssembleArchTableSwitch(instr);
break;
+ case kArchDebugBreak:
+ __ stop("kArchDebugBreak");
+ break;
+ case kArchComment: {
+ Address comment_string = i.InputExternalReference(0).address();
+ __ RecordComment(reinterpret_cast<const char*>(comment_string));
+ break;
+ }
case kArchNop:
case kArchThrowTerminator:
// don't emit code for nops.
@@ -710,6 +741,45 @@
Operand(offset.offset()));
break;
}
+ case kIeee754Float64Atan:
+ ASSEMBLE_IEEE754_UNOP(atan);
+ break;
+ case kIeee754Float64Atan2:
+ ASSEMBLE_IEEE754_BINOP(atan2);
+ break;
+ case kIeee754Float64Cos:
+ ASSEMBLE_IEEE754_UNOP(cos);
+ break;
+ case kIeee754Float64Cbrt:
+ ASSEMBLE_IEEE754_UNOP(cbrt);
+ break;
+ case kIeee754Float64Exp:
+ ASSEMBLE_IEEE754_UNOP(exp);
+ break;
+ case kIeee754Float64Expm1:
+ ASSEMBLE_IEEE754_UNOP(expm1);
+ break;
+ case kIeee754Float64Atanh:
+ ASSEMBLE_IEEE754_UNOP(atanh);
+ break;
+ case kIeee754Float64Log:
+ ASSEMBLE_IEEE754_UNOP(log);
+ break;
+ case kIeee754Float64Log1p:
+ ASSEMBLE_IEEE754_UNOP(log1p);
+ break;
+ case kIeee754Float64Log10:
+ ASSEMBLE_IEEE754_UNOP(log10);
+ break;
+ case kIeee754Float64Log2:
+ ASSEMBLE_IEEE754_UNOP(log2);
+ break;
+ case kIeee754Float64Sin:
+ ASSEMBLE_IEEE754_UNOP(sin);
+ break;
+ case kIeee754Float64Tan:
+ ASSEMBLE_IEEE754_UNOP(tan);
+ break;
case kMipsAdd:
__ Addu(i.OutputRegister(), i.InputRegister(0), i.InputOperand(1));
break;
@@ -938,6 +1008,11 @@
__ sub_s(i.OutputDoubleRegister(), i.InputDoubleRegister(0),
i.InputDoubleRegister(1));
break;
+ case kMipsSubPreserveNanS:
+ __ SubNanPreservePayloadAndSign_s(i.OutputDoubleRegister(),
+ i.InputDoubleRegister(0),
+ i.InputDoubleRegister(1));
+ break;
case kMipsMulS:
// TODO(plind): add special case: right op is -1.0, see arm port.
__ mul_s(i.OutputDoubleRegister(), i.InputDoubleRegister(0),
@@ -1004,6 +1079,11 @@
__ sub_d(i.OutputDoubleRegister(), i.InputDoubleRegister(0),
i.InputDoubleRegister(1));
break;
+ case kMipsSubPreserveNanD:
+ __ SubNanPreservePayloadAndSign_d(i.OutputDoubleRegister(),
+ i.InputDoubleRegister(0),
+ i.InputDoubleRegister(1));
+ break;
case kMipsMulD:
// TODO(plind): add special case: right op is -1.0, see arm port.
__ mul_d(i.OutputDoubleRegister(), i.InputDoubleRegister(0),
@@ -1233,6 +1313,20 @@
case kMipsFloat64InsertHighWord32:
__ FmoveHigh(i.OutputDoubleRegister(), i.InputRegister(1));
break;
+ case kMipsFloat64SilenceNaN: {
+ FPURegister value = i.InputDoubleRegister(0);
+ FPURegister result = i.OutputDoubleRegister();
+ Register scratch0 = i.TempRegister(0);
+ Label is_nan, not_nan;
+ __ BranchF(NULL, &is_nan, eq, value, value);
+ __ Branch(¬_nan);
+ __ bind(&is_nan);
+ __ LoadRoot(scratch0, Heap::kNanValueRootIndex);
+ __ ldc1(result, FieldMemOperand(scratch0, HeapNumber::kValueOffset));
+ __ bind(¬_nan);
+ break;
+ }
+
// ... more basic instructions ...
case kMipsLbu:
@@ -1292,7 +1386,13 @@
}
case kMipsStoreToStackSlot: {
if (instr->InputAt(0)->IsFPRegister()) {
- __ sdc1(i.InputDoubleRegister(0), MemOperand(sp, i.InputInt32(1)));
+ LocationOperand* op = LocationOperand::cast(instr->InputAt(0));
+ if (op->representation() == MachineRepresentation::kFloat64) {
+ __ sdc1(i.InputDoubleRegister(0), MemOperand(sp, i.InputInt32(1)));
+ } else {
+ DCHECK_EQ(MachineRepresentation::kFloat32, op->representation());
+ __ swc1(i.InputSingleRegister(0), MemOperand(sp, i.InputInt32(1)));
+ }
} else {
__ sw(i.InputRegister(0), MemOperand(sp, i.InputInt32(1)));
}
@@ -1804,6 +1904,7 @@
switch (src.type()) {
case Constant::kInt32:
if (src.rmode() == RelocInfo::WASM_MEMORY_REFERENCE ||
+ src.rmode() == RelocInfo::WASM_GLOBAL_REFERENCE ||
src.rmode() == RelocInfo::WASM_MEMORY_SIZE_REFERENCE) {
__ li(dst, Operand(src.ToInt32(), src.rmode()));
} else {
@@ -1872,7 +1973,13 @@
DCHECK(destination->IsFPRegister() || destination->IsFPStackSlot());
MemOperand src = g.ToMemOperand(source);
if (destination->IsFPRegister()) {
- __ ldc1(g.ToDoubleRegister(destination), src);
+ LocationOperand* op = LocationOperand::cast(source);
+ if (op->representation() == MachineRepresentation::kFloat64) {
+ __ ldc1(g.ToDoubleRegister(destination), src);
+ } else {
+ DCHECK_EQ(MachineRepresentation::kFloat32, op->representation());
+ __ lwc1(g.ToDoubleRegister(destination), src);
+ }
} else {
FPURegister temp = kScratchDoubleReg;
__ ldc1(temp, src);
diff --git a/src/compiler/mips/instruction-codes-mips.h b/src/compiler/mips/instruction-codes-mips.h
index 5c36525..766a5b1 100644
--- a/src/compiler/mips/instruction-codes-mips.h
+++ b/src/compiler/mips/instruction-codes-mips.h
@@ -46,6 +46,7 @@
V(MipsCmpS) \
V(MipsAddS) \
V(MipsSubS) \
+ V(MipsSubPreserveNanS) \
V(MipsMulS) \
V(MipsDivS) \
V(MipsModS) \
@@ -56,6 +57,7 @@
V(MipsCmpD) \
V(MipsAddD) \
V(MipsSubD) \
+ V(MipsSubPreserveNanD) \
V(MipsMulD) \
V(MipsDivD) \
V(MipsModD) \
@@ -106,6 +108,7 @@
V(MipsFloat64ExtractHighWord32) \
V(MipsFloat64InsertLowWord32) \
V(MipsFloat64InsertHighWord32) \
+ V(MipsFloat64SilenceNaN) \
V(MipsFloat64Max) \
V(MipsFloat64Min) \
V(MipsFloat32Max) \
diff --git a/src/compiler/mips/instruction-selector-mips.cc b/src/compiler/mips/instruction-selector-mips.cc
index cccb39a..c95613e 100644
--- a/src/compiler/mips/instruction-selector-mips.cc
+++ b/src/compiler/mips/instruction-selector-mips.cc
@@ -755,7 +755,7 @@
}
void InstructionSelector::VisitFloat32SubPreserveNan(Node* node) {
- VisitRRR(this, kMipsSubS, node);
+ VisitRRR(this, kMipsSubPreserveNanS, node);
}
void InstructionSelector::VisitFloat64Sub(Node* node) {
@@ -777,7 +777,7 @@
}
void InstructionSelector::VisitFloat64SubPreserveNan(Node* node) {
- VisitRRR(this, kMipsSubD, node);
+ VisitRRR(this, kMipsSubPreserveNanD, node);
}
void InstructionSelector::VisitFloat32Mul(Node* node) {
@@ -876,7 +876,6 @@
VisitRR(this, kMipsAbsD, node);
}
-
void InstructionSelector::VisitFloat32Sqrt(Node* node) {
VisitRR(this, kMipsSqrtS, node);
}
@@ -931,6 +930,24 @@
VisitRR(this, kMipsFloat64RoundTiesEven, node);
}
+void InstructionSelector::VisitFloat32Neg(Node* node) { UNREACHABLE(); }
+
+void InstructionSelector::VisitFloat64Neg(Node* node) { UNREACHABLE(); }
+
+void InstructionSelector::VisitFloat64Ieee754Binop(Node* node,
+ InstructionCode opcode) {
+ MipsOperandGenerator g(this);
+ Emit(opcode, g.DefineAsFixed(node, f0), g.UseFixed(node->InputAt(0), f12),
+ g.UseFixed(node->InputAt(1), f14))
+ ->MarkAsCall();
+}
+
+void InstructionSelector::VisitFloat64Ieee754Unop(Node* node,
+ InstructionCode opcode) {
+ MipsOperandGenerator g(this);
+ Emit(opcode, g.DefineAsFixed(node, f0), g.UseFixed(node->InputAt(0), f12))
+ ->MarkAsCall();
+}
void InstructionSelector::EmitPrepareArguments(
ZoneVector<PushParameter>* arguments, const CallDescriptor* descriptor,
@@ -1454,6 +1471,14 @@
g.UseRegister(left), g.UseRegister(right));
}
+void InstructionSelector::VisitFloat64SilenceNaN(Node* node) {
+ MipsOperandGenerator g(this);
+ Node* left = node->InputAt(0);
+ InstructionOperand temps[] = {g.TempRegister()};
+ Emit(kMipsFloat64SilenceNaN, g.DefineSameAsFirst(node), g.UseRegister(left),
+ arraysize(temps), temps);
+}
+
void InstructionSelector::VisitAtomicLoad(Node* node) {
LoadRepresentation load_rep = LoadRepresentationOf(node->op());
MipsOperandGenerator g(this);
@@ -1548,6 +1573,20 @@
MachineOperatorBuilder::kFloat32RoundTiesEven;
}
+// static
+MachineOperatorBuilder::AlignmentRequirements
+InstructionSelector::AlignmentRequirements() {
+ if (IsMipsArchVariant(kMips32r6)) {
+ return MachineOperatorBuilder::AlignmentRequirements::
+ FullUnalignedAccessSupport();
+ } else {
+ DCHECK(IsMipsArchVariant(kLoongson) || IsMipsArchVariant(kMips32r1) ||
+ IsMipsArchVariant(kMips32r2));
+ return MachineOperatorBuilder::AlignmentRequirements::
+ NoUnalignedAccessSupport();
+ }
+}
+
} // namespace compiler
} // namespace internal
} // namespace v8