Merge V8 5.3.332.45. DO NOT MERGE
Test: Manual
FPIIM-449
Change-Id: Id3254828b068abdea3cb10442e0172a8c9a98e03
(cherry picked from commit 13e2dadd00298019ed862f2b2fc5068bba730bcf)
diff --git a/src/mips64/assembler-mips64.h b/src/mips64/assembler-mips64.h
index f93bc48..ff3611d 100644
--- a/src/mips64/assembler-mips64.h
+++ b/src/mips64/assembler-mips64.h
@@ -125,8 +125,6 @@
return r;
}
- const char* ToString();
- bool IsAllocatable() const;
bool is_valid() const { return 0 <= reg_code && reg_code < kNumRegisters; }
bool is(Register reg) const { return reg_code == reg.reg_code; }
int code() const {
@@ -155,6 +153,8 @@
Register ToRegister(int num);
+static const bool kSimpleFPAliasing = true;
+
// Coprocessor register.
struct FPURegister {
enum Code {
@@ -173,8 +173,6 @@
// to number of 32-bit FPU regs, but kNumAllocatableRegisters refers to
// number of Double regs (64-bit regs, or FPU-reg-pairs).
- const char* ToString();
- bool IsAllocatable() const;
bool is_valid() const { return 0 <= reg_code && reg_code < kMaxNumRegisters; }
bool is(FPURegister reg) const { return reg_code == reg.reg_code; }
FPURegister low() const {
@@ -907,6 +905,12 @@
void align(Register rd, Register rs, Register rt, uint8_t bp);
void dalign(Register rd, Register rs, Register rt, uint8_t bp);
+ void wsbh(Register rd, Register rt);
+ void dsbh(Register rd, Register rt);
+ void dshd(Register rd, Register rt);
+ void seh(Register rd, Register rt);
+ void seb(Register rd, Register rt);
+
// --------Coprocessor-instructions----------------
// Load, store, and move.