Merge V8 5.3.332.45. DO NOT MERGE
Test: Manual
FPIIM-449
Change-Id: Id3254828b068abdea3cb10442e0172a8c9a98e03
(cherry picked from commit 13e2dadd00298019ed862f2b2fc5068bba730bcf)
diff --git a/src/register-configuration.h b/src/register-configuration.h
index c07106e..25f3ef5 100644
--- a/src/register-configuration.h
+++ b/src/register-configuration.h
@@ -6,6 +6,7 @@
#define V8_COMPILER_REGISTER_CONFIGURATION_H_
#include "src/base/macros.h"
+#include "src/machine-type.h"
namespace v8 {
namespace internal {
@@ -14,29 +15,35 @@
// for instruction creation.
class RegisterConfiguration {
public:
- // Define the optimized compiler selector for register configuration
- // selection.
- //
- // TODO(X87): This distinction in RegisterConfigurations is temporary
- // until x87 TF supports all of the registers that Crankshaft does.
- enum CompilerSelector { CRANKSHAFT, TURBOFAN };
+ enum AliasingKind {
+ // Registers alias a single register of every other size (e.g. Intel).
+ OVERLAP,
+ // Registers alias two registers of the next smaller size (e.g. ARM).
+ COMBINE
+ };
// Architecture independent maxes.
static const int kMaxGeneralRegisters = 32;
static const int kMaxFPRegisters = 32;
- static const RegisterConfiguration* ArchDefault(CompilerSelector compiler);
+ // Default RegisterConfigurations for the target architecture.
+ // TODO(X87): This distinction in RegisterConfigurations is temporary
+ // until x87 TF supports all of the registers that Crankshaft does.
+ static const RegisterConfiguration* Crankshaft();
+ static const RegisterConfiguration* Turbofan();
RegisterConfiguration(int num_general_registers, int num_double_registers,
int num_allocatable_general_registers,
int num_allocatable_double_registers,
- int num_allocatable_aliased_double_registers,
const int* allocatable_general_codes,
const int* allocatable_double_codes,
+ AliasingKind fp_aliasing_kind,
char const* const* general_names,
+ char const* const* float_names,
char const* const* double_names);
int num_general_registers() const { return num_general_registers_; }
+ int num_float_registers() const { return num_float_registers_; }
int num_double_registers() const { return num_double_registers_; }
int num_allocatable_general_registers() const {
return num_allocatable_general_registers_;
@@ -44,12 +51,10 @@
int num_allocatable_double_registers() const {
return num_allocatable_double_registers_;
}
- // TODO(turbofan): This is a temporary work-around required because our
- // register allocator does not yet support the aliasing of single/double
- // registers on ARM.
- int num_allocatable_aliased_double_registers() const {
- return num_allocatable_aliased_double_registers_;
+ int num_allocatable_float_registers() const {
+ return num_allocatable_float_registers_;
}
+ AliasingKind fp_aliasing_kind() const { return fp_aliasing_kind_; }
int32_t allocatable_general_codes_mask() const {
return allocatable_general_codes_mask_;
}
@@ -59,12 +64,27 @@
int GetAllocatableGeneralCode(int index) const {
return allocatable_general_codes_[index];
}
+ bool IsAllocatableGeneralCode(int index) const {
+ return ((1 << index) & allocatable_general_codes_mask_) != 0;
+ }
int GetAllocatableDoubleCode(int index) const {
return allocatable_double_codes_[index];
}
+ bool IsAllocatableDoubleCode(int index) const {
+ return ((1 << index) & allocatable_double_codes_mask_) != 0;
+ }
+ int GetAllocatableFloatCode(int index) const {
+ return allocatable_float_codes_[index];
+ }
+ bool IsAllocatableFloatCode(int index) const {
+ return ((1 << index) & allocatable_float_codes_mask_) != 0;
+ }
const char* GetGeneralRegisterName(int code) const {
return general_register_names_[code];
}
+ const char* GetFloatRegisterName(int code) const {
+ return float_register_names_[code];
+ }
const char* GetDoubleRegisterName(int code) const {
return double_register_names_[code];
}
@@ -74,18 +94,38 @@
const int* allocatable_double_codes() const {
return allocatable_double_codes_;
}
+ const int* allocatable_float_codes() const {
+ return allocatable_float_codes_;
+ }
+
+ // Aliasing calculations for floating point registers, when fp_aliasing_kind()
+ // is COMBINE. Currently only implemented for kFloat32, or kFloat64 reps.
+ // Returns the number of aliases, and if > 0, alias_base_index is set to the
+ // index of the first alias.
+ int GetAliases(MachineRepresentation rep, int index,
+ MachineRepresentation other_rep, int* alias_base_index) const;
+ // Returns a value indicating whether two registers alias each other, when
+ // fp_aliasing_kind() is COMBINE. Currently only implemented for kFloat32, or
+ // kFloat64 reps.
+ bool AreAliases(MachineRepresentation rep, int index,
+ MachineRepresentation other_rep, int other_index) const;
private:
const int num_general_registers_;
+ int num_float_registers_;
const int num_double_registers_;
int num_allocatable_general_registers_;
int num_allocatable_double_registers_;
- int num_allocatable_aliased_double_registers_;
+ int num_allocatable_float_registers_;
int32_t allocatable_general_codes_mask_;
int32_t allocatable_double_codes_mask_;
+ int32_t allocatable_float_codes_mask_;
const int* allocatable_general_codes_;
const int* allocatable_double_codes_;
+ int allocatable_float_codes_[kMaxFPRegisters];
+ AliasingKind fp_aliasing_kind_;
char const* const* general_register_names_;
+ char const* const* float_register_names_;
char const* const* double_register_names_;
};