Merge V8 5.2.361.47 DO NOT MERGE
https://chromium.googlesource.com/v8/v8/+/5.2.361.47
FPIIM-449
Change-Id: Ibec421b85a9b88cb3a432ada642e469fe7e78346
(cherry picked from commit bcf72ee8e3b26f1d0726869c7ddb3921c68b09a8)
diff --git a/src/compiler/register-allocator.cc b/src/compiler/register-allocator.cc
index 82faf75..4683672 100644
--- a/src/compiler/register-allocator.cc
+++ b/src/compiler/register-allocator.cc
@@ -26,23 +26,22 @@
}
int GetRegisterCount(const RegisterConfiguration* cfg, RegisterKind kind) {
- return kind == DOUBLE_REGISTERS ? cfg->num_double_registers()
- : cfg->num_general_registers();
+ return kind == FP_REGISTERS ? cfg->num_double_registers()
+ : cfg->num_general_registers();
}
int GetAllocatableRegisterCount(const RegisterConfiguration* cfg,
RegisterKind kind) {
- return kind == DOUBLE_REGISTERS
- ? cfg->num_allocatable_aliased_double_registers()
- : cfg->num_allocatable_general_registers();
+ return kind == FP_REGISTERS ? cfg->num_allocatable_aliased_double_registers()
+ : cfg->num_allocatable_general_registers();
}
const int* GetAllocatableRegisterCodes(const RegisterConfiguration* cfg,
RegisterKind kind) {
- return kind == DOUBLE_REGISTERS ? cfg->allocatable_double_codes()
- : cfg->allocatable_general_codes();
+ return kind == FP_REGISTERS ? cfg->allocatable_double_codes()
+ : cfg->allocatable_general_codes();
}
@@ -81,7 +80,7 @@
bool IsOutputDoubleRegisterOf(Instruction* instr, DoubleRegister reg) {
for (size_t i = 0; i < instr->OutputCount(); i++) {
InstructionOperand* output = instr->OutputAt(i);
- if (output->IsDoubleRegister() &&
+ if (output->IsFPRegister() &&
LocationOperand::cast(output)->GetDoubleRegister().is(reg)) {
return true;
}
@@ -351,10 +350,10 @@
case InstructionOperand::UNALLOCATED:
return UsePositionHintType::kUnresolved;
case InstructionOperand::ALLOCATED:
- if (op.IsRegister() || op.IsDoubleRegister()) {
+ if (op.IsRegister() || op.IsFPRegister()) {
return UsePositionHintType::kOperand;
} else {
- DCHECK(op.IsStackSlot() || op.IsDoubleStackSlot());
+ DCHECK(op.IsStackSlot() || op.IsFPStackSlot());
return UsePositionHintType::kNone;
}
case InstructionOperand::INVALID:
@@ -489,8 +488,7 @@
RegisterKind LiveRange::kind() const {
- return IsFloatingPoint(representation()) ? DOUBLE_REGISTERS
- : GENERAL_REGISTERS;
+ return IsFloatingPoint(representation()) ? FP_REGISTERS : GENERAL_REGISTERS;
}
@@ -728,11 +726,11 @@
if (!pos->HasOperand()) continue;
switch (pos->type()) {
case UsePositionType::kRequiresSlot:
- DCHECK(spill_op.IsStackSlot() || spill_op.IsDoubleStackSlot());
+ DCHECK(spill_op.IsStackSlot() || spill_op.IsFPStackSlot());
InstructionOperand::ReplaceWith(pos->operand(), &spill_op);
break;
case UsePositionType::kRequiresRegister:
- DCHECK(op.IsRegister() || op.IsDoubleRegister());
+ DCHECK(op.IsRegister() || op.IsFPRegister());
// Fall through.
case UsePositionType::kAny:
InstructionOperand::ReplaceWith(pos->operand(), &op);
@@ -1400,10 +1398,6 @@
debug_name_(debug_name),
config_(config),
phi_map_(allocation_zone()),
- allocatable_codes_(this->config()->num_general_registers(), -1,
- allocation_zone()),
- allocatable_double_codes_(this->config()->num_double_registers(), -1,
- allocation_zone()),
live_in_sets_(code->InstructionBlockCount(), nullptr, allocation_zone()),
live_out_sets_(code->InstructionBlockCount(), nullptr, allocation_zone()),
live_ranges_(code->VirtualRegisterCount() * 2, nullptr,
@@ -1418,10 +1412,6 @@
assigned_double_registers_(nullptr),
virtual_register_count_(code->VirtualRegisterCount()),
preassigned_slot_ranges_(zone) {
- DCHECK(this->config()->num_general_registers() <=
- RegisterConfiguration::kMaxGeneralRegisters);
- DCHECK(this->config()->num_double_registers() <=
- RegisterConfiguration::kMaxDoubleRegisters);
assigned_registers_ = new (code_zone())
BitVector(this->config()->num_general_registers(), code_zone());
assigned_double_registers_ = new (code_zone())
@@ -1591,7 +1581,7 @@
void RegisterAllocationData::MarkAllocated(RegisterKind kind, int index) {
- if (kind == DOUBLE_REGISTERS) {
+ if (kind == FP_REGISTERS) {
assigned_double_registers_->Add(index);
} else {
DCHECK(kind == GENERAL_REGISTERS);
@@ -1942,7 +1932,7 @@
MachineRepresentation::kFloat64);
DCHECK(result->IsFixed());
result->set_assigned_register(index);
- data()->MarkAllocated(DOUBLE_REGISTERS, index);
+ data()->MarkAllocated(FP_REGISTERS, index);
data()->fixed_double_live_ranges()[index] = result;
}
return result;
@@ -1959,7 +1949,7 @@
} else if (operand->IsRegister()) {
return FixedLiveRangeFor(
LocationOperand::cast(operand)->GetRegister().code());
- } else if (operand->IsDoubleRegister()) {
+ } else if (operand->IsFPRegister()) {
return FixedDoubleLiveRangeFor(
LocationOperand::cast(operand)->GetDoubleRegister().code());
} else {
@@ -2590,8 +2580,8 @@
const ZoneVector<TopLevelLiveRange*>& RegisterAllocator::GetFixedRegisters()
const {
- return mode() == DOUBLE_REGISTERS ? data()->fixed_double_live_ranges()
- : data()->fixed_live_ranges();
+ return mode() == FP_REGISTERS ? data()->fixed_double_live_ranges()
+ : data()->fixed_live_ranges();
}
@@ -2616,7 +2606,7 @@
inactive_live_ranges().reserve(8);
// TryAllocateFreeReg and AllocateBlockedReg assume this
// when allocating local arrays.
- DCHECK(RegisterConfiguration::kMaxDoubleRegisters >=
+ DCHECK(RegisterConfiguration::kMaxFPRegisters >=
this->data()->config()->num_general_registers());
}
@@ -2813,7 +2803,7 @@
bool LinearScanAllocator::TryAllocateFreeReg(LiveRange* current) {
- LifetimePosition free_until_pos[RegisterConfiguration::kMaxDoubleRegisters];
+ LifetimePosition free_until_pos[RegisterConfiguration::kMaxFPRegisters];
for (int i = 0; i < num_registers(); i++) {
free_until_pos[i] = LifetimePosition::MaxPosition();
@@ -2899,8 +2889,8 @@
return;
}
- LifetimePosition use_pos[RegisterConfiguration::kMaxDoubleRegisters];
- LifetimePosition block_pos[RegisterConfiguration::kMaxDoubleRegisters];
+ LifetimePosition use_pos[RegisterConfiguration::kMaxFPRegisters];
+ LifetimePosition block_pos[RegisterConfiguration::kMaxFPRegisters];
for (int i = 0; i < num_registers(); i++) {
use_pos[i] = block_pos[i] = LifetimePosition::MaxPosition();
@@ -2947,9 +2937,13 @@
LifetimePosition pos = use_pos[reg];
if (pos < register_use->pos()) {
- // All registers are blocked before the first use that requires a register.
- // Spill starting part of live range up to that use.
- SpillBetween(current, current->Start(), register_use->pos());
+ if (LifetimePosition::ExistsGapPositionBetween(current->Start(),
+ register_use->pos())) {
+ SpillBetween(current, current->Start(), register_use->pos());
+ } else {
+ SetLiveRangeAssignedRegister(current, reg);
+ SplitAndSpillIntersecting(current);
+ }
return;
}
@@ -2994,6 +2988,8 @@
// live-ranges: ranges are allocated in order of their start positions,
// ranges are retired from active/inactive when the start of the
// current live-range is larger than their end.
+ DCHECK(LifetimePosition::ExistsGapPositionBetween(current->Start(),
+ next_pos->pos()));
SpillBetweenUntil(range, spill_pos, current->Start(), next_pos->pos());
}
ActiveToHandled(range);
@@ -3092,7 +3088,7 @@
? range->TopLevel()->GetSpillRange()
: data()->AssignSpillRangeToLiveRange(range->TopLevel());
bool merged = first_op_spill->TryMerge(spill_range);
- CHECK(merged);
+ if (!merged) return false;
Spill(range);
return true;
} else if (pos->pos() > range->Start().NextStart()) {
@@ -3101,7 +3097,7 @@
? range->TopLevel()->GetSpillRange()
: data()->AssignSpillRangeToLiveRange(range->TopLevel());
bool merged = first_op_spill->TryMerge(spill_range);
- CHECK(merged);
+ if (!merged) return false;
SpillBetween(range, range->Start(), pos->pos());
DCHECK(UnhandledIsSorted());
return true;
@@ -3405,7 +3401,8 @@
BitVector* live = live_in_sets[block->rpo_number().ToInt()];
BitVector::Iterator iterator(live);
while (!iterator.Done()) {
- LiveRangeBoundArray* array = finder.ArrayFor(iterator.Current());
+ int vreg = iterator.Current();
+ LiveRangeBoundArray* array = finder.ArrayFor(vreg);
for (const RpoNumber& pred : block->predecessors()) {
FindResult result;
const InstructionBlock* pred_block = code()->InstructionBlockAt(pred);
@@ -3622,6 +3619,7 @@
worklist.push(iterator.Current());
}
+ ZoneSet<std::pair<RpoNumber, int>> done_moves(temp_zone);
// Seek the deferred blocks that dominate locations requiring spill operands,
// and spill there. We only need to spill at the start of such blocks.
BitVector done_blocks(
@@ -3648,10 +3646,15 @@
InstructionOperand pred_op = bound->range_->GetAssignedOperand();
- data()->AddGapMove(spill_block->first_instruction_index(),
- Instruction::GapPosition::START, pred_op,
- spill_operand);
- spill_block->mark_needs_frame();
+ RpoNumber spill_block_number = spill_block->rpo_number();
+ if (done_moves.find(std::make_pair(
+ spill_block_number, range->vreg())) == done_moves.end()) {
+ data()->AddGapMove(spill_block->first_instruction_index(),
+ Instruction::GapPosition::START, pred_op,
+ spill_operand);
+ done_moves.insert(std::make_pair(spill_block_number, range->vreg()));
+ spill_block->mark_needs_frame();
+ }
}
}
}