Merge V8 5.2.361.47 DO NOT MERGE
https://chromium.googlesource.com/v8/v8/+/5.2.361.47
FPIIM-449
Change-Id: Ibec421b85a9b88cb3a432ada642e469fe7e78346
(cherry picked from commit bcf72ee8e3b26f1d0726869c7ddb3921c68b09a8)
diff --git a/src/mips/assembler-mips.h b/src/mips/assembler-mips.h
index 886ac6c..c595cc9 100644
--- a/src/mips/assembler-mips.h
+++ b/src/mips/assembler-mips.h
@@ -63,6 +63,8 @@
V(f16) V(f17) V(f18) V(f19) V(f20) V(f21) V(f22) V(f23) \
V(f24) V(f25) V(f26) V(f27) V(f28) V(f29) V(f30) V(f31)
+#define FLOAT_REGISTERS DOUBLE_REGISTERS
+
#define ALLOCATABLE_DOUBLE_REGISTERS(V) \
V(f0) V(f2) V(f4) V(f6) V(f8) V(f10) V(f12) V(f14) \
V(f16) V(f18) V(f20) V(f22) V(f24) V(f26)
@@ -154,7 +156,7 @@
Register ToRegister(int num);
// Coprocessor register.
-struct DoubleRegister {
+struct FPURegister {
enum Code {
#define REGISTER_CODE(R) kCode_##R,
DOUBLE_REGISTERS(REGISTER_CODE)
@@ -174,19 +176,19 @@
const char* ToString();
bool IsAllocatable() const;
bool is_valid() const { return 0 <= reg_code && reg_code < kMaxNumRegisters; }
- bool is(DoubleRegister reg) const { return reg_code == reg.reg_code; }
- DoubleRegister low() const {
+ bool is(FPURegister reg) const { return reg_code == reg.reg_code; }
+ FPURegister low() const {
// Find low reg of a Double-reg pair, which is the reg itself.
DCHECK(reg_code % 2 == 0); // Specified Double reg must be even.
- DoubleRegister reg;
+ FPURegister reg;
reg.reg_code = reg_code;
DCHECK(reg.is_valid());
return reg;
}
- DoubleRegister high() const {
+ FPURegister high() const {
// Find high reg of a Doubel-reg pair, which is reg + 1.
DCHECK(reg_code % 2 == 0); // Specified Double reg must be even.
- DoubleRegister reg;
+ FPURegister reg;
reg.reg_code = reg_code + 1;
DCHECK(reg.is_valid());
return reg;
@@ -201,8 +203,8 @@
return 1 << reg_code;
}
- static DoubleRegister from_code(int code) {
- DoubleRegister r = {code};
+ static FPURegister from_code(int code) {
+ FPURegister r = {code};
return r;
}
void setcode(int f) {
@@ -227,8 +229,12 @@
// but it is not in common use. Someday we will want to support this in v8.)
// For O32 ABI, Floats and Doubles refer to same set of 32 32-bit registers.
-typedef DoubleRegister FPURegister;
-typedef DoubleRegister FloatRegister;
+typedef FPURegister FloatRegister;
+
+typedef FPURegister DoubleRegister;
+
+// TODO(mips) Define SIMD registers.
+typedef FPURegister Simd128Register;
const DoubleRegister no_freg = {-1};
@@ -304,9 +310,6 @@
const FPUControlRegister no_fpucreg = { kInvalidFPUControlRegister };
const FPUControlRegister FCSR = { kFCSRRegister };
-// TODO(mips) Define SIMD registers.
-typedef DoubleRegister Simd128Register;
-
// -----------------------------------------------------------------------------
// Machine instruction Operands.
@@ -799,6 +802,9 @@
void teq(Register rs, Register rt, uint16_t code);
void tne(Register rs, Register rt, uint16_t code);
+ // Memory barrier instruction.
+ void sync();
+
// Move from HI/LO register.
void mfhi(Register rd);
void mflo(Register rd);
@@ -1039,8 +1045,7 @@
// Record a deoptimization reason that can be used by a log or cpu profiler.
// Use --trace-deopt to enable.
- void RecordDeoptReason(const int reason, int raw_position);
-
+ void RecordDeoptReason(const int reason, int raw_position, int id);
static int RelocateInternalReference(RelocInfo::Mode rmode, byte* pc,
intptr_t pc_delta);
@@ -1158,10 +1163,15 @@
bool IsPrevInstrCompactBranch() { return prev_instr_compact_branch_; }
+ inline int UnboundLabelsCount() { return unbound_labels_count_; }
+
protected:
// Load Scaled Address instruction.
void lsa(Register rd, Register rt, Register rs, uint8_t sa);
+ // Helpers.
+ void LoadRegPlusOffsetToAt(const MemOperand& src);
+
// Relocation for a type-recording IC has the AST id added to it. This
// member variable is a way to pass the information from the call site to
// the relocation info.
@@ -1359,8 +1369,6 @@
void GenInstrJump(Opcode opcode,
uint32_t address);
- // Helpers.
- void LoadRegPlusOffsetToAt(const MemOperand& src);
// Labels.
void print(Label* L);