Update V8 to version 4.1.0.21
This is a cherry-pick of all commits up to and including the
4.1.0.21 cherry-pick in Chromium.
Original commit message:
Version 4.1.0.21 (cherry-pick)
Merged 206e9136bde0f2b5ae8cb77afbb1e7833e5bd412
Unlink pages from the space page list after evacuation.
BUG=430201
LOG=N
R=jkummerow@chromium.org
Review URL: https://codereview.chromium.org/953813002
Cr-Commit-Position: refs/branch-heads/4.1@{#22}
Cr-Branched-From: 2e08d2a7aa9d65d269d8c57aba82eb38a8cb0a18-refs/heads/candidates@{#25353}
---
FPIIM-449
Change-Id: I8c23c7bbb70772b4858fe8a47b64fa97ee0d1f8c
diff --git a/src/mips64/simulator-mips64.cc b/src/mips64/simulator-mips64.cc
index 4c74939..9899d47 100644
--- a/src/mips64/simulator-mips64.cc
+++ b/src/mips64/simulator-mips64.cc
@@ -2080,16 +2080,15 @@
case MFLO:
*alu_out = get_register(LO);
break;
- case MULT: // MULT == D_MUL_MUH.
- // TODO(plind) - Unify MULT/DMULT with single set of 64-bit HI/Lo
- // regs.
- // TODO(plind) - make the 32-bit MULT ops conform to spec regarding
- // checking of 32-bit input values, and un-define operations of HW.
- *i64hilo = static_cast<int64_t>((int32_t)rs) *
- static_cast<int64_t>((int32_t)rt);
+ case MULT: { // MULT == D_MUL_MUH.
+ int32_t rs_lo = static_cast<int32_t>(rs);
+ int32_t rt_lo = static_cast<int32_t>(rt);
+ *i64hilo = static_cast<int64_t>(rs_lo) * static_cast<int64_t>(rt_lo);
break;
+ }
case MULTU:
- *u64hilo = static_cast<uint64_t>(rs_u) * static_cast<uint64_t>(rt_u);
+ *u64hilo = static_cast<uint64_t>(rs_u & 0xffffffff) *
+ static_cast<uint64_t>(rt_u & 0xffffffff);
break;
case DMULT: // DMULT == D_MUL_MUH.
if (kArchVariant != kMips64r6) {
@@ -2231,7 +2230,7 @@
// Interpret sa field as 5-bit lsb of insert.
uint16_t lsb = sa;
uint16_t size = msb - lsb + 1;
- uint32_t mask = (1 << size) - 1;
+ uint64_t mask = (1ULL << size) - 1;
*alu_out = (rt_u & ~(mask << lsb)) | ((rs_u & mask) << lsb);
break;
}
@@ -2241,8 +2240,18 @@
// Interpret sa field as 5-bit lsb of extract.
uint16_t lsb = sa;
uint16_t size = msb + 1;
- uint32_t mask = (1 << size) - 1;
- *alu_out = (rs_u & (mask << lsb)) >> lsb;
+ uint64_t mask = (1ULL << size) - 1;
+ *alu_out = static_cast<int32_t>((rs_u & (mask << lsb)) >> lsb);
+ break;
+ }
+ case DEXT: { // Mips32r2 instruction.
+ // Interpret rd field as 5-bit msb of extract.
+ uint16_t msb = rd_reg;
+ // Interpret sa field as 5-bit lsb of extract.
+ uint16_t lsb = sa;
+ uint16_t size = msb + 1;
+ uint64_t mask = (1ULL << size) - 1;
+ *alu_out = static_cast<int64_t>((rs_u & (mask << lsb)) >> lsb);
break;
}
default:
@@ -2784,7 +2793,8 @@
TraceRegWr(alu_out);
break;
case EXT:
- // Ext instr leaves result in Rt, rather than Rd.
+ case DEXT:
+ // Dext/Ext instr leaves result in Rt, rather than Rd.
set_register(rt_reg, alu_out);
TraceRegWr(alu_out);
break;
@@ -2816,9 +2826,9 @@
int64_t ft = get_fpu_register(ft_reg);
// Zero extended immediate.
- uint32_t oe_imm16 = 0xffff & imm16;
+ uint64_t oe_imm16 = 0xffff & imm16;
// Sign extended immediate.
- int32_t se_imm16 = imm16;
+ int64_t se_imm16 = imm16;
// Get current pc.
int64_t current_pc = get_pc();