Upgrade V8 to 5.1.281.57 DO NOT MERGE
FPIIM-449
Change-Id: Id981b686b4d587ac31697662eb98bb34be42ad90
(cherry picked from commit 3b9bc31999c9787eb726ecdbfd5796bfdec32a18)
diff --git a/src/arm64/assembler-arm64.cc b/src/arm64/assembler-arm64.cc
index ea7a732..2471d5e 100644
--- a/src/arm64/assembler-arm64.cc
+++ b/src/arm64/assembler-arm64.cc
@@ -56,7 +56,10 @@
if (cpu.implementer() == base::CPU::NVIDIA &&
cpu.variant() == base::CPU::NVIDIA_DENVER &&
cpu.part() <= base::CPU::NVIDIA_DENVER_V10) {
- supported_ |= 1u << COHERENT_CACHE;
+ // TODO(jkummerow): This is turned off as an experiment to see if it
+ // affects crash rates. Keep an eye on crash reports and either remove
+ // coherent cache support permanently, or re-enable it!
+ // supported_ |= 1u << COHERENT_CACHE;
}
}
@@ -437,7 +440,8 @@
DCHECK(mode != RelocInfo::NONE32);
return RelocInfo::IsNone(mode) ||
- (!assm_->serializer_enabled() && (mode >= RelocInfo::CELL));
+ (!assm_->serializer_enabled() &&
+ (mode >= RelocInfo::FIRST_SHAREABLE_RELOC_MODE));
}
@@ -2871,7 +2875,7 @@
// We do not try to reuse pool constants.
RelocInfo rinfo(isolate(), reinterpret_cast<byte*>(pc_), rmode, data, NULL);
if (((rmode >= RelocInfo::COMMENT) &&
- (rmode <= RelocInfo::DEBUG_BREAK_SLOT_AT_CALL)) ||
+ (rmode <= RelocInfo::DEBUG_BREAK_SLOT_AT_TAIL_CALL)) ||
(rmode == RelocInfo::INTERNAL_REFERENCE) ||
(rmode == RelocInfo::CONST_POOL) || (rmode == RelocInfo::VENEER_POOL) ||
(rmode == RelocInfo::DEOPT_REASON) ||