| // Copyright 2014 the V8 project authors. All rights reserved. |
| // Use of this source code is governed by a BSD-style license that can be |
| // found in the LICENSE file. |
| |
| #include "src/base/adapters.h" |
| #include "src/compiler/instruction-selector-impl.h" |
| #include "src/compiler/node-matchers.h" |
| #include "src/compiler/node-properties.h" |
| |
| namespace v8 { |
| namespace internal { |
| namespace compiler { |
| |
| // Adds IA32-specific methods for generating operands. |
| class IA32OperandGenerator final : public OperandGenerator { |
| public: |
| explicit IA32OperandGenerator(InstructionSelector* selector) |
| : OperandGenerator(selector) {} |
| |
| InstructionOperand UseByteRegister(Node* node) { |
| // TODO(titzer): encode byte register use constraints. |
| return UseFixed(node, edx); |
| } |
| |
| InstructionOperand DefineAsByteRegister(Node* node) { |
| // TODO(titzer): encode byte register def constraints. |
| return DefineAsRegister(node); |
| } |
| |
| bool CanBeMemoryOperand(InstructionCode opcode, Node* node, Node* input, |
| int effect_level) { |
| if (input->opcode() != IrOpcode::kLoad || |
| !selector()->CanCover(node, input)) { |
| return false; |
| } |
| if (effect_level != selector()->GetEffectLevel(input)) { |
| return false; |
| } |
| MachineRepresentation rep = |
| LoadRepresentationOf(input->op()).representation(); |
| switch (opcode) { |
| case kIA32Cmp: |
| case kIA32Test: |
| return rep == MachineRepresentation::kWord32 || |
| rep == MachineRepresentation::kTagged; |
| case kIA32Cmp16: |
| case kIA32Test16: |
| return rep == MachineRepresentation::kWord16; |
| case kIA32Cmp8: |
| case kIA32Test8: |
| return rep == MachineRepresentation::kWord8; |
| default: |
| break; |
| } |
| return false; |
| } |
| |
| bool CanBeImmediate(Node* node) { |
| switch (node->opcode()) { |
| case IrOpcode::kInt32Constant: |
| case IrOpcode::kNumberConstant: |
| case IrOpcode::kExternalConstant: |
| case IrOpcode::kRelocatableInt32Constant: |
| case IrOpcode::kRelocatableInt64Constant: |
| return true; |
| case IrOpcode::kHeapConstant: { |
| // TODO(bmeurer): We must not dereference handles concurrently. If we |
| // really have to this here, then we need to find a way to put this |
| // information on the HeapConstant node already. |
| #if 0 |
| // Constants in new space cannot be used as immediates in V8 because |
| // the GC does not scan code objects when collecting the new generation. |
| Handle<HeapObject> value = OpParameter<Handle<HeapObject>>(node); |
| Isolate* isolate = value->GetIsolate(); |
| return !isolate->heap()->InNewSpace(*value); |
| #endif |
| } |
| default: |
| return false; |
| } |
| } |
| |
| AddressingMode GenerateMemoryOperandInputs(Node* index, int scale, Node* base, |
| Node* displacement_node, |
| InstructionOperand inputs[], |
| size_t* input_count) { |
| AddressingMode mode = kMode_MRI; |
| int32_t displacement = (displacement_node == nullptr) |
| ? 0 |
| : OpParameter<int32_t>(displacement_node); |
| if (base != nullptr) { |
| if (base->opcode() == IrOpcode::kInt32Constant) { |
| displacement += OpParameter<int32_t>(base); |
| base = nullptr; |
| } |
| } |
| if (base != nullptr) { |
| inputs[(*input_count)++] = UseRegister(base); |
| if (index != nullptr) { |
| DCHECK(scale >= 0 && scale <= 3); |
| inputs[(*input_count)++] = UseRegister(index); |
| if (displacement != 0) { |
| inputs[(*input_count)++] = TempImmediate(displacement); |
| static const AddressingMode kMRnI_modes[] = {kMode_MR1I, kMode_MR2I, |
| kMode_MR4I, kMode_MR8I}; |
| mode = kMRnI_modes[scale]; |
| } else { |
| static const AddressingMode kMRn_modes[] = {kMode_MR1, kMode_MR2, |
| kMode_MR4, kMode_MR8}; |
| mode = kMRn_modes[scale]; |
| } |
| } else { |
| if (displacement == 0) { |
| mode = kMode_MR; |
| } else { |
| inputs[(*input_count)++] = TempImmediate(displacement); |
| mode = kMode_MRI; |
| } |
| } |
| } else { |
| DCHECK(scale >= 0 && scale <= 3); |
| if (index != nullptr) { |
| inputs[(*input_count)++] = UseRegister(index); |
| if (displacement != 0) { |
| inputs[(*input_count)++] = TempImmediate(displacement); |
| static const AddressingMode kMnI_modes[] = {kMode_MRI, kMode_M2I, |
| kMode_M4I, kMode_M8I}; |
| mode = kMnI_modes[scale]; |
| } else { |
| static const AddressingMode kMn_modes[] = {kMode_MR, kMode_M2, |
| kMode_M4, kMode_M8}; |
| mode = kMn_modes[scale]; |
| } |
| } else { |
| inputs[(*input_count)++] = TempImmediate(displacement); |
| return kMode_MI; |
| } |
| } |
| return mode; |
| } |
| |
| AddressingMode GetEffectiveAddressMemoryOperand(Node* node, |
| InstructionOperand inputs[], |
| size_t* input_count) { |
| BaseWithIndexAndDisplacement32Matcher m(node, true); |
| DCHECK(m.matches()); |
| if ((m.displacement() == nullptr || CanBeImmediate(m.displacement()))) { |
| return GenerateMemoryOperandInputs(m.index(), m.scale(), m.base(), |
| m.displacement(), inputs, input_count); |
| } else { |
| inputs[(*input_count)++] = UseRegister(node->InputAt(0)); |
| inputs[(*input_count)++] = UseRegister(node->InputAt(1)); |
| return kMode_MR1; |
| } |
| } |
| |
| bool CanBeBetterLeftOperand(Node* node) const { |
| return !selector()->IsLive(node); |
| } |
| }; |
| |
| |
| namespace { |
| |
| void VisitRO(InstructionSelector* selector, Node* node, ArchOpcode opcode) { |
| IA32OperandGenerator g(selector); |
| selector->Emit(opcode, g.DefineAsRegister(node), g.Use(node->InputAt(0))); |
| } |
| |
| |
| void VisitRR(InstructionSelector* selector, Node* node, |
| InstructionCode opcode) { |
| IA32OperandGenerator g(selector); |
| selector->Emit(opcode, g.DefineAsRegister(node), |
| g.UseRegister(node->InputAt(0))); |
| } |
| |
| |
| void VisitRROFloat(InstructionSelector* selector, Node* node, |
| ArchOpcode avx_opcode, ArchOpcode sse_opcode) { |
| IA32OperandGenerator g(selector); |
| InstructionOperand operand0 = g.UseRegister(node->InputAt(0)); |
| InstructionOperand operand1 = g.Use(node->InputAt(1)); |
| if (selector->IsSupported(AVX)) { |
| selector->Emit(avx_opcode, g.DefineAsRegister(node), operand0, operand1); |
| } else { |
| selector->Emit(sse_opcode, g.DefineSameAsFirst(node), operand0, operand1); |
| } |
| } |
| |
| |
| void VisitFloatUnop(InstructionSelector* selector, Node* node, Node* input, |
| ArchOpcode avx_opcode, ArchOpcode sse_opcode) { |
| IA32OperandGenerator g(selector); |
| if (selector->IsSupported(AVX)) { |
| selector->Emit(avx_opcode, g.DefineAsRegister(node), g.Use(input)); |
| } else { |
| selector->Emit(sse_opcode, g.DefineSameAsFirst(node), g.UseRegister(input)); |
| } |
| } |
| |
| |
| } // namespace |
| |
| |
| void InstructionSelector::VisitLoad(Node* node) { |
| LoadRepresentation load_rep = LoadRepresentationOf(node->op()); |
| |
| ArchOpcode opcode = kArchNop; |
| switch (load_rep.representation()) { |
| case MachineRepresentation::kFloat32: |
| opcode = kIA32Movss; |
| break; |
| case MachineRepresentation::kFloat64: |
| opcode = kIA32Movsd; |
| break; |
| case MachineRepresentation::kBit: // Fall through. |
| case MachineRepresentation::kWord8: |
| opcode = load_rep.IsSigned() ? kIA32Movsxbl : kIA32Movzxbl; |
| break; |
| case MachineRepresentation::kWord16: |
| opcode = load_rep.IsSigned() ? kIA32Movsxwl : kIA32Movzxwl; |
| break; |
| case MachineRepresentation::kTagged: // Fall through. |
| case MachineRepresentation::kWord32: |
| opcode = kIA32Movl; |
| break; |
| case MachineRepresentation::kWord64: // Fall through. |
| case MachineRepresentation::kSimd128: // Fall through. |
| case MachineRepresentation::kNone: |
| UNREACHABLE(); |
| return; |
| } |
| |
| IA32OperandGenerator g(this); |
| InstructionOperand outputs[1]; |
| outputs[0] = g.DefineAsRegister(node); |
| InstructionOperand inputs[3]; |
| size_t input_count = 0; |
| AddressingMode mode = |
| g.GetEffectiveAddressMemoryOperand(node, inputs, &input_count); |
| InstructionCode code = opcode | AddressingModeField::encode(mode); |
| Emit(code, 1, outputs, input_count, inputs); |
| } |
| |
| |
| void InstructionSelector::VisitStore(Node* node) { |
| IA32OperandGenerator g(this); |
| Node* base = node->InputAt(0); |
| Node* index = node->InputAt(1); |
| Node* value = node->InputAt(2); |
| |
| StoreRepresentation store_rep = StoreRepresentationOf(node->op()); |
| WriteBarrierKind write_barrier_kind = store_rep.write_barrier_kind(); |
| MachineRepresentation rep = store_rep.representation(); |
| |
| if (write_barrier_kind != kNoWriteBarrier) { |
| DCHECK_EQ(MachineRepresentation::kTagged, rep); |
| AddressingMode addressing_mode; |
| InstructionOperand inputs[3]; |
| size_t input_count = 0; |
| inputs[input_count++] = g.UseUniqueRegister(base); |
| if (g.CanBeImmediate(index)) { |
| inputs[input_count++] = g.UseImmediate(index); |
| addressing_mode = kMode_MRI; |
| } else { |
| inputs[input_count++] = g.UseUniqueRegister(index); |
| addressing_mode = kMode_MR1; |
| } |
| inputs[input_count++] = g.UseUniqueRegister(value); |
| RecordWriteMode record_write_mode = RecordWriteMode::kValueIsAny; |
| switch (write_barrier_kind) { |
| case kNoWriteBarrier: |
| UNREACHABLE(); |
| break; |
| case kMapWriteBarrier: |
| record_write_mode = RecordWriteMode::kValueIsMap; |
| break; |
| case kPointerWriteBarrier: |
| record_write_mode = RecordWriteMode::kValueIsPointer; |
| break; |
| case kFullWriteBarrier: |
| record_write_mode = RecordWriteMode::kValueIsAny; |
| break; |
| } |
| InstructionOperand temps[] = {g.TempRegister(), g.TempRegister()}; |
| size_t const temp_count = arraysize(temps); |
| InstructionCode code = kArchStoreWithWriteBarrier; |
| code |= AddressingModeField::encode(addressing_mode); |
| code |= MiscField::encode(static_cast<int>(record_write_mode)); |
| Emit(code, 0, nullptr, input_count, inputs, temp_count, temps); |
| } else { |
| ArchOpcode opcode = kArchNop; |
| switch (rep) { |
| case MachineRepresentation::kFloat32: |
| opcode = kIA32Movss; |
| break; |
| case MachineRepresentation::kFloat64: |
| opcode = kIA32Movsd; |
| break; |
| case MachineRepresentation::kBit: // Fall through. |
| case MachineRepresentation::kWord8: |
| opcode = kIA32Movb; |
| break; |
| case MachineRepresentation::kWord16: |
| opcode = kIA32Movw; |
| break; |
| case MachineRepresentation::kTagged: // Fall through. |
| case MachineRepresentation::kWord32: |
| opcode = kIA32Movl; |
| break; |
| case MachineRepresentation::kWord64: // Fall through. |
| case MachineRepresentation::kSimd128: // Fall through. |
| case MachineRepresentation::kNone: |
| UNREACHABLE(); |
| return; |
| } |
| |
| InstructionOperand val; |
| if (g.CanBeImmediate(value)) { |
| val = g.UseImmediate(value); |
| } else if (rep == MachineRepresentation::kWord8 || |
| rep == MachineRepresentation::kBit) { |
| val = g.UseByteRegister(value); |
| } else { |
| val = g.UseRegister(value); |
| } |
| |
| InstructionOperand inputs[4]; |
| size_t input_count = 0; |
| AddressingMode addressing_mode = |
| g.GetEffectiveAddressMemoryOperand(node, inputs, &input_count); |
| InstructionCode code = |
| opcode | AddressingModeField::encode(addressing_mode); |
| inputs[input_count++] = val; |
| Emit(code, 0, static_cast<InstructionOperand*>(nullptr), input_count, |
| inputs); |
| } |
| } |
| |
| |
| void InstructionSelector::VisitCheckedLoad(Node* node) { |
| CheckedLoadRepresentation load_rep = CheckedLoadRepresentationOf(node->op()); |
| IA32OperandGenerator g(this); |
| Node* const buffer = node->InputAt(0); |
| Node* const offset = node->InputAt(1); |
| Node* const length = node->InputAt(2); |
| ArchOpcode opcode = kArchNop; |
| switch (load_rep.representation()) { |
| case MachineRepresentation::kWord8: |
| opcode = load_rep.IsSigned() ? kCheckedLoadInt8 : kCheckedLoadUint8; |
| break; |
| case MachineRepresentation::kWord16: |
| opcode = load_rep.IsSigned() ? kCheckedLoadInt16 : kCheckedLoadUint16; |
| break; |
| case MachineRepresentation::kWord32: |
| opcode = kCheckedLoadWord32; |
| break; |
| case MachineRepresentation::kFloat32: |
| opcode = kCheckedLoadFloat32; |
| break; |
| case MachineRepresentation::kFloat64: |
| opcode = kCheckedLoadFloat64; |
| break; |
| case MachineRepresentation::kBit: // Fall through. |
| case MachineRepresentation::kTagged: // Fall through. |
| case MachineRepresentation::kWord64: // Fall through. |
| case MachineRepresentation::kSimd128: // Fall through. |
| case MachineRepresentation::kNone: |
| UNREACHABLE(); |
| return; |
| } |
| InstructionOperand offset_operand = g.UseRegister(offset); |
| InstructionOperand length_operand = |
| g.CanBeImmediate(length) ? g.UseImmediate(length) : g.UseRegister(length); |
| if (g.CanBeImmediate(buffer)) { |
| Emit(opcode | AddressingModeField::encode(kMode_MRI), |
| g.DefineAsRegister(node), offset_operand, length_operand, |
| offset_operand, g.UseImmediate(buffer)); |
| } else { |
| Emit(opcode | AddressingModeField::encode(kMode_MR1), |
| g.DefineAsRegister(node), offset_operand, length_operand, |
| g.UseRegister(buffer), offset_operand); |
| } |
| } |
| |
| |
| void InstructionSelector::VisitCheckedStore(Node* node) { |
| MachineRepresentation rep = CheckedStoreRepresentationOf(node->op()); |
| IA32OperandGenerator g(this); |
| Node* const buffer = node->InputAt(0); |
| Node* const offset = node->InputAt(1); |
| Node* const length = node->InputAt(2); |
| Node* const value = node->InputAt(3); |
| ArchOpcode opcode = kArchNop; |
| switch (rep) { |
| case MachineRepresentation::kWord8: |
| opcode = kCheckedStoreWord8; |
| break; |
| case MachineRepresentation::kWord16: |
| opcode = kCheckedStoreWord16; |
| break; |
| case MachineRepresentation::kWord32: |
| opcode = kCheckedStoreWord32; |
| break; |
| case MachineRepresentation::kFloat32: |
| opcode = kCheckedStoreFloat32; |
| break; |
| case MachineRepresentation::kFloat64: |
| opcode = kCheckedStoreFloat64; |
| break; |
| case MachineRepresentation::kBit: // Fall through. |
| case MachineRepresentation::kTagged: // Fall through. |
| case MachineRepresentation::kWord64: // Fall through. |
| case MachineRepresentation::kSimd128: // Fall through. |
| case MachineRepresentation::kNone: |
| UNREACHABLE(); |
| return; |
| } |
| InstructionOperand value_operand = |
| g.CanBeImmediate(value) ? g.UseImmediate(value) |
| : ((rep == MachineRepresentation::kWord8 || |
| rep == MachineRepresentation::kBit) |
| ? g.UseByteRegister(value) |
| : g.UseRegister(value)); |
| InstructionOperand offset_operand = g.UseRegister(offset); |
| InstructionOperand length_operand = |
| g.CanBeImmediate(length) ? g.UseImmediate(length) : g.UseRegister(length); |
| if (g.CanBeImmediate(buffer)) { |
| Emit(opcode | AddressingModeField::encode(kMode_MRI), g.NoOutput(), |
| offset_operand, length_operand, value_operand, offset_operand, |
| g.UseImmediate(buffer)); |
| } else { |
| Emit(opcode | AddressingModeField::encode(kMode_MR1), g.NoOutput(), |
| offset_operand, length_operand, value_operand, g.UseRegister(buffer), |
| offset_operand); |
| } |
| } |
| |
| namespace { |
| |
| // Shared routine for multiple binary operations. |
| void VisitBinop(InstructionSelector* selector, Node* node, |
| InstructionCode opcode, FlagsContinuation* cont) { |
| IA32OperandGenerator g(selector); |
| Int32BinopMatcher m(node); |
| Node* left = m.left().node(); |
| Node* right = m.right().node(); |
| InstructionOperand inputs[4]; |
| size_t input_count = 0; |
| InstructionOperand outputs[2]; |
| size_t output_count = 0; |
| |
| // TODO(turbofan): match complex addressing modes. |
| if (left == right) { |
| // If both inputs refer to the same operand, enforce allocating a register |
| // for both of them to ensure that we don't end up generating code like |
| // this: |
| // |
| // mov eax, [ebp-0x10] |
| // add eax, [ebp-0x10] |
| // jo label |
| InstructionOperand const input = g.UseRegister(left); |
| inputs[input_count++] = input; |
| inputs[input_count++] = input; |
| } else if (g.CanBeImmediate(right)) { |
| inputs[input_count++] = g.UseRegister(left); |
| inputs[input_count++] = g.UseImmediate(right); |
| } else { |
| if (node->op()->HasProperty(Operator::kCommutative) && |
| g.CanBeBetterLeftOperand(right)) { |
| std::swap(left, right); |
| } |
| inputs[input_count++] = g.UseRegister(left); |
| inputs[input_count++] = g.Use(right); |
| } |
| |
| if (cont->IsBranch()) { |
| inputs[input_count++] = g.Label(cont->true_block()); |
| inputs[input_count++] = g.Label(cont->false_block()); |
| } |
| |
| outputs[output_count++] = g.DefineSameAsFirst(node); |
| if (cont->IsSet()) { |
| outputs[output_count++] = g.DefineAsByteRegister(cont->result()); |
| } |
| |
| DCHECK_NE(0u, input_count); |
| DCHECK_NE(0u, output_count); |
| DCHECK_GE(arraysize(inputs), input_count); |
| DCHECK_GE(arraysize(outputs), output_count); |
| |
| opcode = cont->Encode(opcode); |
| if (cont->IsDeoptimize()) { |
| selector->EmitDeoptimize(opcode, output_count, outputs, input_count, inputs, |
| cont->frame_state()); |
| } else { |
| selector->Emit(opcode, output_count, outputs, input_count, inputs); |
| } |
| } |
| |
| |
| // Shared routine for multiple binary operations. |
| void VisitBinop(InstructionSelector* selector, Node* node, |
| InstructionCode opcode) { |
| FlagsContinuation cont; |
| VisitBinop(selector, node, opcode, &cont); |
| } |
| |
| } // namespace |
| |
| void InstructionSelector::VisitWord32And(Node* node) { |
| VisitBinop(this, node, kIA32And); |
| } |
| |
| |
| void InstructionSelector::VisitWord32Or(Node* node) { |
| VisitBinop(this, node, kIA32Or); |
| } |
| |
| |
| void InstructionSelector::VisitWord32Xor(Node* node) { |
| IA32OperandGenerator g(this); |
| Int32BinopMatcher m(node); |
| if (m.right().Is(-1)) { |
| Emit(kIA32Not, g.DefineSameAsFirst(node), g.UseRegister(m.left().node())); |
| } else { |
| VisitBinop(this, node, kIA32Xor); |
| } |
| } |
| |
| |
| // Shared routine for multiple shift operations. |
| static inline void VisitShift(InstructionSelector* selector, Node* node, |
| ArchOpcode opcode) { |
| IA32OperandGenerator g(selector); |
| Node* left = node->InputAt(0); |
| Node* right = node->InputAt(1); |
| |
| if (g.CanBeImmediate(right)) { |
| selector->Emit(opcode, g.DefineSameAsFirst(node), g.UseRegister(left), |
| g.UseImmediate(right)); |
| } else { |
| selector->Emit(opcode, g.DefineSameAsFirst(node), g.UseRegister(left), |
| g.UseFixed(right, ecx)); |
| } |
| } |
| |
| |
| namespace { |
| |
| void VisitMulHigh(InstructionSelector* selector, Node* node, |
| ArchOpcode opcode) { |
| IA32OperandGenerator g(selector); |
| InstructionOperand temps[] = {g.TempRegister(eax)}; |
| selector->Emit( |
| opcode, g.DefineAsFixed(node, edx), g.UseFixed(node->InputAt(0), eax), |
| g.UseUniqueRegister(node->InputAt(1)), arraysize(temps), temps); |
| } |
| |
| |
| void VisitDiv(InstructionSelector* selector, Node* node, ArchOpcode opcode) { |
| IA32OperandGenerator g(selector); |
| InstructionOperand temps[] = {g.TempRegister(edx)}; |
| selector->Emit(opcode, g.DefineAsFixed(node, eax), |
| g.UseFixed(node->InputAt(0), eax), |
| g.UseUnique(node->InputAt(1)), arraysize(temps), temps); |
| } |
| |
| |
| void VisitMod(InstructionSelector* selector, Node* node, ArchOpcode opcode) { |
| IA32OperandGenerator g(selector); |
| InstructionOperand temps[] = {g.TempRegister(eax)}; |
| selector->Emit(opcode, g.DefineAsFixed(node, edx), |
| g.UseFixed(node->InputAt(0), eax), |
| g.UseUnique(node->InputAt(1)), arraysize(temps), temps); |
| } |
| |
| void EmitLea(InstructionSelector* selector, Node* result, Node* index, |
| int scale, Node* base, Node* displacement) { |
| IA32OperandGenerator g(selector); |
| InstructionOperand inputs[4]; |
| size_t input_count = 0; |
| AddressingMode mode = g.GenerateMemoryOperandInputs( |
| index, scale, base, displacement, inputs, &input_count); |
| |
| DCHECK_NE(0u, input_count); |
| DCHECK_GE(arraysize(inputs), input_count); |
| |
| InstructionOperand outputs[1]; |
| outputs[0] = g.DefineAsRegister(result); |
| |
| InstructionCode opcode = AddressingModeField::encode(mode) | kIA32Lea; |
| |
| selector->Emit(opcode, 1, outputs, input_count, inputs); |
| } |
| |
| } // namespace |
| |
| |
| void InstructionSelector::VisitWord32Shl(Node* node) { |
| Int32ScaleMatcher m(node, true); |
| if (m.matches()) { |
| Node* index = node->InputAt(0); |
| Node* base = m.power_of_two_plus_one() ? index : nullptr; |
| EmitLea(this, node, index, m.scale(), base, nullptr); |
| return; |
| } |
| VisitShift(this, node, kIA32Shl); |
| } |
| |
| |
| void InstructionSelector::VisitWord32Shr(Node* node) { |
| VisitShift(this, node, kIA32Shr); |
| } |
| |
| |
| void InstructionSelector::VisitWord32Sar(Node* node) { |
| VisitShift(this, node, kIA32Sar); |
| } |
| |
| void InstructionSelector::VisitInt32PairAdd(Node* node) { |
| IA32OperandGenerator g(this); |
| |
| // We use UseUniqueRegister here to avoid register sharing with the temp |
| // register. |
| InstructionOperand inputs[] = { |
| g.UseRegister(node->InputAt(0)), g.UseUniqueRegister(node->InputAt(1)), |
| g.UseRegister(node->InputAt(2)), g.UseUniqueRegister(node->InputAt(3))}; |
| |
| InstructionOperand outputs[] = { |
| g.DefineSameAsFirst(node), |
| g.DefineAsRegister(NodeProperties::FindProjection(node, 1))}; |
| |
| InstructionOperand temps[] = {g.TempRegister()}; |
| |
| Emit(kIA32AddPair, 2, outputs, 4, inputs, 1, temps); |
| } |
| |
| void InstructionSelector::VisitInt32PairSub(Node* node) { |
| IA32OperandGenerator g(this); |
| |
| // We use UseUniqueRegister here to avoid register sharing with the temp |
| // register. |
| InstructionOperand inputs[] = { |
| g.UseRegister(node->InputAt(0)), g.UseUniqueRegister(node->InputAt(1)), |
| g.UseRegister(node->InputAt(2)), g.UseUniqueRegister(node->InputAt(3))}; |
| |
| InstructionOperand outputs[] = { |
| g.DefineSameAsFirst(node), |
| g.DefineAsRegister(NodeProperties::FindProjection(node, 1))}; |
| |
| InstructionOperand temps[] = {g.TempRegister()}; |
| |
| Emit(kIA32SubPair, 2, outputs, 4, inputs, 1, temps); |
| } |
| |
| void InstructionSelector::VisitInt32PairMul(Node* node) { |
| IA32OperandGenerator g(this); |
| |
| // InputAt(3) explicitly shares ecx with OutputRegister(1) to save one |
| // register and one mov instruction. |
| InstructionOperand inputs[] = { |
| g.UseUnique(node->InputAt(0)), g.UseUnique(node->InputAt(1)), |
| g.UseUniqueRegister(node->InputAt(2)), g.UseFixed(node->InputAt(3), ecx)}; |
| |
| InstructionOperand outputs[] = { |
| g.DefineAsFixed(node, eax), |
| g.DefineAsFixed(NodeProperties::FindProjection(node, 1), ecx)}; |
| |
| InstructionOperand temps[] = {g.TempRegister(edx)}; |
| |
| Emit(kIA32MulPair, 2, outputs, 4, inputs, 1, temps); |
| } |
| |
| void VisitWord32PairShift(InstructionSelector* selector, InstructionCode opcode, |
| Node* node) { |
| IA32OperandGenerator g(selector); |
| |
| Node* shift = node->InputAt(2); |
| InstructionOperand shift_operand; |
| if (g.CanBeImmediate(shift)) { |
| shift_operand = g.UseImmediate(shift); |
| } else { |
| shift_operand = g.UseFixed(shift, ecx); |
| } |
| InstructionOperand inputs[] = {g.UseFixed(node->InputAt(0), eax), |
| g.UseFixed(node->InputAt(1), edx), |
| shift_operand}; |
| |
| InstructionOperand outputs[] = { |
| g.DefineAsFixed(node, eax), |
| g.DefineAsFixed(NodeProperties::FindProjection(node, 1), edx)}; |
| |
| selector->Emit(opcode, 2, outputs, 3, inputs); |
| } |
| |
| void InstructionSelector::VisitWord32PairShl(Node* node) { |
| VisitWord32PairShift(this, kIA32ShlPair, node); |
| } |
| |
| void InstructionSelector::VisitWord32PairShr(Node* node) { |
| VisitWord32PairShift(this, kIA32ShrPair, node); |
| } |
| |
| void InstructionSelector::VisitWord32PairSar(Node* node) { |
| VisitWord32PairShift(this, kIA32SarPair, node); |
| } |
| |
| void InstructionSelector::VisitWord32Ror(Node* node) { |
| VisitShift(this, node, kIA32Ror); |
| } |
| |
| |
| void InstructionSelector::VisitWord32Clz(Node* node) { |
| IA32OperandGenerator g(this); |
| Emit(kIA32Lzcnt, g.DefineAsRegister(node), g.Use(node->InputAt(0))); |
| } |
| |
| |
| void InstructionSelector::VisitWord32Ctz(Node* node) { |
| IA32OperandGenerator g(this); |
| Emit(kIA32Tzcnt, g.DefineAsRegister(node), g.Use(node->InputAt(0))); |
| } |
| |
| |
| void InstructionSelector::VisitWord32ReverseBits(Node* node) { UNREACHABLE(); } |
| |
| |
| void InstructionSelector::VisitWord32Popcnt(Node* node) { |
| IA32OperandGenerator g(this); |
| Emit(kIA32Popcnt, g.DefineAsRegister(node), g.Use(node->InputAt(0))); |
| } |
| |
| |
| void InstructionSelector::VisitInt32Add(Node* node) { |
| IA32OperandGenerator g(this); |
| |
| // Try to match the Add to a lea pattern |
| BaseWithIndexAndDisplacement32Matcher m(node); |
| if (m.matches() && |
| (m.displacement() == nullptr || g.CanBeImmediate(m.displacement()))) { |
| InstructionOperand inputs[4]; |
| size_t input_count = 0; |
| AddressingMode mode = g.GenerateMemoryOperandInputs( |
| m.index(), m.scale(), m.base(), m.displacement(), inputs, &input_count); |
| |
| DCHECK_NE(0u, input_count); |
| DCHECK_GE(arraysize(inputs), input_count); |
| |
| InstructionOperand outputs[1]; |
| outputs[0] = g.DefineAsRegister(node); |
| |
| InstructionCode opcode = AddressingModeField::encode(mode) | kIA32Lea; |
| Emit(opcode, 1, outputs, input_count, inputs); |
| return; |
| } |
| |
| // No lea pattern match, use add |
| VisitBinop(this, node, kIA32Add); |
| } |
| |
| |
| void InstructionSelector::VisitInt32Sub(Node* node) { |
| IA32OperandGenerator g(this); |
| Int32BinopMatcher m(node); |
| if (m.left().Is(0)) { |
| Emit(kIA32Neg, g.DefineSameAsFirst(node), g.Use(m.right().node())); |
| } else { |
| VisitBinop(this, node, kIA32Sub); |
| } |
| } |
| |
| |
| void InstructionSelector::VisitInt32Mul(Node* node) { |
| Int32ScaleMatcher m(node, true); |
| if (m.matches()) { |
| Node* index = node->InputAt(0); |
| Node* base = m.power_of_two_plus_one() ? index : nullptr; |
| EmitLea(this, node, index, m.scale(), base, nullptr); |
| return; |
| } |
| IA32OperandGenerator g(this); |
| Node* left = node->InputAt(0); |
| Node* right = node->InputAt(1); |
| if (g.CanBeImmediate(right)) { |
| Emit(kIA32Imul, g.DefineAsRegister(node), g.Use(left), |
| g.UseImmediate(right)); |
| } else { |
| if (g.CanBeBetterLeftOperand(right)) { |
| std::swap(left, right); |
| } |
| Emit(kIA32Imul, g.DefineSameAsFirst(node), g.UseRegister(left), |
| g.Use(right)); |
| } |
| } |
| |
| |
| void InstructionSelector::VisitInt32MulHigh(Node* node) { |
| VisitMulHigh(this, node, kIA32ImulHigh); |
| } |
| |
| |
| void InstructionSelector::VisitUint32MulHigh(Node* node) { |
| VisitMulHigh(this, node, kIA32UmulHigh); |
| } |
| |
| |
| void InstructionSelector::VisitInt32Div(Node* node) { |
| VisitDiv(this, node, kIA32Idiv); |
| } |
| |
| |
| void InstructionSelector::VisitUint32Div(Node* node) { |
| VisitDiv(this, node, kIA32Udiv); |
| } |
| |
| |
| void InstructionSelector::VisitInt32Mod(Node* node) { |
| VisitMod(this, node, kIA32Idiv); |
| } |
| |
| |
| void InstructionSelector::VisitUint32Mod(Node* node) { |
| VisitMod(this, node, kIA32Udiv); |
| } |
| |
| |
| void InstructionSelector::VisitChangeFloat32ToFloat64(Node* node) { |
| VisitRO(this, node, kSSEFloat32ToFloat64); |
| } |
| |
| |
| void InstructionSelector::VisitRoundInt32ToFloat32(Node* node) { |
| VisitRO(this, node, kSSEInt32ToFloat32); |
| } |
| |
| |
| void InstructionSelector::VisitRoundUint32ToFloat32(Node* node) { |
| IA32OperandGenerator g(this); |
| InstructionOperand temps[] = {g.TempRegister(), g.TempRegister()}; |
| Emit(kSSEUint32ToFloat32, g.DefineAsRegister(node), g.Use(node->InputAt(0)), |
| arraysize(temps), temps); |
| } |
| |
| |
| void InstructionSelector::VisitChangeInt32ToFloat64(Node* node) { |
| VisitRO(this, node, kSSEInt32ToFloat64); |
| } |
| |
| |
| void InstructionSelector::VisitChangeUint32ToFloat64(Node* node) { |
| VisitRO(this, node, kSSEUint32ToFloat64); |
| } |
| |
| |
| void InstructionSelector::VisitTruncateFloat32ToInt32(Node* node) { |
| VisitRO(this, node, kSSEFloat32ToInt32); |
| } |
| |
| |
| void InstructionSelector::VisitTruncateFloat32ToUint32(Node* node) { |
| VisitRO(this, node, kSSEFloat32ToUint32); |
| } |
| |
| |
| void InstructionSelector::VisitChangeFloat64ToInt32(Node* node) { |
| VisitRO(this, node, kSSEFloat64ToInt32); |
| } |
| |
| |
| void InstructionSelector::VisitChangeFloat64ToUint32(Node* node) { |
| VisitRO(this, node, kSSEFloat64ToUint32); |
| } |
| |
| void InstructionSelector::VisitTruncateFloat64ToUint32(Node* node) { |
| VisitRO(this, node, kSSEFloat64ToUint32); |
| } |
| |
| void InstructionSelector::VisitTruncateFloat64ToFloat32(Node* node) { |
| VisitRO(this, node, kSSEFloat64ToFloat32); |
| } |
| |
| void InstructionSelector::VisitTruncateFloat64ToWord32(Node* node) { |
| VisitRR(this, node, kArchTruncateDoubleToI); |
| } |
| |
| void InstructionSelector::VisitRoundFloat64ToInt32(Node* node) { |
| VisitRO(this, node, kSSEFloat64ToInt32); |
| } |
| |
| |
| void InstructionSelector::VisitBitcastFloat32ToInt32(Node* node) { |
| IA32OperandGenerator g(this); |
| Emit(kIA32BitcastFI, g.DefineAsRegister(node), g.Use(node->InputAt(0))); |
| } |
| |
| |
| void InstructionSelector::VisitBitcastInt32ToFloat32(Node* node) { |
| IA32OperandGenerator g(this); |
| Emit(kIA32BitcastIF, g.DefineAsRegister(node), g.Use(node->InputAt(0))); |
| } |
| |
| |
| void InstructionSelector::VisitFloat32Add(Node* node) { |
| VisitRROFloat(this, node, kAVXFloat32Add, kSSEFloat32Add); |
| } |
| |
| |
| void InstructionSelector::VisitFloat64Add(Node* node) { |
| VisitRROFloat(this, node, kAVXFloat64Add, kSSEFloat64Add); |
| } |
| |
| |
| void InstructionSelector::VisitFloat32Sub(Node* node) { |
| IA32OperandGenerator g(this); |
| Float32BinopMatcher m(node); |
| if (m.left().IsMinusZero()) { |
| VisitFloatUnop(this, node, m.right().node(), kAVXFloat32Neg, |
| kSSEFloat32Neg); |
| return; |
| } |
| VisitRROFloat(this, node, kAVXFloat32Sub, kSSEFloat32Sub); |
| } |
| |
| void InstructionSelector::VisitFloat32SubPreserveNan(Node* node) { |
| VisitRROFloat(this, node, kAVXFloat32Sub, kSSEFloat32Sub); |
| } |
| |
| void InstructionSelector::VisitFloat64Sub(Node* node) { |
| IA32OperandGenerator g(this); |
| Float64BinopMatcher m(node); |
| if (m.left().IsMinusZero()) { |
| if (m.right().IsFloat64RoundDown() && |
| CanCover(m.node(), m.right().node())) { |
| if (m.right().InputAt(0)->opcode() == IrOpcode::kFloat64Sub && |
| CanCover(m.right().node(), m.right().InputAt(0))) { |
| Float64BinopMatcher mright0(m.right().InputAt(0)); |
| if (mright0.left().IsMinusZero()) { |
| Emit(kSSEFloat64Round | MiscField::encode(kRoundUp), |
| g.DefineAsRegister(node), g.UseRegister(mright0.right().node())); |
| return; |
| } |
| } |
| } |
| VisitFloatUnop(this, node, m.right().node(), kAVXFloat64Neg, |
| kSSEFloat64Neg); |
| return; |
| } |
| VisitRROFloat(this, node, kAVXFloat64Sub, kSSEFloat64Sub); |
| } |
| |
| void InstructionSelector::VisitFloat64SubPreserveNan(Node* node) { |
| VisitRROFloat(this, node, kAVXFloat64Sub, kSSEFloat64Sub); |
| } |
| |
| void InstructionSelector::VisitFloat32Mul(Node* node) { |
| VisitRROFloat(this, node, kAVXFloat32Mul, kSSEFloat32Mul); |
| } |
| |
| |
| void InstructionSelector::VisitFloat64Mul(Node* node) { |
| VisitRROFloat(this, node, kAVXFloat64Mul, kSSEFloat64Mul); |
| } |
| |
| |
| void InstructionSelector::VisitFloat32Div(Node* node) { |
| VisitRROFloat(this, node, kAVXFloat32Div, kSSEFloat32Div); |
| } |
| |
| |
| void InstructionSelector::VisitFloat64Div(Node* node) { |
| VisitRROFloat(this, node, kAVXFloat64Div, kSSEFloat64Div); |
| } |
| |
| |
| void InstructionSelector::VisitFloat64Mod(Node* node) { |
| IA32OperandGenerator g(this); |
| InstructionOperand temps[] = {g.TempRegister(eax)}; |
| Emit(kSSEFloat64Mod, g.DefineSameAsFirst(node), |
| g.UseRegister(node->InputAt(0)), g.UseRegister(node->InputAt(1)), 1, |
| temps); |
| } |
| |
| |
| void InstructionSelector::VisitFloat32Max(Node* node) { |
| VisitRROFloat(this, node, kAVXFloat32Max, kSSEFloat32Max); |
| } |
| |
| |
| void InstructionSelector::VisitFloat64Max(Node* node) { |
| VisitRROFloat(this, node, kAVXFloat64Max, kSSEFloat64Max); |
| } |
| |
| |
| void InstructionSelector::VisitFloat32Min(Node* node) { |
| VisitRROFloat(this, node, kAVXFloat32Min, kSSEFloat32Min); |
| } |
| |
| |
| void InstructionSelector::VisitFloat64Min(Node* node) { |
| VisitRROFloat(this, node, kAVXFloat64Min, kSSEFloat64Min); |
| } |
| |
| |
| void InstructionSelector::VisitFloat32Abs(Node* node) { |
| IA32OperandGenerator g(this); |
| VisitFloatUnop(this, node, node->InputAt(0), kAVXFloat32Abs, kSSEFloat32Abs); |
| } |
| |
| |
| void InstructionSelector::VisitFloat64Abs(Node* node) { |
| IA32OperandGenerator g(this); |
| VisitFloatUnop(this, node, node->InputAt(0), kAVXFloat64Abs, kSSEFloat64Abs); |
| } |
| |
| void InstructionSelector::VisitFloat32Sqrt(Node* node) { |
| VisitRO(this, node, kSSEFloat32Sqrt); |
| } |
| |
| |
| void InstructionSelector::VisitFloat64Sqrt(Node* node) { |
| VisitRO(this, node, kSSEFloat64Sqrt); |
| } |
| |
| |
| void InstructionSelector::VisitFloat32RoundDown(Node* node) { |
| VisitRR(this, node, kSSEFloat32Round | MiscField::encode(kRoundDown)); |
| } |
| |
| |
| void InstructionSelector::VisitFloat64RoundDown(Node* node) { |
| VisitRR(this, node, kSSEFloat64Round | MiscField::encode(kRoundDown)); |
| } |
| |
| |
| void InstructionSelector::VisitFloat32RoundUp(Node* node) { |
| VisitRR(this, node, kSSEFloat32Round | MiscField::encode(kRoundUp)); |
| } |
| |
| |
| void InstructionSelector::VisitFloat64RoundUp(Node* node) { |
| VisitRR(this, node, kSSEFloat64Round | MiscField::encode(kRoundUp)); |
| } |
| |
| |
| void InstructionSelector::VisitFloat32RoundTruncate(Node* node) { |
| VisitRR(this, node, kSSEFloat32Round | MiscField::encode(kRoundToZero)); |
| } |
| |
| |
| void InstructionSelector::VisitFloat64RoundTruncate(Node* node) { |
| VisitRR(this, node, kSSEFloat64Round | MiscField::encode(kRoundToZero)); |
| } |
| |
| |
| void InstructionSelector::VisitFloat64RoundTiesAway(Node* node) { |
| UNREACHABLE(); |
| } |
| |
| |
| void InstructionSelector::VisitFloat32RoundTiesEven(Node* node) { |
| VisitRR(this, node, kSSEFloat32Round | MiscField::encode(kRoundToNearest)); |
| } |
| |
| |
| void InstructionSelector::VisitFloat64RoundTiesEven(Node* node) { |
| VisitRR(this, node, kSSEFloat64Round | MiscField::encode(kRoundToNearest)); |
| } |
| |
| void InstructionSelector::VisitFloat32Neg(Node* node) { UNREACHABLE(); } |
| |
| void InstructionSelector::VisitFloat64Neg(Node* node) { UNREACHABLE(); } |
| |
| void InstructionSelector::VisitFloat64Ieee754Binop(Node* node, |
| InstructionCode opcode) { |
| IA32OperandGenerator g(this); |
| Emit(opcode, g.DefineSameAsFirst(node), g.UseRegister(node->InputAt(0)), |
| g.UseRegister(node->InputAt(1))) |
| ->MarkAsCall(); |
| } |
| |
| void InstructionSelector::VisitFloat64Ieee754Unop(Node* node, |
| InstructionCode opcode) { |
| IA32OperandGenerator g(this); |
| Emit(opcode, g.DefineSameAsFirst(node), g.UseRegister(node->InputAt(0))) |
| ->MarkAsCall(); |
| } |
| |
| void InstructionSelector::EmitPrepareArguments( |
| ZoneVector<PushParameter>* arguments, const CallDescriptor* descriptor, |
| Node* node) { |
| IA32OperandGenerator g(this); |
| |
| // Prepare for C function call. |
| if (descriptor->IsCFunctionCall()) { |
| InstructionOperand temps[] = {g.TempRegister()}; |
| size_t const temp_count = arraysize(temps); |
| Emit(kArchPrepareCallCFunction | |
| MiscField::encode(static_cast<int>(descriptor->CParameterCount())), |
| 0, nullptr, 0, nullptr, temp_count, temps); |
| |
| // Poke any stack arguments. |
| for (size_t n = 0; n < arguments->size(); ++n) { |
| PushParameter input = (*arguments)[n]; |
| if (input.node()) { |
| int const slot = static_cast<int>(n); |
| InstructionOperand value = g.CanBeImmediate(node) |
| ? g.UseImmediate(input.node()) |
| : g.UseRegister(input.node()); |
| Emit(kIA32Poke | MiscField::encode(slot), g.NoOutput(), value); |
| } |
| } |
| } else { |
| // Push any stack arguments. |
| for (PushParameter input : base::Reversed(*arguments)) { |
| // Skip any alignment holes in pushed nodes. |
| if (input.node() == nullptr) continue; |
| InstructionOperand value = |
| g.CanBeImmediate(input.node()) |
| ? g.UseImmediate(input.node()) |
| : IsSupported(ATOM) || |
| sequence()->IsFP(GetVirtualRegister(input.node())) |
| ? g.UseRegister(input.node()) |
| : g.Use(input.node()); |
| if (input.type() == MachineType::Float32()) { |
| Emit(kIA32PushFloat32, g.NoOutput(), value); |
| } else if (input.type() == MachineType::Float64()) { |
| Emit(kIA32PushFloat64, g.NoOutput(), value); |
| } else { |
| Emit(kIA32Push, g.NoOutput(), value); |
| } |
| } |
| } |
| } |
| |
| |
| bool InstructionSelector::IsTailCallAddressImmediate() { return true; } |
| |
| int InstructionSelector::GetTempsCountForTailCallFromJSFunction() { return 0; } |
| |
| namespace { |
| |
| void VisitCompareWithMemoryOperand(InstructionSelector* selector, |
| InstructionCode opcode, Node* left, |
| InstructionOperand right, |
| FlagsContinuation* cont) { |
| DCHECK(left->opcode() == IrOpcode::kLoad); |
| IA32OperandGenerator g(selector); |
| size_t input_count = 0; |
| InstructionOperand inputs[6]; |
| AddressingMode addressing_mode = |
| g.GetEffectiveAddressMemoryOperand(left, inputs, &input_count); |
| opcode |= AddressingModeField::encode(addressing_mode); |
| opcode = cont->Encode(opcode); |
| inputs[input_count++] = right; |
| |
| if (cont->IsBranch()) { |
| inputs[input_count++] = g.Label(cont->true_block()); |
| inputs[input_count++] = g.Label(cont->false_block()); |
| selector->Emit(opcode, 0, nullptr, input_count, inputs); |
| } else if (cont->IsDeoptimize()) { |
| selector->EmitDeoptimize(opcode, 0, nullptr, input_count, inputs, |
| cont->frame_state()); |
| } else { |
| DCHECK(cont->IsSet()); |
| InstructionOperand output = g.DefineAsRegister(cont->result()); |
| selector->Emit(opcode, 1, &output, input_count, inputs); |
| } |
| } |
| |
| // Shared routine for multiple compare operations. |
| void VisitCompare(InstructionSelector* selector, InstructionCode opcode, |
| InstructionOperand left, InstructionOperand right, |
| FlagsContinuation* cont) { |
| IA32OperandGenerator g(selector); |
| opcode = cont->Encode(opcode); |
| if (cont->IsBranch()) { |
| selector->Emit(opcode, g.NoOutput(), left, right, |
| g.Label(cont->true_block()), g.Label(cont->false_block())); |
| } else if (cont->IsDeoptimize()) { |
| selector->EmitDeoptimize(opcode, g.NoOutput(), left, right, |
| cont->frame_state()); |
| } else { |
| DCHECK(cont->IsSet()); |
| selector->Emit(opcode, g.DefineAsByteRegister(cont->result()), left, right); |
| } |
| } |
| |
| |
| // Shared routine for multiple compare operations. |
| void VisitCompare(InstructionSelector* selector, InstructionCode opcode, |
| Node* left, Node* right, FlagsContinuation* cont, |
| bool commutative) { |
| IA32OperandGenerator g(selector); |
| if (commutative && g.CanBeBetterLeftOperand(right)) { |
| std::swap(left, right); |
| } |
| VisitCompare(selector, opcode, g.UseRegister(left), g.Use(right), cont); |
| } |
| |
| // Tries to match the size of the given opcode to that of the operands, if |
| // possible. |
| InstructionCode TryNarrowOpcodeSize(InstructionCode opcode, Node* left, |
| Node* right) { |
| if (opcode != kIA32Cmp && opcode != kIA32Test) { |
| return opcode; |
| } |
| // Currently, if one of the two operands is not a Load, we don't know what its |
| // machine representation is, so we bail out. |
| // TODO(epertoso): we can probably get some size information out of immediates |
| // and phi nodes. |
| if (left->opcode() != IrOpcode::kLoad || right->opcode() != IrOpcode::kLoad) { |
| return opcode; |
| } |
| // If the load representations don't match, both operands will be |
| // zero/sign-extended to 32bit. |
| LoadRepresentation left_representation = LoadRepresentationOf(left->op()); |
| if (left_representation != LoadRepresentationOf(right->op())) { |
| return opcode; |
| } |
| switch (left_representation.representation()) { |
| case MachineRepresentation::kBit: |
| case MachineRepresentation::kWord8: |
| return opcode == kIA32Cmp ? kIA32Cmp8 : kIA32Test8; |
| case MachineRepresentation::kWord16: |
| return opcode == kIA32Cmp ? kIA32Cmp16 : kIA32Test16; |
| default: |
| return opcode; |
| } |
| } |
| |
| // Shared routine for multiple float32 compare operations (inputs commuted). |
| void VisitFloat32Compare(InstructionSelector* selector, Node* node, |
| FlagsContinuation* cont) { |
| Node* const left = node->InputAt(0); |
| Node* const right = node->InputAt(1); |
| VisitCompare(selector, kSSEFloat32Cmp, right, left, cont, false); |
| } |
| |
| |
| // Shared routine for multiple float64 compare operations (inputs commuted). |
| void VisitFloat64Compare(InstructionSelector* selector, Node* node, |
| FlagsContinuation* cont) { |
| Node* const left = node->InputAt(0); |
| Node* const right = node->InputAt(1); |
| VisitCompare(selector, kSSEFloat64Cmp, right, left, cont, false); |
| } |
| |
| // Shared routine for multiple word compare operations. |
| void VisitWordCompare(InstructionSelector* selector, Node* node, |
| InstructionCode opcode, FlagsContinuation* cont) { |
| IA32OperandGenerator g(selector); |
| Node* left = node->InputAt(0); |
| Node* right = node->InputAt(1); |
| |
| InstructionCode narrowed_opcode = TryNarrowOpcodeSize(opcode, left, right); |
| |
| int effect_level = selector->GetEffectLevel(node); |
| if (cont->IsBranch()) { |
| effect_level = selector->GetEffectLevel( |
| cont->true_block()->PredecessorAt(0)->control_input()); |
| } |
| |
| // If one of the two inputs is an immediate, make sure it's on the right, or |
| // if one of the two inputs is a memory operand, make sure it's on the left. |
| if ((!g.CanBeImmediate(right) && g.CanBeImmediate(left)) || |
| (g.CanBeMemoryOperand(narrowed_opcode, node, right, effect_level) && |
| !g.CanBeMemoryOperand(narrowed_opcode, node, left, effect_level))) { |
| if (!node->op()->HasProperty(Operator::kCommutative)) cont->Commute(); |
| std::swap(left, right); |
| } |
| |
| // Match immediates on right side of comparison. |
| if (g.CanBeImmediate(right)) { |
| if (g.CanBeMemoryOperand(opcode, node, left, effect_level)) { |
| // TODO(epertoso): we should use `narrowed_opcode' here once we match |
| // immediates too. |
| return VisitCompareWithMemoryOperand(selector, opcode, left, |
| g.UseImmediate(right), cont); |
| } |
| return VisitCompare(selector, opcode, g.Use(left), g.UseImmediate(right), |
| cont); |
| } |
| |
| // Match memory operands on left side of comparison. |
| if (g.CanBeMemoryOperand(narrowed_opcode, node, left, effect_level)) { |
| bool needs_byte_register = |
| narrowed_opcode == kIA32Test8 || narrowed_opcode == kIA32Cmp8; |
| return VisitCompareWithMemoryOperand( |
| selector, narrowed_opcode, left, |
| needs_byte_register ? g.UseByteRegister(right) : g.UseRegister(right), |
| cont); |
| } |
| |
| if (g.CanBeBetterLeftOperand(right)) { |
| if (!node->op()->HasProperty(Operator::kCommutative)) cont->Commute(); |
| std::swap(left, right); |
| } |
| |
| return VisitCompare(selector, opcode, left, right, cont, |
| node->op()->HasProperty(Operator::kCommutative)); |
| } |
| |
| void VisitWordCompare(InstructionSelector* selector, Node* node, |
| FlagsContinuation* cont) { |
| IA32OperandGenerator g(selector); |
| Int32BinopMatcher m(node); |
| if (m.left().IsLoad() && m.right().IsLoadStackPointer()) { |
| LoadMatcher<ExternalReferenceMatcher> mleft(m.left().node()); |
| ExternalReference js_stack_limit = |
| ExternalReference::address_of_stack_limit(selector->isolate()); |
| if (mleft.object().Is(js_stack_limit) && mleft.index().Is(0)) { |
| // Compare(Load(js_stack_limit), LoadStackPointer) |
| if (!node->op()->HasProperty(Operator::kCommutative)) cont->Commute(); |
| InstructionCode opcode = cont->Encode(kIA32StackCheck); |
| if (cont->IsBranch()) { |
| selector->Emit(opcode, g.NoOutput(), g.Label(cont->true_block()), |
| g.Label(cont->false_block())); |
| } else if (cont->IsDeoptimize()) { |
| selector->EmitDeoptimize(opcode, 0, nullptr, 0, nullptr, |
| cont->frame_state()); |
| } else { |
| DCHECK(cont->IsSet()); |
| selector->Emit(opcode, g.DefineAsRegister(cont->result())); |
| } |
| return; |
| } |
| } |
| VisitWordCompare(selector, node, kIA32Cmp, cont); |
| } |
| |
| |
| // Shared routine for word comparison with zero. |
| void VisitWordCompareZero(InstructionSelector* selector, Node* user, |
| Node* value, FlagsContinuation* cont) { |
| // Try to combine the branch with a comparison. |
| while (selector->CanCover(user, value)) { |
| switch (value->opcode()) { |
| case IrOpcode::kWord32Equal: { |
| // Try to combine with comparisons against 0 by simply inverting the |
| // continuation. |
| Int32BinopMatcher m(value); |
| if (m.right().Is(0)) { |
| user = value; |
| value = m.left().node(); |
| cont->Negate(); |
| continue; |
| } |
| cont->OverwriteAndNegateIfEqual(kEqual); |
| return VisitWordCompare(selector, value, cont); |
| } |
| case IrOpcode::kInt32LessThan: |
| cont->OverwriteAndNegateIfEqual(kSignedLessThan); |
| return VisitWordCompare(selector, value, cont); |
| case IrOpcode::kInt32LessThanOrEqual: |
| cont->OverwriteAndNegateIfEqual(kSignedLessThanOrEqual); |
| return VisitWordCompare(selector, value, cont); |
| case IrOpcode::kUint32LessThan: |
| cont->OverwriteAndNegateIfEqual(kUnsignedLessThan); |
| return VisitWordCompare(selector, value, cont); |
| case IrOpcode::kUint32LessThanOrEqual: |
| cont->OverwriteAndNegateIfEqual(kUnsignedLessThanOrEqual); |
| return VisitWordCompare(selector, value, cont); |
| case IrOpcode::kFloat32Equal: |
| cont->OverwriteAndNegateIfEqual(kUnorderedEqual); |
| return VisitFloat32Compare(selector, value, cont); |
| case IrOpcode::kFloat32LessThan: |
| cont->OverwriteAndNegateIfEqual(kUnsignedGreaterThan); |
| return VisitFloat32Compare(selector, value, cont); |
| case IrOpcode::kFloat32LessThanOrEqual: |
| cont->OverwriteAndNegateIfEqual(kUnsignedGreaterThanOrEqual); |
| return VisitFloat32Compare(selector, value, cont); |
| case IrOpcode::kFloat64Equal: |
| cont->OverwriteAndNegateIfEqual(kUnorderedEqual); |
| return VisitFloat64Compare(selector, value, cont); |
| case IrOpcode::kFloat64LessThan: |
| cont->OverwriteAndNegateIfEqual(kUnsignedGreaterThan); |
| return VisitFloat64Compare(selector, value, cont); |
| case IrOpcode::kFloat64LessThanOrEqual: |
| cont->OverwriteAndNegateIfEqual(kUnsignedGreaterThanOrEqual); |
| return VisitFloat64Compare(selector, value, cont); |
| case IrOpcode::kProjection: |
| // Check if this is the overflow output projection of an |
| // <Operation>WithOverflow node. |
| if (ProjectionIndexOf(value->op()) == 1u) { |
| // We cannot combine the <Operation>WithOverflow with this branch |
| // unless the 0th projection (the use of the actual value of the |
| // <Operation> is either nullptr, which means there's no use of the |
| // actual value, or was already defined, which means it is scheduled |
| // *AFTER* this branch). |
| Node* const node = value->InputAt(0); |
| Node* const result = NodeProperties::FindProjection(node, 0); |
| if (result == nullptr || selector->IsDefined(result)) { |
| switch (node->opcode()) { |
| case IrOpcode::kInt32AddWithOverflow: |
| cont->OverwriteAndNegateIfEqual(kOverflow); |
| return VisitBinop(selector, node, kIA32Add, cont); |
| case IrOpcode::kInt32SubWithOverflow: |
| cont->OverwriteAndNegateIfEqual(kOverflow); |
| return VisitBinop(selector, node, kIA32Sub, cont); |
| default: |
| break; |
| } |
| } |
| } |
| break; |
| case IrOpcode::kInt32Sub: |
| return VisitWordCompare(selector, value, cont); |
| case IrOpcode::kWord32And: |
| return VisitWordCompare(selector, value, kIA32Test, cont); |
| default: |
| break; |
| } |
| break; |
| } |
| |
| // Continuation could not be combined with a compare, emit compare against 0. |
| IA32OperandGenerator g(selector); |
| VisitCompare(selector, kIA32Cmp, g.Use(value), g.TempImmediate(0), cont); |
| } |
| |
| } // namespace |
| |
| void InstructionSelector::VisitBranch(Node* branch, BasicBlock* tbranch, |
| BasicBlock* fbranch) { |
| FlagsContinuation cont(kNotEqual, tbranch, fbranch); |
| VisitWordCompareZero(this, branch, branch->InputAt(0), &cont); |
| } |
| |
| void InstructionSelector::VisitDeoptimizeIf(Node* node) { |
| FlagsContinuation cont = |
| FlagsContinuation::ForDeoptimize(kNotEqual, node->InputAt(1)); |
| VisitWordCompareZero(this, node, node->InputAt(0), &cont); |
| } |
| |
| void InstructionSelector::VisitDeoptimizeUnless(Node* node) { |
| FlagsContinuation cont = |
| FlagsContinuation::ForDeoptimize(kEqual, node->InputAt(1)); |
| VisitWordCompareZero(this, node, node->InputAt(0), &cont); |
| } |
| |
| void InstructionSelector::VisitSwitch(Node* node, const SwitchInfo& sw) { |
| IA32OperandGenerator g(this); |
| InstructionOperand value_operand = g.UseRegister(node->InputAt(0)); |
| |
| // Emit either ArchTableSwitch or ArchLookupSwitch. |
| size_t table_space_cost = 4 + sw.value_range; |
| size_t table_time_cost = 3; |
| size_t lookup_space_cost = 3 + 2 * sw.case_count; |
| size_t lookup_time_cost = sw.case_count; |
| if (sw.case_count > 4 && |
| table_space_cost + 3 * table_time_cost <= |
| lookup_space_cost + 3 * lookup_time_cost && |
| sw.min_value > std::numeric_limits<int32_t>::min()) { |
| InstructionOperand index_operand = value_operand; |
| if (sw.min_value) { |
| index_operand = g.TempRegister(); |
| Emit(kIA32Lea | AddressingModeField::encode(kMode_MRI), index_operand, |
| value_operand, g.TempImmediate(-sw.min_value)); |
| } |
| // Generate a table lookup. |
| return EmitTableSwitch(sw, index_operand); |
| } |
| |
| // Generate a sequence of conditional jumps. |
| return EmitLookupSwitch(sw, value_operand); |
| } |
| |
| |
| void InstructionSelector::VisitWord32Equal(Node* const node) { |
| FlagsContinuation cont = FlagsContinuation::ForSet(kEqual, node); |
| Int32BinopMatcher m(node); |
| if (m.right().Is(0)) { |
| return VisitWordCompareZero(this, m.node(), m.left().node(), &cont); |
| } |
| VisitWordCompare(this, node, &cont); |
| } |
| |
| |
| void InstructionSelector::VisitInt32LessThan(Node* node) { |
| FlagsContinuation cont = FlagsContinuation::ForSet(kSignedLessThan, node); |
| VisitWordCompare(this, node, &cont); |
| } |
| |
| |
| void InstructionSelector::VisitInt32LessThanOrEqual(Node* node) { |
| FlagsContinuation cont = |
| FlagsContinuation::ForSet(kSignedLessThanOrEqual, node); |
| VisitWordCompare(this, node, &cont); |
| } |
| |
| |
| void InstructionSelector::VisitUint32LessThan(Node* node) { |
| FlagsContinuation cont = FlagsContinuation::ForSet(kUnsignedLessThan, node); |
| VisitWordCompare(this, node, &cont); |
| } |
| |
| |
| void InstructionSelector::VisitUint32LessThanOrEqual(Node* node) { |
| FlagsContinuation cont = |
| FlagsContinuation::ForSet(kUnsignedLessThanOrEqual, node); |
| VisitWordCompare(this, node, &cont); |
| } |
| |
| |
| void InstructionSelector::VisitInt32AddWithOverflow(Node* node) { |
| if (Node* ovf = NodeProperties::FindProjection(node, 1)) { |
| FlagsContinuation cont = FlagsContinuation::ForSet(kOverflow, ovf); |
| return VisitBinop(this, node, kIA32Add, &cont); |
| } |
| FlagsContinuation cont; |
| VisitBinop(this, node, kIA32Add, &cont); |
| } |
| |
| |
| void InstructionSelector::VisitInt32SubWithOverflow(Node* node) { |
| if (Node* ovf = NodeProperties::FindProjection(node, 1)) { |
| FlagsContinuation cont = FlagsContinuation::ForSet(kOverflow, ovf); |
| return VisitBinop(this, node, kIA32Sub, &cont); |
| } |
| FlagsContinuation cont; |
| VisitBinop(this, node, kIA32Sub, &cont); |
| } |
| |
| |
| void InstructionSelector::VisitFloat32Equal(Node* node) { |
| FlagsContinuation cont = FlagsContinuation::ForSet(kUnorderedEqual, node); |
| VisitFloat32Compare(this, node, &cont); |
| } |
| |
| |
| void InstructionSelector::VisitFloat32LessThan(Node* node) { |
| FlagsContinuation cont = |
| FlagsContinuation::ForSet(kUnsignedGreaterThan, node); |
| VisitFloat32Compare(this, node, &cont); |
| } |
| |
| |
| void InstructionSelector::VisitFloat32LessThanOrEqual(Node* node) { |
| FlagsContinuation cont = |
| FlagsContinuation::ForSet(kUnsignedGreaterThanOrEqual, node); |
| VisitFloat32Compare(this, node, &cont); |
| } |
| |
| |
| void InstructionSelector::VisitFloat64Equal(Node* node) { |
| FlagsContinuation cont = FlagsContinuation::ForSet(kUnorderedEqual, node); |
| VisitFloat64Compare(this, node, &cont); |
| } |
| |
| |
| void InstructionSelector::VisitFloat64LessThan(Node* node) { |
| FlagsContinuation cont = |
| FlagsContinuation::ForSet(kUnsignedGreaterThan, node); |
| VisitFloat64Compare(this, node, &cont); |
| } |
| |
| |
| void InstructionSelector::VisitFloat64LessThanOrEqual(Node* node) { |
| FlagsContinuation cont = |
| FlagsContinuation::ForSet(kUnsignedGreaterThanOrEqual, node); |
| VisitFloat64Compare(this, node, &cont); |
| } |
| |
| |
| void InstructionSelector::VisitFloat64ExtractLowWord32(Node* node) { |
| IA32OperandGenerator g(this); |
| Emit(kSSEFloat64ExtractLowWord32, g.DefineAsRegister(node), |
| g.Use(node->InputAt(0))); |
| } |
| |
| |
| void InstructionSelector::VisitFloat64ExtractHighWord32(Node* node) { |
| IA32OperandGenerator g(this); |
| Emit(kSSEFloat64ExtractHighWord32, g.DefineAsRegister(node), |
| g.Use(node->InputAt(0))); |
| } |
| |
| |
| void InstructionSelector::VisitFloat64InsertLowWord32(Node* node) { |
| IA32OperandGenerator g(this); |
| Node* left = node->InputAt(0); |
| Node* right = node->InputAt(1); |
| Float64Matcher mleft(left); |
| if (mleft.HasValue() && (bit_cast<uint64_t>(mleft.Value()) >> 32) == 0u) { |
| Emit(kSSEFloat64LoadLowWord32, g.DefineAsRegister(node), g.Use(right)); |
| return; |
| } |
| Emit(kSSEFloat64InsertLowWord32, g.DefineSameAsFirst(node), |
| g.UseRegister(left), g.Use(right)); |
| } |
| |
| |
| void InstructionSelector::VisitFloat64InsertHighWord32(Node* node) { |
| IA32OperandGenerator g(this); |
| Node* left = node->InputAt(0); |
| Node* right = node->InputAt(1); |
| Emit(kSSEFloat64InsertHighWord32, g.DefineSameAsFirst(node), |
| g.UseRegister(left), g.Use(right)); |
| } |
| |
| void InstructionSelector::VisitFloat64SilenceNaN(Node* node) { |
| IA32OperandGenerator g(this); |
| Emit(kSSEFloat64SilenceNaN, g.DefineSameAsFirst(node), |
| g.UseRegister(node->InputAt(0))); |
| } |
| |
| void InstructionSelector::VisitAtomicLoad(Node* node) { |
| LoadRepresentation load_rep = LoadRepresentationOf(node->op()); |
| DCHECK(load_rep.representation() == MachineRepresentation::kWord8 || |
| load_rep.representation() == MachineRepresentation::kWord16 || |
| load_rep.representation() == MachineRepresentation::kWord32); |
| USE(load_rep); |
| VisitLoad(node); |
| } |
| |
| void InstructionSelector::VisitAtomicStore(Node* node) { |
| IA32OperandGenerator g(this); |
| Node* base = node->InputAt(0); |
| Node* index = node->InputAt(1); |
| Node* value = node->InputAt(2); |
| |
| MachineRepresentation rep = AtomicStoreRepresentationOf(node->op()); |
| ArchOpcode opcode = kArchNop; |
| switch (rep) { |
| case MachineRepresentation::kWord8: |
| opcode = kIA32Xchgb; |
| break; |
| case MachineRepresentation::kWord16: |
| opcode = kIA32Xchgw; |
| break; |
| case MachineRepresentation::kWord32: |
| opcode = kIA32Xchgl; |
| break; |
| default: |
| UNREACHABLE(); |
| break; |
| } |
| AddressingMode addressing_mode; |
| InstructionOperand inputs[4]; |
| size_t input_count = 0; |
| inputs[input_count++] = g.UseUniqueRegister(base); |
| if (g.CanBeImmediate(index)) { |
| inputs[input_count++] = g.UseImmediate(index); |
| addressing_mode = kMode_MRI; |
| } else { |
| inputs[input_count++] = g.UseUniqueRegister(index); |
| addressing_mode = kMode_MR1; |
| } |
| inputs[input_count++] = g.UseUniqueRegister(value); |
| InstructionCode code = opcode | AddressingModeField::encode(addressing_mode); |
| Emit(code, 0, nullptr, input_count, inputs); |
| } |
| |
| // static |
| MachineOperatorBuilder::Flags |
| InstructionSelector::SupportedMachineOperatorFlags() { |
| MachineOperatorBuilder::Flags flags = |
| MachineOperatorBuilder::kFloat32Max | |
| MachineOperatorBuilder::kFloat32Min | |
| MachineOperatorBuilder::kFloat64Max | |
| MachineOperatorBuilder::kFloat64Min | |
| MachineOperatorBuilder::kWord32ShiftIsSafe | |
| MachineOperatorBuilder::kWord32Ctz; |
| if (CpuFeatures::IsSupported(POPCNT)) { |
| flags |= MachineOperatorBuilder::kWord32Popcnt; |
| } |
| if (CpuFeatures::IsSupported(SSE4_1)) { |
| flags |= MachineOperatorBuilder::kFloat32RoundDown | |
| MachineOperatorBuilder::kFloat64RoundDown | |
| MachineOperatorBuilder::kFloat32RoundUp | |
| MachineOperatorBuilder::kFloat64RoundUp | |
| MachineOperatorBuilder::kFloat32RoundTruncate | |
| MachineOperatorBuilder::kFloat64RoundTruncate | |
| MachineOperatorBuilder::kFloat32RoundTiesEven | |
| MachineOperatorBuilder::kFloat64RoundTiesEven; |
| } |
| return flags; |
| } |
| |
| // static |
| MachineOperatorBuilder::AlignmentRequirements |
| InstructionSelector::AlignmentRequirements() { |
| return MachineOperatorBuilder::AlignmentRequirements:: |
| FullUnalignedAccessSupport(); |
| } |
| |
| } // namespace compiler |
| } // namespace internal |
| } // namespace v8 |