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gerrit-public.fairphone.software / fp2-dev / platform / external / v8 / 097c5b25f8b57b92e6c94f25383a883ff242344f / . / src / compiler / ia32 / instruction-codes-ia32.h
blob: 61fd035403de27dbd7f7f678447f90672e0aa1e1 [file] [log] [blame]
Ben Murdochb8a8cc12014-11-26 15:28:44 +0000[diff] [blame]1// Copyright 2014 the V8 project authors. All rights reserved.
2// Use of this source code is governed by a BSD-style license that can be
3// found in the LICENSE file.
4
5#ifndef V8_COMPILER_IA32_INSTRUCTION_CODES_IA32_H_
6#define V8_COMPILER_IA32_INSTRUCTION_CODES_IA32_H_
7
8namespace v8 {
9namespace internal {
10namespace compiler {
11
12// IA32-specific opcodes that specify which assembly sequence to emit.
13// Most opcodes specify a single instruction.
14#define TARGET_ARCH_OPCODE_LIST(V) \
15 V(IA32Add) \
16 V(IA32And) \
17 V(IA32Cmp) \
18 V(IA32Test) \
19 V(IA32Or) \
20 V(IA32Xor) \
21 V(IA32Sub) \
22 V(IA32Imul) \
Emily Bernierd0a1eb72015-03-24 16:35:39 -0400[diff] [blame]23 V(IA32ImulHigh) \
24 V(IA32UmulHigh) \
Ben Murdochb8a8cc12014-11-26 15:28:44 +0000[diff] [blame]25 V(IA32Idiv) \
26 V(IA32Udiv) \
27 V(IA32Not) \
28 V(IA32Neg) \
29 V(IA32Shl) \
30 V(IA32Shr) \
31 V(IA32Sar) \
32 V(IA32Ror) \
Ben Murdoch4a90d5f2016-03-22 12:00:34 +0000[diff] [blame]33 V(IA32Lzcnt) \
34 V(IA32Tzcnt) \
35 V(IA32Popcnt) \
36 V(SSEFloat32Cmp) \
37 V(SSEFloat32Add) \
38 V(SSEFloat32Sub) \
39 V(SSEFloat32Mul) \
40 V(SSEFloat32Div) \
41 V(SSEFloat32Max) \
42 V(SSEFloat32Min) \
43 V(SSEFloat32Abs) \
44 V(SSEFloat32Neg) \
45 V(SSEFloat32Sqrt) \
46 V(SSEFloat32Round) \
Ben Murdochb8a8cc12014-11-26 15:28:44 +0000[diff] [blame]47 V(SSEFloat64Cmp) \
48 V(SSEFloat64Add) \
49 V(SSEFloat64Sub) \
50 V(SSEFloat64Mul) \
51 V(SSEFloat64Div) \
52 V(SSEFloat64Mod) \
Ben Murdoch4a90d5f2016-03-22 12:00:34 +0000[diff] [blame]53 V(SSEFloat64Max) \
54 V(SSEFloat64Min) \
55 V(SSEFloat64Abs) \
56 V(SSEFloat64Neg) \
Ben Murdochb8a8cc12014-11-26 15:28:44 +0000[diff] [blame]57 V(SSEFloat64Sqrt) \
Ben Murdoch4a90d5f2016-03-22 12:00:34 +0000[diff] [blame]58 V(SSEFloat64Round) \
59 V(SSEFloat32ToFloat64) \
60 V(SSEFloat64ToFloat32) \
Ben Murdoch097c5b22016-05-18 11:27:45 +0100[diff] [blame^]61 V(SSEFloat32ToInt32) \
62 V(SSEFloat32ToUint32) \
Ben Murdochb8a8cc12014-11-26 15:28:44 +0000[diff] [blame]63 V(SSEFloat64ToInt32) \
64 V(SSEFloat64ToUint32) \
Ben Murdoch097c5b22016-05-18 11:27:45 +0100[diff] [blame^]65 V(SSEInt32ToFloat32) \
66 V(SSEUint32ToFloat32) \
Ben Murdochb8a8cc12014-11-26 15:28:44 +0000[diff] [blame]67 V(SSEInt32ToFloat64) \
68 V(SSEUint32ToFloat64) \
Ben Murdoch4a90d5f2016-03-22 12:00:34 +0000[diff] [blame]69 V(SSEFloat64ExtractLowWord32) \
70 V(SSEFloat64ExtractHighWord32) \
71 V(SSEFloat64InsertLowWord32) \
72 V(SSEFloat64InsertHighWord32) \
73 V(SSEFloat64LoadLowWord32) \
74 V(AVXFloat32Add) \
75 V(AVXFloat32Sub) \
76 V(AVXFloat32Mul) \
77 V(AVXFloat32Div) \
78 V(AVXFloat32Max) \
79 V(AVXFloat32Min) \
Emily Bernierd0a1eb72015-03-24 16:35:39 -0400[diff] [blame]80 V(AVXFloat64Add) \
81 V(AVXFloat64Sub) \
82 V(AVXFloat64Mul) \
83 V(AVXFloat64Div) \
Ben Murdoch4a90d5f2016-03-22 12:00:34 +0000[diff] [blame]84 V(AVXFloat64Max) \
85 V(AVXFloat64Min) \
86 V(AVXFloat64Abs) \
87 V(AVXFloat64Neg) \
88 V(AVXFloat32Abs) \
89 V(AVXFloat32Neg) \
Ben Murdochb8a8cc12014-11-26 15:28:44 +0000[diff] [blame]90 V(IA32Movsxbl) \
91 V(IA32Movzxbl) \
92 V(IA32Movb) \
93 V(IA32Movsxwl) \
94 V(IA32Movzxwl) \
95 V(IA32Movw) \
96 V(IA32Movl) \
97 V(IA32Movss) \
98 V(IA32Movsd) \
Ben Murdoch4a90d5f2016-03-22 12:00:34 +0000[diff] [blame]99 V(IA32BitcastFI) \
100 V(IA32BitcastIF) \
Emily Bernierd0a1eb72015-03-24 16:35:39 -0400[diff] [blame]101 V(IA32Lea) \
Ben Murdochb8a8cc12014-11-26 15:28:44 +0000[diff] [blame]102 V(IA32Push) \
Ben Murdoch4a90d5f2016-03-22 12:00:34 +0000[diff] [blame]103 V(IA32PushFloat32) \
104 V(IA32PushFloat64) \
105 V(IA32Poke) \
106 V(IA32StackCheck)
Ben Murdochb8a8cc12014-11-26 15:28:44 +0000[diff] [blame]107
108
109// Addressing modes represent the "shape" of inputs to an instruction.
110// Many instructions support multiple addressing modes. Addressing modes
111// are encoded into the InstructionCode of the instruction and tell the
112// code generator after register allocation which assembler method to call.
113//
114// We use the following local notation for addressing modes:
115//
Emily Bernierd0a1eb72015-03-24 16:35:39 -0400[diff] [blame]116// M = memory operand
117// R = base register
118// N = index register * N for N in {1, 2, 4, 8}
119// I = immediate displacement (int32_t)
120
Ben Murdochb8a8cc12014-11-26 15:28:44 +0000[diff] [blame]121#define TARGET_ADDRESSING_MODE_LIST(V) \
Emily Bernierd0a1eb72015-03-24 16:35:39 -0400[diff] [blame]122 V(MR) /* [%r1 ] */ \
123 V(MRI) /* [%r1 + K] */ \
124 V(MR1) /* [%r1 + %r2*1 ] */ \
125 V(MR2) /* [%r1 + %r2*2 ] */ \
126 V(MR4) /* [%r1 + %r2*4 ] */ \
127 V(MR8) /* [%r1 + %r2*8 ] */ \
128 V(MR1I) /* [%r1 + %r2*1 + K] */ \
129 V(MR2I) /* [%r1 + %r2*2 + K] */ \
130 V(MR4I) /* [%r1 + %r2*3 + K] */ \
131 V(MR8I) /* [%r1 + %r2*4 + K] */ \
132 V(M1) /* [ %r2*1 ] */ \
133 V(M2) /* [ %r2*2 ] */ \
134 V(M4) /* [ %r2*4 ] */ \
135 V(M8) /* [ %r2*8 ] */ \
136 V(M1I) /* [ %r2*1 + K] */ \
137 V(M2I) /* [ %r2*2 + K] */ \
138 V(M4I) /* [ %r2*4 + K] */ \
139 V(M8I) /* [ %r2*8 + K] */ \
140 V(MI) /* [ K] */
Ben Murdochb8a8cc12014-11-26 15:28:44 +0000[diff] [blame]141
142} // namespace compiler
143} // namespace internal
144} // namespace v8
145
146#endif // V8_COMPILER_IA32_INSTRUCTION_CODES_IA32_H_