Steve Block | a7e24c1 | 2009-10-30 11:49:00 +0000 | [diff] [blame] | 1 | // Copyright (c) 1994-2006 Sun Microsystems Inc. |
| 2 | // All Rights Reserved. |
| 3 | // |
| 4 | // Redistribution and use in source and binary forms, with or without |
| 5 | // modification, are permitted provided that the following conditions |
| 6 | // are met: |
| 7 | // |
| 8 | // - Redistributions of source code must retain the above copyright notice, |
| 9 | // this list of conditions and the following disclaimer. |
| 10 | // |
| 11 | // - Redistribution in binary form must reproduce the above copyright |
| 12 | // notice, this list of conditions and the following disclaimer in the |
| 13 | // documentation and/or other materials provided with the |
| 14 | // distribution. |
| 15 | // |
| 16 | // - Neither the name of Sun Microsystems or the names of contributors may |
| 17 | // be used to endorse or promote products derived from this software without |
| 18 | // specific prior written permission. |
| 19 | // |
| 20 | // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS |
| 21 | // "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT |
| 22 | // LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS |
| 23 | // FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE |
| 24 | // COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, |
| 25 | // INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES |
| 26 | // (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR |
| 27 | // SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) |
| 28 | // HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, |
| 29 | // STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) |
| 30 | // ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED |
| 31 | // OF THE POSSIBILITY OF SUCH DAMAGE. |
| 32 | |
Leon Clarke | d91b9f7 | 2010-01-27 17:25:45 +0000 | [diff] [blame] | 33 | // The original source code covered by the above license above has been |
| 34 | // modified significantly by Google Inc. |
| 35 | // Copyright 2010 the V8 project authors. All rights reserved. |
Steve Block | a7e24c1 | 2009-10-30 11:49:00 +0000 | [diff] [blame] | 36 | |
| 37 | // A light-weight ARM Assembler |
| 38 | // Generates user mode instructions for the ARM architecture up to version 5 |
| 39 | |
| 40 | #ifndef V8_ARM_ASSEMBLER_ARM_H_ |
| 41 | #define V8_ARM_ASSEMBLER_ARM_H_ |
| 42 | #include <stdio.h> |
| 43 | #include "assembler.h" |
Steve Block | d0582a6 | 2009-12-15 09:54:21 +0000 | [diff] [blame] | 44 | #include "serialize.h" |
Steve Block | a7e24c1 | 2009-10-30 11:49:00 +0000 | [diff] [blame] | 45 | |
| 46 | namespace v8 { |
| 47 | namespace internal { |
| 48 | |
| 49 | // CPU Registers. |
| 50 | // |
| 51 | // 1) We would prefer to use an enum, but enum values are assignment- |
| 52 | // compatible with int, which has caused code-generation bugs. |
| 53 | // |
| 54 | // 2) We would prefer to use a class instead of a struct but we don't like |
| 55 | // the register initialization to depend on the particular initialization |
| 56 | // order (which appears to be different on OS X, Linux, and Windows for the |
| 57 | // installed versions of C++ we tried). Using a struct permits C-style |
| 58 | // "initialization". Also, the Register objects cannot be const as this |
| 59 | // forces initialization stubs in MSVC, making us dependent on initialization |
| 60 | // order. |
| 61 | // |
| 62 | // 3) By not using an enum, we are possibly preventing the compiler from |
| 63 | // doing certain constant folds, which may significantly reduce the |
| 64 | // code generated for some assembly instructions (because they boil down |
| 65 | // to a few constants). If this is a problem, we could change the code |
| 66 | // such that we use an enum in optimized mode, and the struct in debug |
| 67 | // mode. This way we get the compile-time error checking in debug mode |
| 68 | // and best performance in optimized code. |
| 69 | // |
| 70 | // Core register |
| 71 | struct Register { |
| 72 | bool is_valid() const { return 0 <= code_ && code_ < 16; } |
| 73 | bool is(Register reg) const { return code_ == reg.code_; } |
| 74 | int code() const { |
| 75 | ASSERT(is_valid()); |
| 76 | return code_; |
| 77 | } |
| 78 | int bit() const { |
| 79 | ASSERT(is_valid()); |
| 80 | return 1 << code_; |
| 81 | } |
| 82 | |
Andrei Popescu | 3100271 | 2010-02-23 13:46:05 +0000 | [diff] [blame] | 83 | // Unfortunately we can't make this private in a struct. |
Steve Block | a7e24c1 | 2009-10-30 11:49:00 +0000 | [diff] [blame] | 84 | int code_; |
| 85 | }; |
| 86 | |
Steve Block | 6ded16b | 2010-05-10 14:33:55 +0100 | [diff] [blame] | 87 | const Register no_reg = { -1 }; |
Steve Block | a7e24c1 | 2009-10-30 11:49:00 +0000 | [diff] [blame] | 88 | |
Steve Block | 6ded16b | 2010-05-10 14:33:55 +0100 | [diff] [blame] | 89 | const Register r0 = { 0 }; |
| 90 | const Register r1 = { 1 }; |
| 91 | const Register r2 = { 2 }; |
| 92 | const Register r3 = { 3 }; |
| 93 | const Register r4 = { 4 }; |
| 94 | const Register r5 = { 5 }; |
| 95 | const Register r6 = { 6 }; |
| 96 | const Register r7 = { 7 }; |
| 97 | const Register r8 = { 8 }; // Used as context register. |
| 98 | const Register r9 = { 9 }; |
| 99 | const Register r10 = { 10 }; // Used as roots register. |
| 100 | const Register fp = { 11 }; |
| 101 | const Register ip = { 12 }; |
| 102 | const Register sp = { 13 }; |
| 103 | const Register lr = { 14 }; |
| 104 | const Register pc = { 15 }; |
Steve Block | d0582a6 | 2009-12-15 09:54:21 +0000 | [diff] [blame] | 105 | |
Leon Clarke | e46be81 | 2010-01-19 14:06:41 +0000 | [diff] [blame] | 106 | // Single word VFP register. |
| 107 | struct SwVfpRegister { |
| 108 | bool is_valid() const { return 0 <= code_ && code_ < 32; } |
| 109 | bool is(SwVfpRegister reg) const { return code_ == reg.code_; } |
| 110 | int code() const { |
| 111 | ASSERT(is_valid()); |
| 112 | return code_; |
| 113 | } |
| 114 | int bit() const { |
| 115 | ASSERT(is_valid()); |
| 116 | return 1 << code_; |
| 117 | } |
| 118 | |
| 119 | int code_; |
| 120 | }; |
| 121 | |
| 122 | |
| 123 | // Double word VFP register. |
| 124 | struct DwVfpRegister { |
| 125 | // Supporting d0 to d15, can be later extended to d31. |
| 126 | bool is_valid() const { return 0 <= code_ && code_ < 16; } |
| 127 | bool is(DwVfpRegister reg) const { return code_ == reg.code_; } |
| 128 | int code() const { |
| 129 | ASSERT(is_valid()); |
| 130 | return code_; |
| 131 | } |
| 132 | int bit() const { |
| 133 | ASSERT(is_valid()); |
| 134 | return 1 << code_; |
| 135 | } |
| 136 | |
| 137 | int code_; |
| 138 | }; |
| 139 | |
| 140 | |
Steve Block | 6ded16b | 2010-05-10 14:33:55 +0100 | [diff] [blame] | 141 | // Support for the VFP registers s0 to s31 (d0 to d15). |
Leon Clarke | e46be81 | 2010-01-19 14:06:41 +0000 | [diff] [blame] | 142 | // Note that "s(N):s(N+1)" is the same as "d(N/2)". |
Steve Block | 6ded16b | 2010-05-10 14:33:55 +0100 | [diff] [blame] | 143 | const SwVfpRegister s0 = { 0 }; |
| 144 | const SwVfpRegister s1 = { 1 }; |
| 145 | const SwVfpRegister s2 = { 2 }; |
| 146 | const SwVfpRegister s3 = { 3 }; |
| 147 | const SwVfpRegister s4 = { 4 }; |
| 148 | const SwVfpRegister s5 = { 5 }; |
| 149 | const SwVfpRegister s6 = { 6 }; |
| 150 | const SwVfpRegister s7 = { 7 }; |
| 151 | const SwVfpRegister s8 = { 8 }; |
| 152 | const SwVfpRegister s9 = { 9 }; |
| 153 | const SwVfpRegister s10 = { 10 }; |
| 154 | const SwVfpRegister s11 = { 11 }; |
| 155 | const SwVfpRegister s12 = { 12 }; |
| 156 | const SwVfpRegister s13 = { 13 }; |
| 157 | const SwVfpRegister s14 = { 14 }; |
| 158 | const SwVfpRegister s15 = { 15 }; |
| 159 | const SwVfpRegister s16 = { 16 }; |
| 160 | const SwVfpRegister s17 = { 17 }; |
| 161 | const SwVfpRegister s18 = { 18 }; |
| 162 | const SwVfpRegister s19 = { 19 }; |
| 163 | const SwVfpRegister s20 = { 20 }; |
| 164 | const SwVfpRegister s21 = { 21 }; |
| 165 | const SwVfpRegister s22 = { 22 }; |
| 166 | const SwVfpRegister s23 = { 23 }; |
| 167 | const SwVfpRegister s24 = { 24 }; |
| 168 | const SwVfpRegister s25 = { 25 }; |
| 169 | const SwVfpRegister s26 = { 26 }; |
| 170 | const SwVfpRegister s27 = { 27 }; |
| 171 | const SwVfpRegister s28 = { 28 }; |
| 172 | const SwVfpRegister s29 = { 29 }; |
| 173 | const SwVfpRegister s30 = { 30 }; |
| 174 | const SwVfpRegister s31 = { 31 }; |
Leon Clarke | e46be81 | 2010-01-19 14:06:41 +0000 | [diff] [blame] | 175 | |
Steve Block | 6ded16b | 2010-05-10 14:33:55 +0100 | [diff] [blame] | 176 | const DwVfpRegister d0 = { 0 }; |
| 177 | const DwVfpRegister d1 = { 1 }; |
| 178 | const DwVfpRegister d2 = { 2 }; |
| 179 | const DwVfpRegister d3 = { 3 }; |
| 180 | const DwVfpRegister d4 = { 4 }; |
| 181 | const DwVfpRegister d5 = { 5 }; |
| 182 | const DwVfpRegister d6 = { 6 }; |
| 183 | const DwVfpRegister d7 = { 7 }; |
| 184 | const DwVfpRegister d8 = { 8 }; |
| 185 | const DwVfpRegister d9 = { 9 }; |
| 186 | const DwVfpRegister d10 = { 10 }; |
| 187 | const DwVfpRegister d11 = { 11 }; |
| 188 | const DwVfpRegister d12 = { 12 }; |
| 189 | const DwVfpRegister d13 = { 13 }; |
| 190 | const DwVfpRegister d14 = { 14 }; |
| 191 | const DwVfpRegister d15 = { 15 }; |
Leon Clarke | e46be81 | 2010-01-19 14:06:41 +0000 | [diff] [blame] | 192 | |
Steve Block | a7e24c1 | 2009-10-30 11:49:00 +0000 | [diff] [blame] | 193 | |
| 194 | // Coprocessor register |
| 195 | struct CRegister { |
| 196 | bool is_valid() const { return 0 <= code_ && code_ < 16; } |
| 197 | bool is(CRegister creg) const { return code_ == creg.code_; } |
| 198 | int code() const { |
| 199 | ASSERT(is_valid()); |
| 200 | return code_; |
| 201 | } |
| 202 | int bit() const { |
| 203 | ASSERT(is_valid()); |
| 204 | return 1 << code_; |
| 205 | } |
| 206 | |
Andrei Popescu | 3100271 | 2010-02-23 13:46:05 +0000 | [diff] [blame] | 207 | // Unfortunately we can't make this private in a struct. |
Steve Block | a7e24c1 | 2009-10-30 11:49:00 +0000 | [diff] [blame] | 208 | int code_; |
| 209 | }; |
| 210 | |
| 211 | |
Steve Block | 6ded16b | 2010-05-10 14:33:55 +0100 | [diff] [blame] | 212 | const CRegister no_creg = { -1 }; |
| 213 | |
| 214 | const CRegister cr0 = { 0 }; |
| 215 | const CRegister cr1 = { 1 }; |
| 216 | const CRegister cr2 = { 2 }; |
| 217 | const CRegister cr3 = { 3 }; |
| 218 | const CRegister cr4 = { 4 }; |
| 219 | const CRegister cr5 = { 5 }; |
| 220 | const CRegister cr6 = { 6 }; |
| 221 | const CRegister cr7 = { 7 }; |
| 222 | const CRegister cr8 = { 8 }; |
| 223 | const CRegister cr9 = { 9 }; |
| 224 | const CRegister cr10 = { 10 }; |
| 225 | const CRegister cr11 = { 11 }; |
| 226 | const CRegister cr12 = { 12 }; |
| 227 | const CRegister cr13 = { 13 }; |
| 228 | const CRegister cr14 = { 14 }; |
| 229 | const CRegister cr15 = { 15 }; |
Steve Block | a7e24c1 | 2009-10-30 11:49:00 +0000 | [diff] [blame] | 230 | |
| 231 | |
| 232 | // Coprocessor number |
| 233 | enum Coprocessor { |
| 234 | p0 = 0, |
| 235 | p1 = 1, |
| 236 | p2 = 2, |
| 237 | p3 = 3, |
| 238 | p4 = 4, |
| 239 | p5 = 5, |
| 240 | p6 = 6, |
| 241 | p7 = 7, |
| 242 | p8 = 8, |
| 243 | p9 = 9, |
| 244 | p10 = 10, |
| 245 | p11 = 11, |
| 246 | p12 = 12, |
| 247 | p13 = 13, |
| 248 | p14 = 14, |
| 249 | p15 = 15 |
| 250 | }; |
| 251 | |
| 252 | |
Andrei Popescu | 3100271 | 2010-02-23 13:46:05 +0000 | [diff] [blame] | 253 | // Condition field in instructions. |
Steve Block | a7e24c1 | 2009-10-30 11:49:00 +0000 | [diff] [blame] | 254 | enum Condition { |
| 255 | eq = 0 << 28, // Z set equal. |
| 256 | ne = 1 << 28, // Z clear not equal. |
| 257 | nz = 1 << 28, // Z clear not zero. |
| 258 | cs = 2 << 28, // C set carry set. |
| 259 | hs = 2 << 28, // C set unsigned higher or same. |
| 260 | cc = 3 << 28, // C clear carry clear. |
| 261 | lo = 3 << 28, // C clear unsigned lower. |
| 262 | mi = 4 << 28, // N set negative. |
| 263 | pl = 5 << 28, // N clear positive or zero. |
| 264 | vs = 6 << 28, // V set overflow. |
| 265 | vc = 7 << 28, // V clear no overflow. |
| 266 | hi = 8 << 28, // C set, Z clear unsigned higher. |
| 267 | ls = 9 << 28, // C clear or Z set unsigned lower or same. |
| 268 | ge = 10 << 28, // N == V greater or equal. |
| 269 | lt = 11 << 28, // N != V less than. |
| 270 | gt = 12 << 28, // Z clear, N == V greater than. |
| 271 | le = 13 << 28, // Z set or N != V less then or equal |
| 272 | al = 14 << 28 // always. |
| 273 | }; |
| 274 | |
| 275 | |
| 276 | // Returns the equivalent of !cc. |
| 277 | INLINE(Condition NegateCondition(Condition cc)); |
| 278 | |
| 279 | |
| 280 | // Corresponds to transposing the operands of a comparison. |
| 281 | inline Condition ReverseCondition(Condition cc) { |
| 282 | switch (cc) { |
| 283 | case lo: |
| 284 | return hi; |
| 285 | case hi: |
| 286 | return lo; |
| 287 | case hs: |
| 288 | return ls; |
| 289 | case ls: |
| 290 | return hs; |
| 291 | case lt: |
| 292 | return gt; |
| 293 | case gt: |
| 294 | return lt; |
| 295 | case ge: |
| 296 | return le; |
| 297 | case le: |
| 298 | return ge; |
| 299 | default: |
| 300 | return cc; |
| 301 | }; |
| 302 | } |
| 303 | |
| 304 | |
| 305 | // Branch hints are not used on the ARM. They are defined so that they can |
| 306 | // appear in shared function signatures, but will be ignored in ARM |
| 307 | // implementations. |
| 308 | enum Hint { no_hint }; |
| 309 | |
| 310 | // Hints are not used on the arm. Negating is trivial. |
| 311 | inline Hint NegateHint(Hint ignored) { return no_hint; } |
| 312 | |
| 313 | |
| 314 | // ----------------------------------------------------------------------------- |
| 315 | // Addressing modes and instruction variants |
| 316 | |
| 317 | // Shifter operand shift operation |
| 318 | enum ShiftOp { |
| 319 | LSL = 0 << 5, |
| 320 | LSR = 1 << 5, |
| 321 | ASR = 2 << 5, |
| 322 | ROR = 3 << 5, |
| 323 | RRX = -1 |
| 324 | }; |
| 325 | |
| 326 | |
| 327 | // Condition code updating mode |
| 328 | enum SBit { |
| 329 | SetCC = 1 << 20, // set condition code |
| 330 | LeaveCC = 0 << 20 // leave condition code unchanged |
| 331 | }; |
| 332 | |
| 333 | |
| 334 | // Status register selection |
| 335 | enum SRegister { |
| 336 | CPSR = 0 << 22, |
| 337 | SPSR = 1 << 22 |
| 338 | }; |
| 339 | |
| 340 | |
| 341 | // Status register fields |
| 342 | enum SRegisterField { |
| 343 | CPSR_c = CPSR | 1 << 16, |
| 344 | CPSR_x = CPSR | 1 << 17, |
| 345 | CPSR_s = CPSR | 1 << 18, |
| 346 | CPSR_f = CPSR | 1 << 19, |
| 347 | SPSR_c = SPSR | 1 << 16, |
| 348 | SPSR_x = SPSR | 1 << 17, |
| 349 | SPSR_s = SPSR | 1 << 18, |
| 350 | SPSR_f = SPSR | 1 << 19 |
| 351 | }; |
| 352 | |
| 353 | // Status register field mask (or'ed SRegisterField enum values) |
| 354 | typedef uint32_t SRegisterFieldMask; |
| 355 | |
| 356 | |
| 357 | // Memory operand addressing mode |
| 358 | enum AddrMode { |
| 359 | // bit encoding P U W |
| 360 | Offset = (8|4|0) << 21, // offset (without writeback to base) |
| 361 | PreIndex = (8|4|1) << 21, // pre-indexed addressing with writeback |
| 362 | PostIndex = (0|4|0) << 21, // post-indexed addressing with writeback |
| 363 | NegOffset = (8|0|0) << 21, // negative offset (without writeback to base) |
| 364 | NegPreIndex = (8|0|1) << 21, // negative pre-indexed with writeback |
| 365 | NegPostIndex = (0|0|0) << 21 // negative post-indexed with writeback |
| 366 | }; |
| 367 | |
| 368 | |
| 369 | // Load/store multiple addressing mode |
| 370 | enum BlockAddrMode { |
| 371 | // bit encoding P U W |
| 372 | da = (0|0|0) << 21, // decrement after |
| 373 | ia = (0|4|0) << 21, // increment after |
| 374 | db = (8|0|0) << 21, // decrement before |
| 375 | ib = (8|4|0) << 21, // increment before |
| 376 | da_w = (0|0|1) << 21, // decrement after with writeback to base |
| 377 | ia_w = (0|4|1) << 21, // increment after with writeback to base |
| 378 | db_w = (8|0|1) << 21, // decrement before with writeback to base |
| 379 | ib_w = (8|4|1) << 21 // increment before with writeback to base |
| 380 | }; |
| 381 | |
| 382 | |
| 383 | // Coprocessor load/store operand size |
| 384 | enum LFlag { |
| 385 | Long = 1 << 22, // long load/store coprocessor |
| 386 | Short = 0 << 22 // short load/store coprocessor |
| 387 | }; |
| 388 | |
| 389 | |
| 390 | // ----------------------------------------------------------------------------- |
| 391 | // Machine instruction Operands |
| 392 | |
| 393 | // Class Operand represents a shifter operand in data processing instructions |
| 394 | class Operand BASE_EMBEDDED { |
| 395 | public: |
| 396 | // immediate |
| 397 | INLINE(explicit Operand(int32_t immediate, |
| 398 | RelocInfo::Mode rmode = RelocInfo::NONE)); |
| 399 | INLINE(explicit Operand(const ExternalReference& f)); |
| 400 | INLINE(explicit Operand(const char* s)); |
Steve Block | a7e24c1 | 2009-10-30 11:49:00 +0000 | [diff] [blame] | 401 | explicit Operand(Handle<Object> handle); |
| 402 | INLINE(explicit Operand(Smi* value)); |
| 403 | |
| 404 | // rm |
| 405 | INLINE(explicit Operand(Register rm)); |
| 406 | |
| 407 | // rm <shift_op> shift_imm |
| 408 | explicit Operand(Register rm, ShiftOp shift_op, int shift_imm); |
| 409 | |
| 410 | // rm <shift_op> rs |
| 411 | explicit Operand(Register rm, ShiftOp shift_op, Register rs); |
| 412 | |
| 413 | // Return true if this is a register operand. |
| 414 | INLINE(bool is_reg() const); |
| 415 | |
| 416 | Register rm() const { return rm_; } |
| 417 | |
| 418 | private: |
| 419 | Register rm_; |
| 420 | Register rs_; |
| 421 | ShiftOp shift_op_; |
| 422 | int shift_imm_; // valid if rm_ != no_reg && rs_ == no_reg |
| 423 | int32_t imm32_; // valid if rm_ == no_reg |
| 424 | RelocInfo::Mode rmode_; |
| 425 | |
| 426 | friend class Assembler; |
| 427 | }; |
| 428 | |
| 429 | |
| 430 | // Class MemOperand represents a memory operand in load and store instructions |
| 431 | class MemOperand BASE_EMBEDDED { |
| 432 | public: |
| 433 | // [rn +/- offset] Offset/NegOffset |
| 434 | // [rn +/- offset]! PreIndex/NegPreIndex |
| 435 | // [rn], +/- offset PostIndex/NegPostIndex |
| 436 | // offset is any signed 32-bit value; offset is first loaded to register ip if |
| 437 | // it does not fit the addressing mode (12-bit unsigned and sign bit) |
| 438 | explicit MemOperand(Register rn, int32_t offset = 0, AddrMode am = Offset); |
| 439 | |
| 440 | // [rn +/- rm] Offset/NegOffset |
| 441 | // [rn +/- rm]! PreIndex/NegPreIndex |
| 442 | // [rn], +/- rm PostIndex/NegPostIndex |
| 443 | explicit MemOperand(Register rn, Register rm, AddrMode am = Offset); |
| 444 | |
| 445 | // [rn +/- rm <shift_op> shift_imm] Offset/NegOffset |
| 446 | // [rn +/- rm <shift_op> shift_imm]! PreIndex/NegPreIndex |
| 447 | // [rn], +/- rm <shift_op> shift_imm PostIndex/NegPostIndex |
| 448 | explicit MemOperand(Register rn, Register rm, |
| 449 | ShiftOp shift_op, int shift_imm, AddrMode am = Offset); |
| 450 | |
Kristian Monsen | 25f6136 | 2010-05-21 11:50:48 +0100 | [diff] [blame^] | 451 | void set_offset(int32_t offset) { |
| 452 | ASSERT(rm_.is(no_reg)); |
| 453 | offset_ = offset; |
| 454 | } |
| 455 | |
| 456 | uint32_t offset() { |
| 457 | ASSERT(rm_.is(no_reg)); |
| 458 | return offset_; |
| 459 | } |
| 460 | |
| 461 | Register rm() const {return rm_;} |
| 462 | |
Steve Block | a7e24c1 | 2009-10-30 11:49:00 +0000 | [diff] [blame] | 463 | private: |
| 464 | Register rn_; // base |
| 465 | Register rm_; // register offset |
| 466 | int32_t offset_; // valid if rm_ == no_reg |
| 467 | ShiftOp shift_op_; |
| 468 | int shift_imm_; // valid if rm_ != no_reg && rs_ == no_reg |
| 469 | AddrMode am_; // bits P, U, and W |
| 470 | |
| 471 | friend class Assembler; |
| 472 | }; |
| 473 | |
Steve Block | d0582a6 | 2009-12-15 09:54:21 +0000 | [diff] [blame] | 474 | // CpuFeatures keeps track of which features are supported by the target CPU. |
| 475 | // Supported features must be enabled by a Scope before use. |
| 476 | class CpuFeatures : public AllStatic { |
| 477 | public: |
| 478 | // Detect features of the target CPU. Set safe defaults if the serializer |
| 479 | // is enabled (snapshots must be portable). |
| 480 | static void Probe(); |
| 481 | |
| 482 | // Check whether a feature is supported by the target CPU. |
| 483 | static bool IsSupported(CpuFeature f) { |
| 484 | if (f == VFP3 && !FLAG_enable_vfp3) return false; |
| 485 | return (supported_ & (1u << f)) != 0; |
| 486 | } |
| 487 | |
| 488 | // Check whether a feature is currently enabled. |
| 489 | static bool IsEnabled(CpuFeature f) { |
| 490 | return (enabled_ & (1u << f)) != 0; |
| 491 | } |
| 492 | |
| 493 | // Enable a specified feature within a scope. |
| 494 | class Scope BASE_EMBEDDED { |
| 495 | #ifdef DEBUG |
| 496 | public: |
| 497 | explicit Scope(CpuFeature f) { |
| 498 | ASSERT(CpuFeatures::IsSupported(f)); |
| 499 | ASSERT(!Serializer::enabled() || |
| 500 | (found_by_runtime_probing_ & (1u << f)) == 0); |
| 501 | old_enabled_ = CpuFeatures::enabled_; |
| 502 | CpuFeatures::enabled_ |= 1u << f; |
| 503 | } |
| 504 | ~Scope() { CpuFeatures::enabled_ = old_enabled_; } |
| 505 | private: |
| 506 | unsigned old_enabled_; |
| 507 | #else |
| 508 | public: |
| 509 | explicit Scope(CpuFeature f) {} |
| 510 | #endif |
| 511 | }; |
| 512 | |
| 513 | private: |
| 514 | static unsigned supported_; |
| 515 | static unsigned enabled_; |
| 516 | static unsigned found_by_runtime_probing_; |
| 517 | }; |
| 518 | |
Steve Block | a7e24c1 | 2009-10-30 11:49:00 +0000 | [diff] [blame] | 519 | |
| 520 | typedef int32_t Instr; |
| 521 | |
| 522 | |
| 523 | extern const Instr kMovLrPc; |
Steve Block | 6ded16b | 2010-05-10 14:33:55 +0100 | [diff] [blame] | 524 | extern const Instr kLdrPCMask; |
Steve Block | a7e24c1 | 2009-10-30 11:49:00 +0000 | [diff] [blame] | 525 | extern const Instr kLdrPCPattern; |
Steve Block | 6ded16b | 2010-05-10 14:33:55 +0100 | [diff] [blame] | 526 | extern const Instr kBlxRegMask; |
| 527 | extern const Instr kBlxRegPattern; |
Steve Block | a7e24c1 | 2009-10-30 11:49:00 +0000 | [diff] [blame] | 528 | |
| 529 | |
| 530 | class Assembler : public Malloced { |
| 531 | public: |
| 532 | // Create an assembler. Instructions and relocation information are emitted |
| 533 | // into a buffer, with the instructions starting from the beginning and the |
| 534 | // relocation information starting from the end of the buffer. See CodeDesc |
| 535 | // for a detailed comment on the layout (globals.h). |
| 536 | // |
| 537 | // If the provided buffer is NULL, the assembler allocates and grows its own |
| 538 | // buffer, and buffer_size determines the initial buffer size. The buffer is |
| 539 | // owned by the assembler and deallocated upon destruction of the assembler. |
| 540 | // |
| 541 | // If the provided buffer is not NULL, the assembler uses the provided buffer |
| 542 | // for code generation and assumes its size to be buffer_size. If the buffer |
| 543 | // is too small, a fatal error occurs. No deallocation of the buffer is done |
| 544 | // upon destruction of the assembler. |
| 545 | Assembler(void* buffer, int buffer_size); |
| 546 | ~Assembler(); |
| 547 | |
| 548 | // GetCode emits any pending (non-emitted) code and fills the descriptor |
| 549 | // desc. GetCode() is idempotent; it returns the same result if no other |
| 550 | // Assembler functions are invoked in between GetCode() calls. |
| 551 | void GetCode(CodeDesc* desc); |
| 552 | |
| 553 | // Label operations & relative jumps (PPUM Appendix D) |
| 554 | // |
| 555 | // Takes a branch opcode (cc) and a label (L) and generates |
| 556 | // either a backward branch or a forward branch and links it |
| 557 | // to the label fixup chain. Usage: |
| 558 | // |
| 559 | // Label L; // unbound label |
| 560 | // j(cc, &L); // forward branch to unbound label |
| 561 | // bind(&L); // bind label to the current pc |
| 562 | // j(cc, &L); // backward branch to bound label |
| 563 | // bind(&L); // illegal: a label may be bound only once |
| 564 | // |
| 565 | // Note: The same Label can be used for forward and backward branches |
| 566 | // but it may be bound only once. |
| 567 | |
| 568 | void bind(Label* L); // binds an unbound label L to the current code position |
| 569 | |
| 570 | // Returns the branch offset to the given label from the current code position |
| 571 | // Links the label to the current position if it is still unbound |
| 572 | // Manages the jump elimination optimization if the second parameter is true. |
| 573 | int branch_offset(Label* L, bool jump_elimination_allowed); |
| 574 | |
| 575 | // Puts a labels target address at the given position. |
| 576 | // The high 8 bits are set to zero. |
| 577 | void label_at_put(Label* L, int at_offset); |
| 578 | |
| 579 | // Return the address in the constant pool of the code target address used by |
| 580 | // the branch/call instruction at pc. |
| 581 | INLINE(static Address target_address_address_at(Address pc)); |
| 582 | |
| 583 | // Read/Modify the code target address in the branch/call instruction at pc. |
| 584 | INLINE(static Address target_address_at(Address pc)); |
| 585 | INLINE(static void set_target_address_at(Address pc, Address target)); |
| 586 | |
Steve Block | d0582a6 | 2009-12-15 09:54:21 +0000 | [diff] [blame] | 587 | // This sets the branch destination (which is in the constant pool on ARM). |
| 588 | // This is for calls and branches within generated code. |
| 589 | inline static void set_target_at(Address constant_pool_entry, Address target); |
| 590 | |
| 591 | // This sets the branch destination (which is in the constant pool on ARM). |
| 592 | // This is for calls and branches to runtime code. |
| 593 | inline static void set_external_target_at(Address constant_pool_entry, |
| 594 | Address target) { |
| 595 | set_target_at(constant_pool_entry, target); |
| 596 | } |
| 597 | |
| 598 | // Here we are patching the address in the constant pool, not the actual call |
| 599 | // instruction. The address in the constant pool is the same size as a |
| 600 | // pointer. |
| 601 | static const int kCallTargetSize = kPointerSize; |
| 602 | static const int kExternalTargetSize = kPointerSize; |
| 603 | |
Steve Block | a7e24c1 | 2009-10-30 11:49:00 +0000 | [diff] [blame] | 604 | // Size of an instruction. |
| 605 | static const int kInstrSize = sizeof(Instr); |
| 606 | |
| 607 | // Distance between the instruction referring to the address of the call |
Steve Block | 6ded16b | 2010-05-10 14:33:55 +0100 | [diff] [blame] | 608 | // target and the return address. |
| 609 | #ifdef USE_BLX |
| 610 | // Call sequence is: |
| 611 | // ldr ip, [pc, #...] @ call address |
| 612 | // blx ip |
| 613 | // @ return address |
| 614 | static const int kCallTargetAddressOffset = 2 * kInstrSize; |
| 615 | #else |
| 616 | // Call sequence is: |
| 617 | // mov lr, pc |
| 618 | // ldr pc, [pc, #...] @ call address |
| 619 | // @ return address |
Steve Block | a7e24c1 | 2009-10-30 11:49:00 +0000 | [diff] [blame] | 620 | static const int kCallTargetAddressOffset = kInstrSize; |
Steve Block | 6ded16b | 2010-05-10 14:33:55 +0100 | [diff] [blame] | 621 | #endif |
Steve Block | a7e24c1 | 2009-10-30 11:49:00 +0000 | [diff] [blame] | 622 | |
| 623 | // Distance between start of patched return sequence and the emitted address |
| 624 | // to jump to. |
Steve Block | 6ded16b | 2010-05-10 14:33:55 +0100 | [diff] [blame] | 625 | #ifdef USE_BLX |
| 626 | // Return sequence is: |
| 627 | // ldr ip, [pc, #0] @ emited address and start |
| 628 | // blx ip |
| 629 | static const int kPatchReturnSequenceAddressOffset = 0 * kInstrSize; |
| 630 | #else |
| 631 | // Return sequence is: |
| 632 | // mov lr, pc @ start of sequence |
| 633 | // ldr pc, [pc, #-4] @ emited address |
| 634 | static const int kPatchReturnSequenceAddressOffset = kInstrSize; |
| 635 | #endif |
Steve Block | a7e24c1 | 2009-10-30 11:49:00 +0000 | [diff] [blame] | 636 | |
| 637 | // Difference between address of current opcode and value read from pc |
| 638 | // register. |
| 639 | static const int kPcLoadDelta = 8; |
| 640 | |
Steve Block | d0582a6 | 2009-12-15 09:54:21 +0000 | [diff] [blame] | 641 | static const int kJSReturnSequenceLength = 4; |
Steve Block | a7e24c1 | 2009-10-30 11:49:00 +0000 | [diff] [blame] | 642 | |
| 643 | // --------------------------------------------------------------------------- |
| 644 | // Code generation |
| 645 | |
| 646 | // Insert the smallest number of nop instructions |
| 647 | // possible to align the pc offset to a multiple |
| 648 | // of m. m must be a power of 2 (>= 4). |
| 649 | void Align(int m); |
| 650 | |
| 651 | // Branch instructions |
| 652 | void b(int branch_offset, Condition cond = al); |
| 653 | void bl(int branch_offset, Condition cond = al); |
| 654 | void blx(int branch_offset); // v5 and above |
| 655 | void blx(Register target, Condition cond = al); // v5 and above |
| 656 | void bx(Register target, Condition cond = al); // v5 and above, plus v4t |
| 657 | |
| 658 | // Convenience branch instructions using labels |
| 659 | void b(Label* L, Condition cond = al) { |
| 660 | b(branch_offset(L, cond == al), cond); |
| 661 | } |
| 662 | void b(Condition cond, Label* L) { b(branch_offset(L, cond == al), cond); } |
| 663 | void bl(Label* L, Condition cond = al) { bl(branch_offset(L, false), cond); } |
| 664 | void bl(Condition cond, Label* L) { bl(branch_offset(L, false), cond); } |
| 665 | void blx(Label* L) { blx(branch_offset(L, false)); } // v5 and above |
| 666 | |
| 667 | // Data-processing instructions |
Andrei Popescu | 3100271 | 2010-02-23 13:46:05 +0000 | [diff] [blame] | 668 | void ubfx(Register dst, Register src1, const Operand& src2, |
| 669 | const Operand& src3, Condition cond = al); |
| 670 | |
Steve Block | a7e24c1 | 2009-10-30 11:49:00 +0000 | [diff] [blame] | 671 | void and_(Register dst, Register src1, const Operand& src2, |
| 672 | SBit s = LeaveCC, Condition cond = al); |
| 673 | |
| 674 | void eor(Register dst, Register src1, const Operand& src2, |
| 675 | SBit s = LeaveCC, Condition cond = al); |
| 676 | |
| 677 | void sub(Register dst, Register src1, const Operand& src2, |
| 678 | SBit s = LeaveCC, Condition cond = al); |
| 679 | void sub(Register dst, Register src1, Register src2, |
| 680 | SBit s = LeaveCC, Condition cond = al) { |
| 681 | sub(dst, src1, Operand(src2), s, cond); |
| 682 | } |
| 683 | |
| 684 | void rsb(Register dst, Register src1, const Operand& src2, |
| 685 | SBit s = LeaveCC, Condition cond = al); |
| 686 | |
| 687 | void add(Register dst, Register src1, const Operand& src2, |
| 688 | SBit s = LeaveCC, Condition cond = al); |
| 689 | |
| 690 | void adc(Register dst, Register src1, const Operand& src2, |
| 691 | SBit s = LeaveCC, Condition cond = al); |
| 692 | |
| 693 | void sbc(Register dst, Register src1, const Operand& src2, |
| 694 | SBit s = LeaveCC, Condition cond = al); |
| 695 | |
| 696 | void rsc(Register dst, Register src1, const Operand& src2, |
| 697 | SBit s = LeaveCC, Condition cond = al); |
| 698 | |
| 699 | void tst(Register src1, const Operand& src2, Condition cond = al); |
| 700 | void tst(Register src1, Register src2, Condition cond = al) { |
| 701 | tst(src1, Operand(src2), cond); |
| 702 | } |
| 703 | |
| 704 | void teq(Register src1, const Operand& src2, Condition cond = al); |
| 705 | |
| 706 | void cmp(Register src1, const Operand& src2, Condition cond = al); |
| 707 | void cmp(Register src1, Register src2, Condition cond = al) { |
| 708 | cmp(src1, Operand(src2), cond); |
| 709 | } |
| 710 | |
| 711 | void cmn(Register src1, const Operand& src2, Condition cond = al); |
| 712 | |
| 713 | void orr(Register dst, Register src1, const Operand& src2, |
| 714 | SBit s = LeaveCC, Condition cond = al); |
| 715 | void orr(Register dst, Register src1, Register src2, |
| 716 | SBit s = LeaveCC, Condition cond = al) { |
| 717 | orr(dst, src1, Operand(src2), s, cond); |
| 718 | } |
| 719 | |
| 720 | void mov(Register dst, const Operand& src, |
| 721 | SBit s = LeaveCC, Condition cond = al); |
| 722 | void mov(Register dst, Register src, SBit s = LeaveCC, Condition cond = al) { |
| 723 | mov(dst, Operand(src), s, cond); |
| 724 | } |
| 725 | |
| 726 | void bic(Register dst, Register src1, const Operand& src2, |
| 727 | SBit s = LeaveCC, Condition cond = al); |
| 728 | |
| 729 | void mvn(Register dst, const Operand& src, |
| 730 | SBit s = LeaveCC, Condition cond = al); |
| 731 | |
| 732 | // Multiply instructions |
| 733 | |
| 734 | void mla(Register dst, Register src1, Register src2, Register srcA, |
| 735 | SBit s = LeaveCC, Condition cond = al); |
| 736 | |
| 737 | void mul(Register dst, Register src1, Register src2, |
| 738 | SBit s = LeaveCC, Condition cond = al); |
| 739 | |
| 740 | void smlal(Register dstL, Register dstH, Register src1, Register src2, |
| 741 | SBit s = LeaveCC, Condition cond = al); |
| 742 | |
| 743 | void smull(Register dstL, Register dstH, Register src1, Register src2, |
| 744 | SBit s = LeaveCC, Condition cond = al); |
| 745 | |
| 746 | void umlal(Register dstL, Register dstH, Register src1, Register src2, |
| 747 | SBit s = LeaveCC, Condition cond = al); |
| 748 | |
| 749 | void umull(Register dstL, Register dstH, Register src1, Register src2, |
| 750 | SBit s = LeaveCC, Condition cond = al); |
| 751 | |
| 752 | // Miscellaneous arithmetic instructions |
| 753 | |
| 754 | void clz(Register dst, Register src, Condition cond = al); // v5 and above |
| 755 | |
| 756 | // Status register access instructions |
| 757 | |
| 758 | void mrs(Register dst, SRegister s, Condition cond = al); |
| 759 | void msr(SRegisterFieldMask fields, const Operand& src, Condition cond = al); |
| 760 | |
| 761 | // Load/Store instructions |
| 762 | void ldr(Register dst, const MemOperand& src, Condition cond = al); |
| 763 | void str(Register src, const MemOperand& dst, Condition cond = al); |
| 764 | void ldrb(Register dst, const MemOperand& src, Condition cond = al); |
| 765 | void strb(Register src, const MemOperand& dst, Condition cond = al); |
| 766 | void ldrh(Register dst, const MemOperand& src, Condition cond = al); |
| 767 | void strh(Register src, const MemOperand& dst, Condition cond = al); |
| 768 | void ldrsb(Register dst, const MemOperand& src, Condition cond = al); |
| 769 | void ldrsh(Register dst, const MemOperand& src, Condition cond = al); |
Kristian Monsen | 25f6136 | 2010-05-21 11:50:48 +0100 | [diff] [blame^] | 770 | void ldrd(Register dst, const MemOperand& src, Condition cond = al); |
| 771 | void strd(Register src, const MemOperand& dst, Condition cond = al); |
Steve Block | a7e24c1 | 2009-10-30 11:49:00 +0000 | [diff] [blame] | 772 | |
| 773 | // Load/Store multiple instructions |
| 774 | void ldm(BlockAddrMode am, Register base, RegList dst, Condition cond = al); |
| 775 | void stm(BlockAddrMode am, Register base, RegList src, Condition cond = al); |
| 776 | |
| 777 | // Semaphore instructions |
| 778 | void swp(Register dst, Register src, Register base, Condition cond = al); |
| 779 | void swpb(Register dst, Register src, Register base, Condition cond = al); |
| 780 | |
| 781 | // Exception-generating instructions and debugging support |
| 782 | void stop(const char* msg); |
| 783 | |
| 784 | void bkpt(uint32_t imm16); // v5 and above |
| 785 | void swi(uint32_t imm24, Condition cond = al); |
| 786 | |
| 787 | // Coprocessor instructions |
| 788 | |
| 789 | void cdp(Coprocessor coproc, int opcode_1, |
| 790 | CRegister crd, CRegister crn, CRegister crm, |
| 791 | int opcode_2, Condition cond = al); |
| 792 | |
| 793 | void cdp2(Coprocessor coproc, int opcode_1, |
| 794 | CRegister crd, CRegister crn, CRegister crm, |
| 795 | int opcode_2); // v5 and above |
| 796 | |
| 797 | void mcr(Coprocessor coproc, int opcode_1, |
| 798 | Register rd, CRegister crn, CRegister crm, |
| 799 | int opcode_2 = 0, Condition cond = al); |
| 800 | |
| 801 | void mcr2(Coprocessor coproc, int opcode_1, |
| 802 | Register rd, CRegister crn, CRegister crm, |
| 803 | int opcode_2 = 0); // v5 and above |
| 804 | |
| 805 | void mrc(Coprocessor coproc, int opcode_1, |
| 806 | Register rd, CRegister crn, CRegister crm, |
| 807 | int opcode_2 = 0, Condition cond = al); |
| 808 | |
| 809 | void mrc2(Coprocessor coproc, int opcode_1, |
| 810 | Register rd, CRegister crn, CRegister crm, |
| 811 | int opcode_2 = 0); // v5 and above |
| 812 | |
| 813 | void ldc(Coprocessor coproc, CRegister crd, const MemOperand& src, |
| 814 | LFlag l = Short, Condition cond = al); |
| 815 | void ldc(Coprocessor coproc, CRegister crd, Register base, int option, |
| 816 | LFlag l = Short, Condition cond = al); |
| 817 | |
| 818 | void ldc2(Coprocessor coproc, CRegister crd, const MemOperand& src, |
| 819 | LFlag l = Short); // v5 and above |
| 820 | void ldc2(Coprocessor coproc, CRegister crd, Register base, int option, |
| 821 | LFlag l = Short); // v5 and above |
| 822 | |
| 823 | void stc(Coprocessor coproc, CRegister crd, const MemOperand& dst, |
| 824 | LFlag l = Short, Condition cond = al); |
| 825 | void stc(Coprocessor coproc, CRegister crd, Register base, int option, |
| 826 | LFlag l = Short, Condition cond = al); |
| 827 | |
| 828 | void stc2(Coprocessor coproc, CRegister crd, const MemOperand& dst, |
| 829 | LFlag l = Short); // v5 and above |
| 830 | void stc2(Coprocessor coproc, CRegister crd, Register base, int option, |
| 831 | LFlag l = Short); // v5 and above |
| 832 | |
Steve Block | d0582a6 | 2009-12-15 09:54:21 +0000 | [diff] [blame] | 833 | // Support for VFP. |
| 834 | // All these APIs support S0 to S31 and D0 to D15. |
| 835 | // Currently these APIs do not support extended D registers, i.e, D16 to D31. |
| 836 | // However, some simple modifications can allow |
| 837 | // these APIs to support D16 to D31. |
| 838 | |
Leon Clarke | d91b9f7 | 2010-01-27 17:25:45 +0000 | [diff] [blame] | 839 | void vldr(const DwVfpRegister dst, |
| 840 | const Register base, |
| 841 | int offset, // Offset must be a multiple of 4. |
| 842 | const Condition cond = al); |
Steve Block | 6ded16b | 2010-05-10 14:33:55 +0100 | [diff] [blame] | 843 | |
| 844 | void vldr(const SwVfpRegister dst, |
| 845 | const Register base, |
| 846 | int offset, // Offset must be a multiple of 4. |
| 847 | const Condition cond = al); |
| 848 | |
Leon Clarke | d91b9f7 | 2010-01-27 17:25:45 +0000 | [diff] [blame] | 849 | void vstr(const DwVfpRegister src, |
| 850 | const Register base, |
| 851 | int offset, // Offset must be a multiple of 4. |
| 852 | const Condition cond = al); |
Leon Clarke | e46be81 | 2010-01-19 14:06:41 +0000 | [diff] [blame] | 853 | void vmov(const DwVfpRegister dst, |
| 854 | const Register src1, |
Steve Block | d0582a6 | 2009-12-15 09:54:21 +0000 | [diff] [blame] | 855 | const Register src2, |
Leon Clarke | e46be81 | 2010-01-19 14:06:41 +0000 | [diff] [blame] | 856 | const Condition cond = al); |
| 857 | void vmov(const Register dst1, |
| 858 | const Register dst2, |
| 859 | const DwVfpRegister src, |
| 860 | const Condition cond = al); |
| 861 | void vmov(const SwVfpRegister dst, |
| 862 | const Register src, |
| 863 | const Condition cond = al); |
| 864 | void vmov(const Register dst, |
| 865 | const SwVfpRegister src, |
| 866 | const Condition cond = al); |
Steve Block | 6ded16b | 2010-05-10 14:33:55 +0100 | [diff] [blame] | 867 | void vcvt_f64_s32(const DwVfpRegister dst, |
| 868 | const SwVfpRegister src, |
| 869 | const Condition cond = al); |
| 870 | void vcvt_f32_s32(const SwVfpRegister dst, |
| 871 | const SwVfpRegister src, |
| 872 | const Condition cond = al); |
| 873 | void vcvt_f64_u32(const DwVfpRegister dst, |
| 874 | const SwVfpRegister src, |
| 875 | const Condition cond = al); |
| 876 | void vcvt_s32_f64(const SwVfpRegister dst, |
| 877 | const DwVfpRegister src, |
| 878 | const Condition cond = al); |
| 879 | void vcvt_u32_f64(const SwVfpRegister dst, |
| 880 | const DwVfpRegister src, |
| 881 | const Condition cond = al); |
| 882 | void vcvt_f64_f32(const DwVfpRegister dst, |
| 883 | const SwVfpRegister src, |
| 884 | const Condition cond = al); |
| 885 | void vcvt_f32_f64(const SwVfpRegister dst, |
| 886 | const DwVfpRegister src, |
| 887 | const Condition cond = al); |
Leon Clarke | e46be81 | 2010-01-19 14:06:41 +0000 | [diff] [blame] | 888 | |
| 889 | void vadd(const DwVfpRegister dst, |
| 890 | const DwVfpRegister src1, |
| 891 | const DwVfpRegister src2, |
| 892 | const Condition cond = al); |
| 893 | void vsub(const DwVfpRegister dst, |
| 894 | const DwVfpRegister src1, |
| 895 | const DwVfpRegister src2, |
| 896 | const Condition cond = al); |
| 897 | void vmul(const DwVfpRegister dst, |
| 898 | const DwVfpRegister src1, |
| 899 | const DwVfpRegister src2, |
| 900 | const Condition cond = al); |
| 901 | void vdiv(const DwVfpRegister dst, |
| 902 | const DwVfpRegister src1, |
| 903 | const DwVfpRegister src2, |
| 904 | const Condition cond = al); |
| 905 | void vcmp(const DwVfpRegister src1, |
| 906 | const DwVfpRegister src2, |
Steve Block | d0582a6 | 2009-12-15 09:54:21 +0000 | [diff] [blame] | 907 | const SBit s = LeaveCC, |
| 908 | const Condition cond = al); |
| 909 | void vmrs(const Register dst, |
| 910 | const Condition cond = al); |
| 911 | |
Steve Block | a7e24c1 | 2009-10-30 11:49:00 +0000 | [diff] [blame] | 912 | // Pseudo instructions |
Steve Block | 6ded16b | 2010-05-10 14:33:55 +0100 | [diff] [blame] | 913 | void nop(int type = 0); |
Steve Block | a7e24c1 | 2009-10-30 11:49:00 +0000 | [diff] [blame] | 914 | |
| 915 | void push(Register src, Condition cond = al) { |
| 916 | str(src, MemOperand(sp, 4, NegPreIndex), cond); |
| 917 | } |
| 918 | |
| 919 | void pop(Register dst, Condition cond = al) { |
| 920 | ldr(dst, MemOperand(sp, 4, PostIndex), cond); |
| 921 | } |
| 922 | |
| 923 | void pop() { |
| 924 | add(sp, sp, Operand(kPointerSize)); |
| 925 | } |
| 926 | |
| 927 | // Load effective address of memory operand x into register dst |
| 928 | void lea(Register dst, const MemOperand& x, |
| 929 | SBit s = LeaveCC, Condition cond = al); |
| 930 | |
| 931 | // Jump unconditionally to given label. |
| 932 | void jmp(Label* L) { b(L, al); } |
| 933 | |
| 934 | // Check the code size generated from label to here. |
| 935 | int InstructionsGeneratedSince(Label* l) { |
| 936 | return (pc_offset() - l->pos()) / kInstrSize; |
| 937 | } |
| 938 | |
Steve Block | d0582a6 | 2009-12-15 09:54:21 +0000 | [diff] [blame] | 939 | // Check whether an immediate fits an addressing mode 1 instruction. |
| 940 | bool ImmediateFitsAddrMode1Instruction(int32_t imm32); |
| 941 | |
Steve Block | 6ded16b | 2010-05-10 14:33:55 +0100 | [diff] [blame] | 942 | // Class for scoping postponing the constant pool generation. |
| 943 | class BlockConstPoolScope { |
| 944 | public: |
| 945 | explicit BlockConstPoolScope(Assembler* assem) : assem_(assem) { |
| 946 | assem_->StartBlockConstPool(); |
| 947 | } |
| 948 | ~BlockConstPoolScope() { |
| 949 | assem_->EndBlockConstPool(); |
| 950 | } |
| 951 | |
| 952 | private: |
| 953 | Assembler* assem_; |
| 954 | |
| 955 | DISALLOW_IMPLICIT_CONSTRUCTORS(BlockConstPoolScope); |
| 956 | }; |
| 957 | |
Steve Block | d0582a6 | 2009-12-15 09:54:21 +0000 | [diff] [blame] | 958 | // Postpone the generation of the constant pool for the specified number of |
| 959 | // instructions. |
| 960 | void BlockConstPoolFor(int instructions); |
| 961 | |
Steve Block | a7e24c1 | 2009-10-30 11:49:00 +0000 | [diff] [blame] | 962 | // Debugging |
| 963 | |
| 964 | // Mark address of the ExitJSFrame code. |
| 965 | void RecordJSReturn(); |
| 966 | |
| 967 | // Record a comment relocation entry that can be used by a disassembler. |
| 968 | // Use --debug_code to enable. |
| 969 | void RecordComment(const char* msg); |
| 970 | |
| 971 | void RecordPosition(int pos); |
| 972 | void RecordStatementPosition(int pos); |
| 973 | void WriteRecordedPositions(); |
| 974 | |
| 975 | int pc_offset() const { return pc_ - buffer_; } |
| 976 | int current_position() const { return current_position_; } |
Steve Block | 6ded16b | 2010-05-10 14:33:55 +0100 | [diff] [blame] | 977 | int current_statement_position() const { return current_statement_position_; } |
| 978 | |
| 979 | // Read/patch instructions |
| 980 | static Instr instr_at(byte* pc) { return *reinterpret_cast<Instr*>(pc); } |
| 981 | static void instr_at_put(byte* pc, Instr instr) { |
| 982 | *reinterpret_cast<Instr*>(pc) = instr; |
| 983 | } |
| 984 | static bool IsNop(Instr instr, int type = 0); |
| 985 | static bool IsBranch(Instr instr); |
| 986 | static int GetBranchOffset(Instr instr); |
| 987 | static bool IsLdrRegisterImmediate(Instr instr); |
| 988 | static int GetLdrRegisterImmediateOffset(Instr instr); |
| 989 | static Instr SetLdrRegisterImmediateOffset(Instr instr, int offset); |
| 990 | |
Steve Block | a7e24c1 | 2009-10-30 11:49:00 +0000 | [diff] [blame] | 991 | |
| 992 | protected: |
| 993 | int buffer_space() const { return reloc_info_writer.pos() - pc_; } |
| 994 | |
| 995 | // Read/patch instructions |
Steve Block | a7e24c1 | 2009-10-30 11:49:00 +0000 | [diff] [blame] | 996 | Instr instr_at(int pos) { return *reinterpret_cast<Instr*>(buffer_ + pos); } |
| 997 | void instr_at_put(int pos, Instr instr) { |
| 998 | *reinterpret_cast<Instr*>(buffer_ + pos) = instr; |
| 999 | } |
| 1000 | |
| 1001 | // Decode branch instruction at pos and return branch target pos |
| 1002 | int target_at(int pos); |
| 1003 | |
| 1004 | // Patch branch instruction at pos to branch to given branch target pos |
| 1005 | void target_at_put(int pos, int target_pos); |
| 1006 | |
| 1007 | // Check if is time to emit a constant pool for pending reloc info entries |
| 1008 | void CheckConstPool(bool force_emit, bool require_jump); |
| 1009 | |
| 1010 | // Block the emission of the constant pool before pc_offset |
| 1011 | void BlockConstPoolBefore(int pc_offset) { |
| 1012 | if (no_const_pool_before_ < pc_offset) no_const_pool_before_ = pc_offset; |
| 1013 | } |
| 1014 | |
Steve Block | 6ded16b | 2010-05-10 14:33:55 +0100 | [diff] [blame] | 1015 | void StartBlockConstPool() { |
| 1016 | const_pool_blocked_nesting_++; |
| 1017 | } |
| 1018 | void EndBlockConstPool() { |
| 1019 | const_pool_blocked_nesting_--; |
| 1020 | } |
| 1021 | |
Steve Block | a7e24c1 | 2009-10-30 11:49:00 +0000 | [diff] [blame] | 1022 | private: |
| 1023 | // Code buffer: |
| 1024 | // The buffer into which code and relocation info are generated. |
| 1025 | byte* buffer_; |
| 1026 | int buffer_size_; |
| 1027 | // True if the assembler owns the buffer, false if buffer is external. |
| 1028 | bool own_buffer_; |
| 1029 | |
| 1030 | // Buffer size and constant pool distance are checked together at regular |
| 1031 | // intervals of kBufferCheckInterval emitted bytes |
| 1032 | static const int kBufferCheckInterval = 1*KB/2; |
| 1033 | int next_buffer_check_; // pc offset of next buffer check |
| 1034 | |
| 1035 | // Code generation |
| 1036 | // The relocation writer's position is at least kGap bytes below the end of |
| 1037 | // the generated instructions. This is so that multi-instruction sequences do |
| 1038 | // not have to check for overflow. The same is true for writes of large |
| 1039 | // relocation info entries. |
| 1040 | static const int kGap = 32; |
| 1041 | byte* pc_; // the program counter; moves forward |
| 1042 | |
| 1043 | // Constant pool generation |
| 1044 | // Pools are emitted in the instruction stream, preferably after unconditional |
| 1045 | // jumps or after returns from functions (in dead code locations). |
| 1046 | // If a long code sequence does not contain unconditional jumps, it is |
| 1047 | // necessary to emit the constant pool before the pool gets too far from the |
| 1048 | // location it is accessed from. In this case, we emit a jump over the emitted |
| 1049 | // constant pool. |
| 1050 | // Constants in the pool may be addresses of functions that gets relocated; |
| 1051 | // if so, a relocation info entry is associated to the constant pool entry. |
| 1052 | |
| 1053 | // Repeated checking whether the constant pool should be emitted is rather |
| 1054 | // expensive. By default we only check again once a number of instructions |
| 1055 | // has been generated. That also means that the sizing of the buffers is not |
| 1056 | // an exact science, and that we rely on some slop to not overrun buffers. |
| 1057 | static const int kCheckConstIntervalInst = 32; |
| 1058 | static const int kCheckConstInterval = kCheckConstIntervalInst * kInstrSize; |
| 1059 | |
| 1060 | |
| 1061 | // Pools are emitted after function return and in dead code at (more or less) |
| 1062 | // regular intervals of kDistBetweenPools bytes |
| 1063 | static const int kDistBetweenPools = 1*KB; |
| 1064 | |
| 1065 | // Constants in pools are accessed via pc relative addressing, which can |
| 1066 | // reach +/-4KB thereby defining a maximum distance between the instruction |
| 1067 | // and the accessed constant. We satisfy this constraint by limiting the |
| 1068 | // distance between pools. |
| 1069 | static const int kMaxDistBetweenPools = 4*KB - 2*kBufferCheckInterval; |
| 1070 | |
Steve Block | 6ded16b | 2010-05-10 14:33:55 +0100 | [diff] [blame] | 1071 | // Emission of the constant pool may be blocked in some code sequences. |
| 1072 | int const_pool_blocked_nesting_; // Block emission if this is not zero. |
| 1073 | int no_const_pool_before_; // Block emission before this pc offset. |
Steve Block | a7e24c1 | 2009-10-30 11:49:00 +0000 | [diff] [blame] | 1074 | |
| 1075 | // Keep track of the last emitted pool to guarantee a maximal distance |
| 1076 | int last_const_pool_end_; // pc offset following the last constant pool |
| 1077 | |
| 1078 | // Relocation info generation |
| 1079 | // Each relocation is encoded as a variable size value |
| 1080 | static const int kMaxRelocSize = RelocInfoWriter::kMaxSize; |
| 1081 | RelocInfoWriter reloc_info_writer; |
| 1082 | // Relocation info records are also used during code generation as temporary |
| 1083 | // containers for constants and code target addresses until they are emitted |
| 1084 | // to the constant pool. These pending relocation info records are temporarily |
| 1085 | // stored in a separate buffer until a constant pool is emitted. |
| 1086 | // If every instruction in a long sequence is accessing the pool, we need one |
| 1087 | // pending relocation entry per instruction. |
| 1088 | static const int kMaxNumPRInfo = kMaxDistBetweenPools/kInstrSize; |
| 1089 | RelocInfo prinfo_[kMaxNumPRInfo]; // the buffer of pending relocation info |
| 1090 | int num_prinfo_; // number of pending reloc info entries in the buffer |
| 1091 | |
| 1092 | // The bound position, before this we cannot do instruction elimination. |
| 1093 | int last_bound_pos_; |
| 1094 | |
| 1095 | // source position information |
| 1096 | int current_position_; |
| 1097 | int current_statement_position_; |
| 1098 | int written_position_; |
| 1099 | int written_statement_position_; |
| 1100 | |
| 1101 | // Code emission |
| 1102 | inline void CheckBuffer(); |
| 1103 | void GrowBuffer(); |
| 1104 | inline void emit(Instr x); |
| 1105 | |
| 1106 | // Instruction generation |
| 1107 | void addrmod1(Instr instr, Register rn, Register rd, const Operand& x); |
| 1108 | void addrmod2(Instr instr, Register rd, const MemOperand& x); |
| 1109 | void addrmod3(Instr instr, Register rd, const MemOperand& x); |
| 1110 | void addrmod4(Instr instr, Register rn, RegList rl); |
| 1111 | void addrmod5(Instr instr, CRegister crd, const MemOperand& x); |
| 1112 | |
| 1113 | // Labels |
| 1114 | void print(Label* L); |
| 1115 | void bind_to(Label* L, int pos); |
| 1116 | void link_to(Label* L, Label* appendix); |
| 1117 | void next(Label* L); |
| 1118 | |
| 1119 | // Record reloc info for current pc_ |
| 1120 | void RecordRelocInfo(RelocInfo::Mode rmode, intptr_t data = 0); |
| 1121 | |
| 1122 | friend class RegExpMacroAssemblerARM; |
| 1123 | friend class RelocInfo; |
| 1124 | friend class CodePatcher; |
Steve Block | 6ded16b | 2010-05-10 14:33:55 +0100 | [diff] [blame] | 1125 | friend class BlockConstPoolScope; |
Steve Block | a7e24c1 | 2009-10-30 11:49:00 +0000 | [diff] [blame] | 1126 | }; |
| 1127 | |
| 1128 | } } // namespace v8::internal |
| 1129 | |
| 1130 | #endif // V8_ARM_ASSEMBLER_ARM_H_ |