Leon Clarke | d91b9f7 | 2010-01-27 17:25:45 +0000 | [diff] [blame] | 1 | // Copyright 2010 the V8 project authors. All rights reserved. |
Steve Block | a7e24c1 | 2009-10-30 11:49:00 +0000 | [diff] [blame] | 2 | // Redistribution and use in source and binary forms, with or without |
| 3 | // modification, are permitted provided that the following conditions are |
| 4 | // met: |
| 5 | // |
| 6 | // * Redistributions of source code must retain the above copyright |
| 7 | // notice, this list of conditions and the following disclaimer. |
| 8 | // * Redistributions in binary form must reproduce the above |
| 9 | // copyright notice, this list of conditions and the following |
| 10 | // disclaimer in the documentation and/or other materials provided |
| 11 | // with the distribution. |
| 12 | // * Neither the name of Google Inc. nor the names of its |
| 13 | // contributors may be used to endorse or promote products derived |
| 14 | // from this software without specific prior written permission. |
| 15 | // |
| 16 | // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS |
| 17 | // "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT |
| 18 | // LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR |
| 19 | // A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT |
| 20 | // OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, |
| 21 | // SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT |
| 22 | // LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
| 23 | // DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
| 24 | // THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
| 25 | // (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE |
| 26 | // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
| 27 | |
| 28 | // A Disassembler object is used to disassemble a block of code instruction by |
| 29 | // instruction. The default implementation of the NameConverter object can be |
| 30 | // overriden to modify register names or to do symbol lookup on addresses. |
| 31 | // |
| 32 | // The example below will disassemble a block of code and print it to stdout. |
| 33 | // |
| 34 | // NameConverter converter; |
| 35 | // Disassembler d(converter); |
| 36 | // for (byte* pc = begin; pc < end;) { |
Steve Block | 6ded16b | 2010-05-10 14:33:55 +0100 | [diff] [blame] | 37 | // v8::internal::EmbeddedVector<char, 256> buffer; |
Steve Block | a7e24c1 | 2009-10-30 11:49:00 +0000 | [diff] [blame] | 38 | // byte* prev_pc = pc; |
Steve Block | 6ded16b | 2010-05-10 14:33:55 +0100 | [diff] [blame] | 39 | // pc += d.InstructionDecode(buffer, pc); |
Steve Block | a7e24c1 | 2009-10-30 11:49:00 +0000 | [diff] [blame] | 40 | // printf("%p %08x %s\n", |
| 41 | // prev_pc, *reinterpret_cast<int32_t*>(prev_pc), buffer); |
| 42 | // } |
| 43 | // |
| 44 | // The Disassembler class also has a convenience method to disassemble a block |
| 45 | // of code into a FILE*, meaning that the above functionality could also be |
| 46 | // achieved by just calling Disassembler::Disassemble(stdout, begin, end); |
| 47 | |
| 48 | |
| 49 | #include <assert.h> |
| 50 | #include <stdio.h> |
| 51 | #include <stdarg.h> |
| 52 | #include <string.h> |
| 53 | #ifndef WIN32 |
| 54 | #include <stdint.h> |
| 55 | #endif |
| 56 | |
| 57 | #include "v8.h" |
| 58 | |
Leon Clarke | f7060e2 | 2010-06-03 12:02:55 +0100 | [diff] [blame] | 59 | #if defined(V8_TARGET_ARCH_ARM) |
| 60 | |
Steve Block | a7e24c1 | 2009-10-30 11:49:00 +0000 | [diff] [blame] | 61 | #include "constants-arm.h" |
| 62 | #include "disasm.h" |
| 63 | #include "macro-assembler.h" |
| 64 | #include "platform.h" |
| 65 | |
| 66 | |
| 67 | namespace assembler { |
| 68 | namespace arm { |
| 69 | |
| 70 | namespace v8i = v8::internal; |
| 71 | |
| 72 | |
| 73 | //------------------------------------------------------------------------------ |
| 74 | |
| 75 | // Decoder decodes and disassembles instructions into an output buffer. |
| 76 | // It uses the converter to convert register names and call destinations into |
| 77 | // more informative description. |
| 78 | class Decoder { |
| 79 | public: |
| 80 | Decoder(const disasm::NameConverter& converter, |
| 81 | v8::internal::Vector<char> out_buffer) |
| 82 | : converter_(converter), |
| 83 | out_buffer_(out_buffer), |
| 84 | out_buffer_pos_(0) { |
| 85 | out_buffer_[out_buffer_pos_] = '\0'; |
| 86 | } |
| 87 | |
| 88 | ~Decoder() {} |
| 89 | |
| 90 | // Writes one disassembled instruction into 'buffer' (0-terminated). |
| 91 | // Returns the length of the disassembled machine instruction in bytes. |
| 92 | int InstructionDecode(byte* instruction); |
| 93 | |
| 94 | private: |
| 95 | // Bottleneck functions to print into the out_buffer. |
| 96 | void PrintChar(const char ch); |
| 97 | void Print(const char* str); |
| 98 | |
| 99 | // Printing of common values. |
| 100 | void PrintRegister(int reg); |
Steve Block | d0582a6 | 2009-12-15 09:54:21 +0000 | [diff] [blame] | 101 | void PrintSRegister(int reg); |
| 102 | void PrintDRegister(int reg); |
| 103 | int FormatVFPRegister(Instr* instr, const char* format); |
Kristian Monsen | 9dcf7e2 | 2010-06-28 14:14:28 +0100 | [diff] [blame] | 104 | void PrintMovwMovt(Instr* instr); |
Steve Block | d0582a6 | 2009-12-15 09:54:21 +0000 | [diff] [blame] | 105 | int FormatVFPinstruction(Instr* instr, const char* format); |
Steve Block | a7e24c1 | 2009-10-30 11:49:00 +0000 | [diff] [blame] | 106 | void PrintCondition(Instr* instr); |
| 107 | void PrintShiftRm(Instr* instr); |
| 108 | void PrintShiftImm(Instr* instr); |
| 109 | void PrintPU(Instr* instr); |
| 110 | void PrintSoftwareInterrupt(SoftwareInterruptCodes swi); |
| 111 | |
| 112 | // Handle formatting of instructions and their options. |
| 113 | int FormatRegister(Instr* instr, const char* option); |
| 114 | int FormatOption(Instr* instr, const char* option); |
| 115 | void Format(Instr* instr, const char* format); |
| 116 | void Unknown(Instr* instr); |
| 117 | |
| 118 | // Each of these functions decodes one particular instruction type, a 3-bit |
| 119 | // field in the instruction encoding. |
| 120 | // Types 0 and 1 are combined as they are largely the same except for the way |
| 121 | // they interpret the shifter operand. |
| 122 | void DecodeType01(Instr* instr); |
| 123 | void DecodeType2(Instr* instr); |
| 124 | void DecodeType3(Instr* instr); |
| 125 | void DecodeType4(Instr* instr); |
| 126 | void DecodeType5(Instr* instr); |
| 127 | void DecodeType6(Instr* instr); |
| 128 | void DecodeType7(Instr* instr); |
| 129 | void DecodeUnconditional(Instr* instr); |
Steve Block | d0582a6 | 2009-12-15 09:54:21 +0000 | [diff] [blame] | 130 | // For VFP support. |
| 131 | void DecodeTypeVFP(Instr* instr); |
| 132 | void DecodeType6CoprocessorIns(Instr* instr); |
| 133 | |
Steve Block | 6ded16b | 2010-05-10 14:33:55 +0100 | [diff] [blame] | 134 | void DecodeVMOVBetweenCoreAndSinglePrecisionRegisters(Instr* instr); |
| 135 | void DecodeVCMP(Instr* instr); |
| 136 | void DecodeVCVTBetweenDoubleAndSingle(Instr* instr); |
| 137 | void DecodeVCVTBetweenFloatingPointAndInteger(Instr* instr); |
Steve Block | a7e24c1 | 2009-10-30 11:49:00 +0000 | [diff] [blame] | 138 | |
| 139 | const disasm::NameConverter& converter_; |
| 140 | v8::internal::Vector<char> out_buffer_; |
| 141 | int out_buffer_pos_; |
| 142 | |
| 143 | DISALLOW_COPY_AND_ASSIGN(Decoder); |
| 144 | }; |
| 145 | |
| 146 | |
| 147 | // Support for assertions in the Decoder formatting functions. |
| 148 | #define STRING_STARTS_WITH(string, compare_string) \ |
| 149 | (strncmp(string, compare_string, strlen(compare_string)) == 0) |
| 150 | |
| 151 | |
| 152 | // Append the ch to the output buffer. |
| 153 | void Decoder::PrintChar(const char ch) { |
| 154 | out_buffer_[out_buffer_pos_++] = ch; |
| 155 | } |
| 156 | |
| 157 | |
| 158 | // Append the str to the output buffer. |
| 159 | void Decoder::Print(const char* str) { |
| 160 | char cur = *str++; |
| 161 | while (cur != '\0' && (out_buffer_pos_ < (out_buffer_.length() - 1))) { |
| 162 | PrintChar(cur); |
| 163 | cur = *str++; |
| 164 | } |
| 165 | out_buffer_[out_buffer_pos_] = 0; |
| 166 | } |
| 167 | |
| 168 | |
| 169 | // These condition names are defined in a way to match the native disassembler |
| 170 | // formatting. See for example the command "objdump -d <binary file>". |
| 171 | static const char* cond_names[max_condition] = { |
| 172 | "eq", "ne", "cs" , "cc" , "mi" , "pl" , "vs" , "vc" , |
| 173 | "hi", "ls", "ge", "lt", "gt", "le", "", "invalid", |
| 174 | }; |
| 175 | |
| 176 | |
| 177 | // Print the condition guarding the instruction. |
| 178 | void Decoder::PrintCondition(Instr* instr) { |
| 179 | Print(cond_names[instr->ConditionField()]); |
| 180 | } |
| 181 | |
| 182 | |
| 183 | // Print the register name according to the active name converter. |
| 184 | void Decoder::PrintRegister(int reg) { |
| 185 | Print(converter_.NameOfCPURegister(reg)); |
| 186 | } |
| 187 | |
Steve Block | d0582a6 | 2009-12-15 09:54:21 +0000 | [diff] [blame] | 188 | // Print the VFP S register name according to the active name converter. |
| 189 | void Decoder::PrintSRegister(int reg) { |
Steve Block | 6ded16b | 2010-05-10 14:33:55 +0100 | [diff] [blame] | 190 | Print(assembler::arm::VFPRegisters::Name(reg, false)); |
Steve Block | d0582a6 | 2009-12-15 09:54:21 +0000 | [diff] [blame] | 191 | } |
| 192 | |
| 193 | // Print the VFP D register name according to the active name converter. |
| 194 | void Decoder::PrintDRegister(int reg) { |
Steve Block | 6ded16b | 2010-05-10 14:33:55 +0100 | [diff] [blame] | 195 | Print(assembler::arm::VFPRegisters::Name(reg, true)); |
Steve Block | d0582a6 | 2009-12-15 09:54:21 +0000 | [diff] [blame] | 196 | } |
| 197 | |
Steve Block | a7e24c1 | 2009-10-30 11:49:00 +0000 | [diff] [blame] | 198 | |
| 199 | // These shift names are defined in a way to match the native disassembler |
| 200 | // formatting. See for example the command "objdump -d <binary file>". |
| 201 | static const char* shift_names[max_shift] = { |
| 202 | "lsl", "lsr", "asr", "ror" |
| 203 | }; |
| 204 | |
| 205 | |
| 206 | // Print the register shift operands for the instruction. Generally used for |
| 207 | // data processing instructions. |
| 208 | void Decoder::PrintShiftRm(Instr* instr) { |
| 209 | Shift shift = instr->ShiftField(); |
| 210 | int shift_amount = instr->ShiftAmountField(); |
| 211 | int rm = instr->RmField(); |
| 212 | |
| 213 | PrintRegister(rm); |
| 214 | |
| 215 | if ((instr->RegShiftField() == 0) && (shift == LSL) && (shift_amount == 0)) { |
| 216 | // Special case for using rm only. |
| 217 | return; |
| 218 | } |
| 219 | if (instr->RegShiftField() == 0) { |
| 220 | // by immediate |
| 221 | if ((shift == ROR) && (shift_amount == 0)) { |
| 222 | Print(", RRX"); |
| 223 | return; |
| 224 | } else if (((shift == LSR) || (shift == ASR)) && (shift_amount == 0)) { |
| 225 | shift_amount = 32; |
| 226 | } |
| 227 | out_buffer_pos_ += v8i::OS::SNPrintF(out_buffer_ + out_buffer_pos_, |
| 228 | ", %s #%d", |
| 229 | shift_names[shift], shift_amount); |
| 230 | } else { |
| 231 | // by register |
| 232 | int rs = instr->RsField(); |
| 233 | out_buffer_pos_ += v8i::OS::SNPrintF(out_buffer_ + out_buffer_pos_, |
| 234 | ", %s ", shift_names[shift]); |
| 235 | PrintRegister(rs); |
| 236 | } |
| 237 | } |
| 238 | |
| 239 | |
| 240 | // Print the immediate operand for the instruction. Generally used for data |
| 241 | // processing instructions. |
| 242 | void Decoder::PrintShiftImm(Instr* instr) { |
| 243 | int rotate = instr->RotateField() * 2; |
| 244 | int immed8 = instr->Immed8Field(); |
| 245 | int imm = (immed8 >> rotate) | (immed8 << (32 - rotate)); |
| 246 | out_buffer_pos_ += v8i::OS::SNPrintF(out_buffer_ + out_buffer_pos_, |
| 247 | "#%d", imm); |
| 248 | } |
| 249 | |
| 250 | |
| 251 | // Print PU formatting to reduce complexity of FormatOption. |
| 252 | void Decoder::PrintPU(Instr* instr) { |
| 253 | switch (instr->PUField()) { |
| 254 | case 0: { |
| 255 | Print("da"); |
| 256 | break; |
| 257 | } |
| 258 | case 1: { |
| 259 | Print("ia"); |
| 260 | break; |
| 261 | } |
| 262 | case 2: { |
| 263 | Print("db"); |
| 264 | break; |
| 265 | } |
| 266 | case 3: { |
| 267 | Print("ib"); |
| 268 | break; |
| 269 | } |
| 270 | default: { |
| 271 | UNREACHABLE(); |
| 272 | break; |
| 273 | } |
| 274 | } |
| 275 | } |
| 276 | |
| 277 | |
| 278 | // Print SoftwareInterrupt codes. Factoring this out reduces the complexity of |
| 279 | // the FormatOption method. |
| 280 | void Decoder::PrintSoftwareInterrupt(SoftwareInterruptCodes swi) { |
| 281 | switch (swi) { |
| 282 | case call_rt_redirected: |
| 283 | Print("call_rt_redirected"); |
| 284 | return; |
| 285 | case break_point: |
| 286 | Print("break_point"); |
| 287 | return; |
| 288 | default: |
| 289 | out_buffer_pos_ += v8i::OS::SNPrintF(out_buffer_ + out_buffer_pos_, |
| 290 | "%d", |
| 291 | swi); |
| 292 | return; |
| 293 | } |
| 294 | } |
| 295 | |
| 296 | |
| 297 | // Handle all register based formatting in this function to reduce the |
| 298 | // complexity of FormatOption. |
| 299 | int Decoder::FormatRegister(Instr* instr, const char* format) { |
| 300 | ASSERT(format[0] == 'r'); |
| 301 | if (format[1] == 'n') { // 'rn: Rn register |
| 302 | int reg = instr->RnField(); |
| 303 | PrintRegister(reg); |
| 304 | return 2; |
| 305 | } else if (format[1] == 'd') { // 'rd: Rd register |
| 306 | int reg = instr->RdField(); |
| 307 | PrintRegister(reg); |
| 308 | return 2; |
| 309 | } else if (format[1] == 's') { // 'rs: Rs register |
| 310 | int reg = instr->RsField(); |
| 311 | PrintRegister(reg); |
| 312 | return 2; |
| 313 | } else if (format[1] == 'm') { // 'rm: Rm register |
| 314 | int reg = instr->RmField(); |
| 315 | PrintRegister(reg); |
| 316 | return 2; |
Steve Block | d0582a6 | 2009-12-15 09:54:21 +0000 | [diff] [blame] | 317 | } else if (format[1] == 't') { // 'rt: Rt register |
| 318 | int reg = instr->RtField(); |
| 319 | PrintRegister(reg); |
| 320 | return 2; |
Steve Block | a7e24c1 | 2009-10-30 11:49:00 +0000 | [diff] [blame] | 321 | } else if (format[1] == 'l') { |
| 322 | // 'rlist: register list for load and store multiple instructions |
| 323 | ASSERT(STRING_STARTS_WITH(format, "rlist")); |
| 324 | int rlist = instr->RlistField(); |
| 325 | int reg = 0; |
| 326 | Print("{"); |
| 327 | // Print register list in ascending order, by scanning the bit mask. |
| 328 | while (rlist != 0) { |
| 329 | if ((rlist & 1) != 0) { |
| 330 | PrintRegister(reg); |
| 331 | if ((rlist >> 1) != 0) { |
| 332 | Print(", "); |
| 333 | } |
| 334 | } |
| 335 | reg++; |
| 336 | rlist >>= 1; |
| 337 | } |
| 338 | Print("}"); |
| 339 | return 5; |
| 340 | } |
| 341 | UNREACHABLE(); |
| 342 | return -1; |
| 343 | } |
| 344 | |
| 345 | |
Steve Block | d0582a6 | 2009-12-15 09:54:21 +0000 | [diff] [blame] | 346 | // Handle all VFP register based formatting in this function to reduce the |
| 347 | // complexity of FormatOption. |
| 348 | int Decoder::FormatVFPRegister(Instr* instr, const char* format) { |
| 349 | ASSERT((format[0] == 'S') || (format[0] == 'D')); |
| 350 | |
| 351 | if (format[1] == 'n') { |
| 352 | int reg = instr->VnField(); |
| 353 | if (format[0] == 'S') PrintSRegister(((reg << 1) | instr->NField())); |
| 354 | if (format[0] == 'D') PrintDRegister(reg); |
| 355 | return 2; |
| 356 | } else if (format[1] == 'm') { |
| 357 | int reg = instr->VmField(); |
| 358 | if (format[0] == 'S') PrintSRegister(((reg << 1) | instr->MField())); |
| 359 | if (format[0] == 'D') PrintDRegister(reg); |
| 360 | return 2; |
| 361 | } else if (format[1] == 'd') { |
| 362 | int reg = instr->VdField(); |
| 363 | if (format[0] == 'S') PrintSRegister(((reg << 1) | instr->DField())); |
| 364 | if (format[0] == 'D') PrintDRegister(reg); |
| 365 | return 2; |
| 366 | } |
| 367 | |
| 368 | UNREACHABLE(); |
| 369 | return -1; |
| 370 | } |
| 371 | |
| 372 | |
| 373 | int Decoder::FormatVFPinstruction(Instr* instr, const char* format) { |
| 374 | Print(format); |
| 375 | return 0; |
| 376 | } |
| 377 | |
| 378 | |
Kristian Monsen | 9dcf7e2 | 2010-06-28 14:14:28 +0100 | [diff] [blame] | 379 | // Print the movw or movt instruction. |
| 380 | void Decoder::PrintMovwMovt(Instr* instr) { |
| 381 | int imm = instr->ImmedMovwMovtField(); |
| 382 | int rd = instr->RdField(); |
| 383 | PrintRegister(rd); |
| 384 | out_buffer_pos_ += v8i::OS::SNPrintF(out_buffer_ + out_buffer_pos_, |
| 385 | ", #%d", imm); |
| 386 | } |
| 387 | |
| 388 | |
Steve Block | a7e24c1 | 2009-10-30 11:49:00 +0000 | [diff] [blame] | 389 | // FormatOption takes a formatting string and interprets it based on |
| 390 | // the current instructions. The format string points to the first |
| 391 | // character of the option string (the option escape has already been |
| 392 | // consumed by the caller.) FormatOption returns the number of |
| 393 | // characters that were consumed from the formatting string. |
| 394 | int Decoder::FormatOption(Instr* instr, const char* format) { |
| 395 | switch (format[0]) { |
| 396 | case 'a': { // 'a: accumulate multiplies |
| 397 | if (instr->Bit(21) == 0) { |
| 398 | Print("ul"); |
| 399 | } else { |
| 400 | Print("la"); |
| 401 | } |
| 402 | return 1; |
| 403 | } |
| 404 | case 'b': { // 'b: byte loads or stores |
| 405 | if (instr->HasB()) { |
| 406 | Print("b"); |
| 407 | } |
| 408 | return 1; |
| 409 | } |
| 410 | case 'c': { // 'cond: conditional execution |
| 411 | ASSERT(STRING_STARTS_WITH(format, "cond")); |
| 412 | PrintCondition(instr); |
| 413 | return 4; |
| 414 | } |
Ben Murdoch | 7f4d5bd | 2010-06-15 11:15:29 +0100 | [diff] [blame] | 415 | case 'f': { // 'f: bitfield instructions - v7 and above. |
| 416 | uint32_t lsbit = instr->Bits(11, 7); |
| 417 | uint32_t width = instr->Bits(20, 16) + 1; |
| 418 | if (instr->Bit(21) == 0) { |
| 419 | // BFC/BFI: |
| 420 | // Bits 20-16 represent most-significant bit. Covert to width. |
| 421 | width -= lsbit; |
| 422 | ASSERT(width > 0); |
| 423 | } |
| 424 | ASSERT((width + lsbit) <= 32); |
| 425 | out_buffer_pos_ += v8i::OS::SNPrintF(out_buffer_ + out_buffer_pos_, |
| 426 | "#%d, #%d", lsbit, width); |
| 427 | return 1; |
| 428 | } |
Steve Block | a7e24c1 | 2009-10-30 11:49:00 +0000 | [diff] [blame] | 429 | case 'h': { // 'h: halfword operation for extra loads and stores |
| 430 | if (instr->HasH()) { |
| 431 | Print("h"); |
| 432 | } else { |
| 433 | Print("b"); |
| 434 | } |
| 435 | return 1; |
| 436 | } |
| 437 | case 'l': { // 'l: branch and link |
| 438 | if (instr->HasLink()) { |
| 439 | Print("l"); |
| 440 | } |
| 441 | return 1; |
| 442 | } |
| 443 | case 'm': { |
Kristian Monsen | 9dcf7e2 | 2010-06-28 14:14:28 +0100 | [diff] [blame] | 444 | if (format[1] == 'w') { |
| 445 | // 'mw: movt/movw instructions. |
| 446 | PrintMovwMovt(instr); |
| 447 | return 2; |
| 448 | } |
| 449 | if (format[1] == 'e') { // 'memop: load/store instructions. |
Steve Block | a7e24c1 | 2009-10-30 11:49:00 +0000 | [diff] [blame] | 450 | ASSERT(STRING_STARTS_WITH(format, "memop")); |
| 451 | if (instr->HasL()) { |
| 452 | Print("ldr"); |
Kristian Monsen | 25f6136 | 2010-05-21 11:50:48 +0100 | [diff] [blame] | 453 | } else if ((instr->Bits(27, 25) == 0) && (instr->Bit(20) == 0)) { |
| 454 | if (instr->Bits(7, 4) == 0xf) { |
| 455 | Print("strd"); |
| 456 | } else { |
| 457 | Print("ldrd"); |
| 458 | } |
Steve Block | a7e24c1 | 2009-10-30 11:49:00 +0000 | [diff] [blame] | 459 | } else { |
| 460 | Print("str"); |
| 461 | } |
| 462 | return 5; |
| 463 | } |
| 464 | // 'msg: for simulator break instructions |
| 465 | ASSERT(STRING_STARTS_WITH(format, "msg")); |
| 466 | byte* str = |
| 467 | reinterpret_cast<byte*>(instr->InstructionBits() & 0x0fffffff); |
| 468 | out_buffer_pos_ += v8i::OS::SNPrintF(out_buffer_ + out_buffer_pos_, |
| 469 | "%s", converter_.NameInCode(str)); |
| 470 | return 3; |
| 471 | } |
| 472 | case 'o': { |
Andrei Popescu | 3100271 | 2010-02-23 13:46:05 +0000 | [diff] [blame] | 473 | if ((format[3] == '1') && (format[4] == '2')) { |
Steve Block | a7e24c1 | 2009-10-30 11:49:00 +0000 | [diff] [blame] | 474 | // 'off12: 12-bit offset for load and store instructions |
| 475 | ASSERT(STRING_STARTS_WITH(format, "off12")); |
| 476 | out_buffer_pos_ += v8i::OS::SNPrintF(out_buffer_ + out_buffer_pos_, |
| 477 | "%d", instr->Offset12Field()); |
| 478 | return 5; |
Steve Block | 6ded16b | 2010-05-10 14:33:55 +0100 | [diff] [blame] | 479 | } else if (format[3] == '0') { |
| 480 | // 'off0to3and8to19 16-bit immediate encoded in bits 19-8 and 3-0. |
| 481 | ASSERT(STRING_STARTS_WITH(format, "off0to3and8to19")); |
| 482 | out_buffer_pos_ += v8i::OS::SNPrintF(out_buffer_ + out_buffer_pos_, |
| 483 | "%d", |
| 484 | (instr->Bits(19, 8) << 4) + |
| 485 | instr->Bits(3, 0)); |
| 486 | return 15; |
Steve Block | a7e24c1 | 2009-10-30 11:49:00 +0000 | [diff] [blame] | 487 | } |
| 488 | // 'off8: 8-bit offset for extra load and store instructions |
| 489 | ASSERT(STRING_STARTS_WITH(format, "off8")); |
| 490 | int offs8 = (instr->ImmedHField() << 4) | instr->ImmedLField(); |
| 491 | out_buffer_pos_ += v8i::OS::SNPrintF(out_buffer_ + out_buffer_pos_, |
| 492 | "%d", offs8); |
| 493 | return 4; |
| 494 | } |
| 495 | case 'p': { // 'pu: P and U bits for load and store instructions |
| 496 | ASSERT(STRING_STARTS_WITH(format, "pu")); |
| 497 | PrintPU(instr); |
| 498 | return 2; |
| 499 | } |
| 500 | case 'r': { |
| 501 | return FormatRegister(instr, format); |
| 502 | } |
| 503 | case 's': { |
| 504 | if (format[1] == 'h') { // 'shift_op or 'shift_rm |
| 505 | if (format[6] == 'o') { // 'shift_op |
| 506 | ASSERT(STRING_STARTS_WITH(format, "shift_op")); |
| 507 | if (instr->TypeField() == 0) { |
| 508 | PrintShiftRm(instr); |
| 509 | } else { |
| 510 | ASSERT(instr->TypeField() == 1); |
| 511 | PrintShiftImm(instr); |
| 512 | } |
| 513 | return 8; |
| 514 | } else { // 'shift_rm |
| 515 | ASSERT(STRING_STARTS_WITH(format, "shift_rm")); |
| 516 | PrintShiftRm(instr); |
| 517 | return 8; |
| 518 | } |
| 519 | } else if (format[1] == 'w') { // 'swi |
| 520 | ASSERT(STRING_STARTS_WITH(format, "swi")); |
| 521 | PrintSoftwareInterrupt(instr->SwiField()); |
| 522 | return 3; |
| 523 | } else if (format[1] == 'i') { // 'sign: signed extra loads and stores |
| 524 | ASSERT(STRING_STARTS_WITH(format, "sign")); |
| 525 | if (instr->HasSign()) { |
| 526 | Print("s"); |
| 527 | } |
| 528 | return 4; |
| 529 | } |
| 530 | // 's: S field of data processing instructions |
| 531 | if (instr->HasS()) { |
| 532 | Print("s"); |
| 533 | } |
| 534 | return 1; |
| 535 | } |
| 536 | case 't': { // 'target: target of branch instructions |
| 537 | ASSERT(STRING_STARTS_WITH(format, "target")); |
| 538 | int off = (instr->SImmed24Field() << 2) + 8; |
| 539 | out_buffer_pos_ += v8i::OS::SNPrintF( |
| 540 | out_buffer_ + out_buffer_pos_, |
| 541 | "%+d -> %s", |
| 542 | off, |
| 543 | converter_.NameOfAddress(reinterpret_cast<byte*>(instr) + off)); |
| 544 | return 6; |
| 545 | } |
| 546 | case 'u': { // 'u: signed or unsigned multiplies |
| 547 | // The manual gets the meaning of bit 22 backwards in the multiply |
| 548 | // instruction overview on page A3.16.2. The instructions that |
| 549 | // exist in u and s variants are the following: |
| 550 | // smull A4.1.87 |
| 551 | // umull A4.1.129 |
| 552 | // umlal A4.1.128 |
| 553 | // smlal A4.1.76 |
| 554 | // For these 0 means u and 1 means s. As can be seen on their individual |
| 555 | // pages. The other 18 mul instructions have the bit set or unset in |
| 556 | // arbitrary ways that are unrelated to the signedness of the instruction. |
| 557 | // None of these 18 instructions exist in both a 'u' and an 's' variant. |
| 558 | |
| 559 | if (instr->Bit(22) == 0) { |
| 560 | Print("u"); |
| 561 | } else { |
| 562 | Print("s"); |
| 563 | } |
| 564 | return 1; |
| 565 | } |
Steve Block | d0582a6 | 2009-12-15 09:54:21 +0000 | [diff] [blame] | 566 | case 'v': { |
| 567 | return FormatVFPinstruction(instr, format); |
| 568 | } |
| 569 | case 'S': |
| 570 | case 'D': { |
| 571 | return FormatVFPRegister(instr, format); |
| 572 | } |
Steve Block | a7e24c1 | 2009-10-30 11:49:00 +0000 | [diff] [blame] | 573 | case 'w': { // 'w: W field of load and store instructions |
| 574 | if (instr->HasW()) { |
| 575 | Print("!"); |
| 576 | } |
| 577 | return 1; |
| 578 | } |
| 579 | default: { |
| 580 | UNREACHABLE(); |
| 581 | break; |
| 582 | } |
| 583 | } |
| 584 | UNREACHABLE(); |
| 585 | return -1; |
| 586 | } |
| 587 | |
| 588 | |
| 589 | // Format takes a formatting string for a whole instruction and prints it into |
| 590 | // the output buffer. All escaped options are handed to FormatOption to be |
| 591 | // parsed further. |
| 592 | void Decoder::Format(Instr* instr, const char* format) { |
| 593 | char cur = *format++; |
| 594 | while ((cur != 0) && (out_buffer_pos_ < (out_buffer_.length() - 1))) { |
| 595 | if (cur == '\'') { // Single quote is used as the formatting escape. |
| 596 | format += FormatOption(instr, format); |
| 597 | } else { |
| 598 | out_buffer_[out_buffer_pos_++] = cur; |
| 599 | } |
| 600 | cur = *format++; |
| 601 | } |
| 602 | out_buffer_[out_buffer_pos_] = '\0'; |
| 603 | } |
| 604 | |
| 605 | |
| 606 | // For currently unimplemented decodings the disassembler calls Unknown(instr) |
| 607 | // which will just print "unknown" of the instruction bits. |
| 608 | void Decoder::Unknown(Instr* instr) { |
| 609 | Format(instr, "unknown"); |
| 610 | } |
| 611 | |
| 612 | |
| 613 | void Decoder::DecodeType01(Instr* instr) { |
| 614 | int type = instr->TypeField(); |
| 615 | if ((type == 0) && instr->IsSpecialType0()) { |
| 616 | // multiply instruction or extra loads and stores |
| 617 | if (instr->Bits(7, 4) == 9) { |
| 618 | if (instr->Bit(24) == 0) { |
| 619 | // multiply instructions |
| 620 | if (instr->Bit(23) == 0) { |
| 621 | if (instr->Bit(21) == 0) { |
| 622 | // The MUL instruction description (A 4.1.33) refers to Rd as being |
| 623 | // the destination for the operation, but it confusingly uses the |
| 624 | // Rn field to encode it. |
| 625 | Format(instr, "mul'cond's 'rn, 'rm, 'rs"); |
| 626 | } else { |
| 627 | // The MLA instruction description (A 4.1.28) refers to the order |
| 628 | // of registers as "Rd, Rm, Rs, Rn". But confusingly it uses the |
| 629 | // Rn field to encode the Rd register and the Rd field to encode |
| 630 | // the Rn register. |
| 631 | Format(instr, "mla'cond's 'rn, 'rm, 'rs, 'rd"); |
| 632 | } |
| 633 | } else { |
| 634 | // The signed/long multiply instructions use the terms RdHi and RdLo |
| 635 | // when referring to the target registers. They are mapped to the Rn |
| 636 | // and Rd fields as follows: |
| 637 | // RdLo == Rd field |
| 638 | // RdHi == Rn field |
| 639 | // The order of registers is: <RdLo>, <RdHi>, <Rm>, <Rs> |
| 640 | Format(instr, "'um'al'cond's 'rd, 'rn, 'rm, 'rs"); |
| 641 | } |
| 642 | } else { |
| 643 | Unknown(instr); // not used by V8 |
| 644 | } |
Kristian Monsen | 25f6136 | 2010-05-21 11:50:48 +0100 | [diff] [blame] | 645 | } else if ((instr->Bit(20) == 0) && ((instr->Bits(7, 4) & 0xd) == 0xd)) { |
| 646 | // ldrd, strd |
| 647 | switch (instr->PUField()) { |
| 648 | case 0: { |
| 649 | if (instr->Bit(22) == 0) { |
| 650 | Format(instr, "'memop'cond's 'rd, ['rn], -'rm"); |
| 651 | } else { |
| 652 | Format(instr, "'memop'cond's 'rd, ['rn], #-'off8"); |
| 653 | } |
| 654 | break; |
| 655 | } |
| 656 | case 1: { |
| 657 | if (instr->Bit(22) == 0) { |
| 658 | Format(instr, "'memop'cond's 'rd, ['rn], +'rm"); |
| 659 | } else { |
| 660 | Format(instr, "'memop'cond's 'rd, ['rn], #+'off8"); |
| 661 | } |
| 662 | break; |
| 663 | } |
| 664 | case 2: { |
| 665 | if (instr->Bit(22) == 0) { |
| 666 | Format(instr, "'memop'cond's 'rd, ['rn, -'rm]'w"); |
| 667 | } else { |
| 668 | Format(instr, "'memop'cond's 'rd, ['rn, #-'off8]'w"); |
| 669 | } |
| 670 | break; |
| 671 | } |
| 672 | case 3: { |
| 673 | if (instr->Bit(22) == 0) { |
| 674 | Format(instr, "'memop'cond's 'rd, ['rn, +'rm]'w"); |
| 675 | } else { |
| 676 | Format(instr, "'memop'cond's 'rd, ['rn, #+'off8]'w"); |
| 677 | } |
| 678 | break; |
| 679 | } |
| 680 | default: { |
| 681 | // The PU field is a 2-bit field. |
| 682 | UNREACHABLE(); |
| 683 | break; |
| 684 | } |
| 685 | } |
Steve Block | a7e24c1 | 2009-10-30 11:49:00 +0000 | [diff] [blame] | 686 | } else { |
| 687 | // extra load/store instructions |
| 688 | switch (instr->PUField()) { |
| 689 | case 0: { |
| 690 | if (instr->Bit(22) == 0) { |
| 691 | Format(instr, "'memop'cond'sign'h 'rd, ['rn], -'rm"); |
| 692 | } else { |
| 693 | Format(instr, "'memop'cond'sign'h 'rd, ['rn], #-'off8"); |
| 694 | } |
| 695 | break; |
| 696 | } |
| 697 | case 1: { |
| 698 | if (instr->Bit(22) == 0) { |
| 699 | Format(instr, "'memop'cond'sign'h 'rd, ['rn], +'rm"); |
| 700 | } else { |
| 701 | Format(instr, "'memop'cond'sign'h 'rd, ['rn], #+'off8"); |
| 702 | } |
| 703 | break; |
| 704 | } |
| 705 | case 2: { |
| 706 | if (instr->Bit(22) == 0) { |
| 707 | Format(instr, "'memop'cond'sign'h 'rd, ['rn, -'rm]'w"); |
| 708 | } else { |
| 709 | Format(instr, "'memop'cond'sign'h 'rd, ['rn, #-'off8]'w"); |
| 710 | } |
| 711 | break; |
| 712 | } |
| 713 | case 3: { |
| 714 | if (instr->Bit(22) == 0) { |
| 715 | Format(instr, "'memop'cond'sign'h 'rd, ['rn, +'rm]'w"); |
| 716 | } else { |
| 717 | Format(instr, "'memop'cond'sign'h 'rd, ['rn, #+'off8]'w"); |
| 718 | } |
| 719 | break; |
| 720 | } |
| 721 | default: { |
| 722 | // The PU field is a 2-bit field. |
| 723 | UNREACHABLE(); |
| 724 | break; |
| 725 | } |
| 726 | } |
| 727 | return; |
| 728 | } |
Steve Block | 6ded16b | 2010-05-10 14:33:55 +0100 | [diff] [blame] | 729 | } else if ((type == 0) && instr->IsMiscType0()) { |
| 730 | if (instr->Bits(22, 21) == 1) { |
| 731 | switch (instr->Bits(7, 4)) { |
| 732 | case BX: |
| 733 | Format(instr, "bx'cond 'rm"); |
| 734 | break; |
| 735 | case BLX: |
| 736 | Format(instr, "blx'cond 'rm"); |
| 737 | break; |
| 738 | case BKPT: |
| 739 | Format(instr, "bkpt 'off0to3and8to19"); |
| 740 | break; |
| 741 | default: |
| 742 | Unknown(instr); // not used by V8 |
| 743 | break; |
| 744 | } |
| 745 | } else if (instr->Bits(22, 21) == 3) { |
| 746 | switch (instr->Bits(7, 4)) { |
| 747 | case CLZ: |
| 748 | Format(instr, "clz'cond 'rd, 'rm"); |
| 749 | break; |
| 750 | default: |
| 751 | Unknown(instr); // not used by V8 |
| 752 | break; |
| 753 | } |
| 754 | } else { |
| 755 | Unknown(instr); // not used by V8 |
| 756 | } |
Steve Block | a7e24c1 | 2009-10-30 11:49:00 +0000 | [diff] [blame] | 757 | } else { |
| 758 | switch (instr->OpcodeField()) { |
| 759 | case AND: { |
| 760 | Format(instr, "and'cond's 'rd, 'rn, 'shift_op"); |
| 761 | break; |
| 762 | } |
| 763 | case EOR: { |
| 764 | Format(instr, "eor'cond's 'rd, 'rn, 'shift_op"); |
| 765 | break; |
| 766 | } |
| 767 | case SUB: { |
| 768 | Format(instr, "sub'cond's 'rd, 'rn, 'shift_op"); |
| 769 | break; |
| 770 | } |
| 771 | case RSB: { |
| 772 | Format(instr, "rsb'cond's 'rd, 'rn, 'shift_op"); |
| 773 | break; |
| 774 | } |
| 775 | case ADD: { |
| 776 | Format(instr, "add'cond's 'rd, 'rn, 'shift_op"); |
| 777 | break; |
| 778 | } |
| 779 | case ADC: { |
| 780 | Format(instr, "adc'cond's 'rd, 'rn, 'shift_op"); |
| 781 | break; |
| 782 | } |
| 783 | case SBC: { |
| 784 | Format(instr, "sbc'cond's 'rd, 'rn, 'shift_op"); |
| 785 | break; |
| 786 | } |
| 787 | case RSC: { |
| 788 | Format(instr, "rsc'cond's 'rd, 'rn, 'shift_op"); |
| 789 | break; |
| 790 | } |
| 791 | case TST: { |
| 792 | if (instr->HasS()) { |
| 793 | Format(instr, "tst'cond 'rn, 'shift_op"); |
| 794 | } else { |
Kristian Monsen | 9dcf7e2 | 2010-06-28 14:14:28 +0100 | [diff] [blame] | 795 | Format(instr, "movw'cond 'mw"); |
Steve Block | a7e24c1 | 2009-10-30 11:49:00 +0000 | [diff] [blame] | 796 | } |
| 797 | break; |
| 798 | } |
| 799 | case TEQ: { |
| 800 | if (instr->HasS()) { |
| 801 | Format(instr, "teq'cond 'rn, 'shift_op"); |
| 802 | } else { |
Steve Block | 6ded16b | 2010-05-10 14:33:55 +0100 | [diff] [blame] | 803 | // Other instructions matching this pattern are handled in the |
| 804 | // miscellaneous instructions part above. |
| 805 | UNREACHABLE(); |
Steve Block | a7e24c1 | 2009-10-30 11:49:00 +0000 | [diff] [blame] | 806 | } |
| 807 | break; |
| 808 | } |
| 809 | case CMP: { |
| 810 | if (instr->HasS()) { |
| 811 | Format(instr, "cmp'cond 'rn, 'shift_op"); |
| 812 | } else { |
Kristian Monsen | 9dcf7e2 | 2010-06-28 14:14:28 +0100 | [diff] [blame] | 813 | Format(instr, "movt'cond 'mw"); |
Steve Block | a7e24c1 | 2009-10-30 11:49:00 +0000 | [diff] [blame] | 814 | } |
| 815 | break; |
| 816 | } |
| 817 | case CMN: { |
| 818 | if (instr->HasS()) { |
| 819 | Format(instr, "cmn'cond 'rn, 'shift_op"); |
| 820 | } else { |
Steve Block | 6ded16b | 2010-05-10 14:33:55 +0100 | [diff] [blame] | 821 | // Other instructions matching this pattern are handled in the |
| 822 | // miscellaneous instructions part above. |
| 823 | UNREACHABLE(); |
Steve Block | a7e24c1 | 2009-10-30 11:49:00 +0000 | [diff] [blame] | 824 | } |
| 825 | break; |
| 826 | } |
| 827 | case ORR: { |
| 828 | Format(instr, "orr'cond's 'rd, 'rn, 'shift_op"); |
| 829 | break; |
| 830 | } |
| 831 | case MOV: { |
| 832 | Format(instr, "mov'cond's 'rd, 'shift_op"); |
| 833 | break; |
| 834 | } |
| 835 | case BIC: { |
| 836 | Format(instr, "bic'cond's 'rd, 'rn, 'shift_op"); |
| 837 | break; |
| 838 | } |
| 839 | case MVN: { |
| 840 | Format(instr, "mvn'cond's 'rd, 'shift_op"); |
| 841 | break; |
| 842 | } |
| 843 | default: { |
| 844 | // The Opcode field is a 4-bit field. |
| 845 | UNREACHABLE(); |
| 846 | break; |
| 847 | } |
| 848 | } |
| 849 | } |
| 850 | } |
| 851 | |
| 852 | |
| 853 | void Decoder::DecodeType2(Instr* instr) { |
| 854 | switch (instr->PUField()) { |
| 855 | case 0: { |
| 856 | if (instr->HasW()) { |
| 857 | Unknown(instr); // not used in V8 |
| 858 | } |
| 859 | Format(instr, "'memop'cond'b 'rd, ['rn], #-'off12"); |
| 860 | break; |
| 861 | } |
| 862 | case 1: { |
| 863 | if (instr->HasW()) { |
| 864 | Unknown(instr); // not used in V8 |
| 865 | } |
| 866 | Format(instr, "'memop'cond'b 'rd, ['rn], #+'off12"); |
| 867 | break; |
| 868 | } |
| 869 | case 2: { |
| 870 | Format(instr, "'memop'cond'b 'rd, ['rn, #-'off12]'w"); |
| 871 | break; |
| 872 | } |
| 873 | case 3: { |
| 874 | Format(instr, "'memop'cond'b 'rd, ['rn, #+'off12]'w"); |
| 875 | break; |
| 876 | } |
| 877 | default: { |
| 878 | // The PU field is a 2-bit field. |
| 879 | UNREACHABLE(); |
| 880 | break; |
| 881 | } |
| 882 | } |
| 883 | } |
| 884 | |
| 885 | |
| 886 | void Decoder::DecodeType3(Instr* instr) { |
| 887 | switch (instr->PUField()) { |
| 888 | case 0: { |
| 889 | ASSERT(!instr->HasW()); |
| 890 | Format(instr, "'memop'cond'b 'rd, ['rn], -'shift_rm"); |
| 891 | break; |
| 892 | } |
| 893 | case 1: { |
| 894 | ASSERT(!instr->HasW()); |
| 895 | Format(instr, "'memop'cond'b 'rd, ['rn], +'shift_rm"); |
| 896 | break; |
| 897 | } |
| 898 | case 2: { |
| 899 | Format(instr, "'memop'cond'b 'rd, ['rn, -'shift_rm]'w"); |
| 900 | break; |
| 901 | } |
| 902 | case 3: { |
Andrei Popescu | 3100271 | 2010-02-23 13:46:05 +0000 | [diff] [blame] | 903 | if (instr->HasW() && (instr->Bits(6, 4) == 0x5)) { |
| 904 | uint32_t widthminus1 = static_cast<uint32_t>(instr->Bits(20, 16)); |
Ben Murdoch | 7f4d5bd | 2010-06-15 11:15:29 +0100 | [diff] [blame] | 905 | uint32_t lsbit = static_cast<uint32_t>(instr->Bits(11, 7)); |
Andrei Popescu | 3100271 | 2010-02-23 13:46:05 +0000 | [diff] [blame] | 906 | uint32_t msbit = widthminus1 + lsbit; |
| 907 | if (msbit <= 31) { |
Ben Murdoch | 7f4d5bd | 2010-06-15 11:15:29 +0100 | [diff] [blame] | 908 | if (instr->Bit(22)) { |
| 909 | Format(instr, "ubfx'cond 'rd, 'rm, 'f"); |
| 910 | } else { |
| 911 | Format(instr, "sbfx'cond 'rd, 'rm, 'f"); |
| 912 | } |
| 913 | } else { |
| 914 | UNREACHABLE(); |
| 915 | } |
| 916 | } else if (!instr->HasW() && (instr->Bits(6, 4) == 0x1)) { |
| 917 | uint32_t lsbit = static_cast<uint32_t>(instr->Bits(11, 7)); |
| 918 | uint32_t msbit = static_cast<uint32_t>(instr->Bits(20, 16)); |
| 919 | if (msbit >= lsbit) { |
| 920 | if (instr->RmField() == 15) { |
| 921 | Format(instr, "bfc'cond 'rd, 'f"); |
| 922 | } else { |
| 923 | Format(instr, "bfi'cond 'rd, 'rm, 'f"); |
| 924 | } |
Andrei Popescu | 3100271 | 2010-02-23 13:46:05 +0000 | [diff] [blame] | 925 | } else { |
| 926 | UNREACHABLE(); |
| 927 | } |
| 928 | } else { |
| 929 | Format(instr, "'memop'cond'b 'rd, ['rn, +'shift_rm]'w"); |
| 930 | } |
Steve Block | a7e24c1 | 2009-10-30 11:49:00 +0000 | [diff] [blame] | 931 | break; |
| 932 | } |
| 933 | default: { |
| 934 | // The PU field is a 2-bit field. |
| 935 | UNREACHABLE(); |
| 936 | break; |
| 937 | } |
| 938 | } |
| 939 | } |
| 940 | |
| 941 | |
| 942 | void Decoder::DecodeType4(Instr* instr) { |
| 943 | ASSERT(instr->Bit(22) == 0); // Privileged mode currently not supported. |
| 944 | if (instr->HasL()) { |
| 945 | Format(instr, "ldm'cond'pu 'rn'w, 'rlist"); |
| 946 | } else { |
| 947 | Format(instr, "stm'cond'pu 'rn'w, 'rlist"); |
| 948 | } |
| 949 | } |
| 950 | |
| 951 | |
| 952 | void Decoder::DecodeType5(Instr* instr) { |
| 953 | Format(instr, "b'l'cond 'target"); |
| 954 | } |
| 955 | |
| 956 | |
| 957 | void Decoder::DecodeType6(Instr* instr) { |
Steve Block | d0582a6 | 2009-12-15 09:54:21 +0000 | [diff] [blame] | 958 | DecodeType6CoprocessorIns(instr); |
Steve Block | a7e24c1 | 2009-10-30 11:49:00 +0000 | [diff] [blame] | 959 | } |
| 960 | |
| 961 | |
| 962 | void Decoder::DecodeType7(Instr* instr) { |
| 963 | if (instr->Bit(24) == 1) { |
| 964 | Format(instr, "swi'cond 'swi"); |
| 965 | } else { |
Steve Block | d0582a6 | 2009-12-15 09:54:21 +0000 | [diff] [blame] | 966 | DecodeTypeVFP(instr); |
Steve Block | a7e24c1 | 2009-10-30 11:49:00 +0000 | [diff] [blame] | 967 | } |
| 968 | } |
| 969 | |
Steve Block | a7e24c1 | 2009-10-30 11:49:00 +0000 | [diff] [blame] | 970 | void Decoder::DecodeUnconditional(Instr* instr) { |
| 971 | if (instr->Bits(7, 4) == 0xB && instr->Bits(27, 25) == 0 && instr->HasL()) { |
| 972 | Format(instr, "'memop'h'pu 'rd, "); |
| 973 | bool immediate = instr->HasB(); |
| 974 | switch (instr->PUField()) { |
| 975 | case 0: { |
| 976 | // Post index, negative. |
| 977 | if (instr->HasW()) { |
| 978 | Unknown(instr); |
| 979 | break; |
| 980 | } |
| 981 | if (immediate) { |
| 982 | Format(instr, "['rn], #-'imm12"); |
| 983 | } else { |
| 984 | Format(instr, "['rn], -'rm"); |
| 985 | } |
| 986 | break; |
| 987 | } |
| 988 | case 1: { |
| 989 | // Post index, positive. |
| 990 | if (instr->HasW()) { |
| 991 | Unknown(instr); |
| 992 | break; |
| 993 | } |
| 994 | if (immediate) { |
| 995 | Format(instr, "['rn], #+'imm12"); |
| 996 | } else { |
| 997 | Format(instr, "['rn], +'rm"); |
| 998 | } |
| 999 | break; |
| 1000 | } |
| 1001 | case 2: { |
| 1002 | // Pre index or offset, negative. |
| 1003 | if (immediate) { |
| 1004 | Format(instr, "['rn, #-'imm12]'w"); |
| 1005 | } else { |
| 1006 | Format(instr, "['rn, -'rm]'w"); |
| 1007 | } |
| 1008 | break; |
| 1009 | } |
| 1010 | case 3: { |
| 1011 | // Pre index or offset, positive. |
| 1012 | if (immediate) { |
| 1013 | Format(instr, "['rn, #+'imm12]'w"); |
| 1014 | } else { |
| 1015 | Format(instr, "['rn, +'rm]'w"); |
| 1016 | } |
| 1017 | break; |
| 1018 | } |
| 1019 | default: { |
| 1020 | // The PU field is a 2-bit field. |
| 1021 | UNREACHABLE(); |
| 1022 | break; |
| 1023 | } |
| 1024 | } |
| 1025 | return; |
| 1026 | } |
| 1027 | Format(instr, "break 'msg"); |
| 1028 | } |
| 1029 | |
| 1030 | |
Steve Block | d0582a6 | 2009-12-15 09:54:21 +0000 | [diff] [blame] | 1031 | // void Decoder::DecodeTypeVFP(Instr* instr) |
Leon Clarke | e46be81 | 2010-01-19 14:06:41 +0000 | [diff] [blame] | 1032 | // vmov: Sn = Rt |
| 1033 | // vmov: Rt = Sn |
| 1034 | // vcvt: Dd = Sm |
| 1035 | // vcvt: Sd = Dm |
| 1036 | // Dd = vadd(Dn, Dm) |
| 1037 | // Dd = vsub(Dn, Dm) |
| 1038 | // Dd = vmul(Dn, Dm) |
| 1039 | // Dd = vdiv(Dn, Dm) |
Steve Block | d0582a6 | 2009-12-15 09:54:21 +0000 | [diff] [blame] | 1040 | // vcmp(Dd, Dm) |
Steve Block | 8defd9f | 2010-07-08 12:39:36 +0100 | [diff] [blame^] | 1041 | // vmrs |
| 1042 | // Dd = vsqrt(Dm) |
Steve Block | d0582a6 | 2009-12-15 09:54:21 +0000 | [diff] [blame] | 1043 | void Decoder::DecodeTypeVFP(Instr* instr) { |
| 1044 | ASSERT((instr->TypeField() == 7) && (instr->Bit(24) == 0x0) ); |
Steve Block | 6ded16b | 2010-05-10 14:33:55 +0100 | [diff] [blame] | 1045 | ASSERT(instr->Bits(11, 9) == 0x5); |
Steve Block | d0582a6 | 2009-12-15 09:54:21 +0000 | [diff] [blame] | 1046 | |
Steve Block | 6ded16b | 2010-05-10 14:33:55 +0100 | [diff] [blame] | 1047 | if (instr->Bit(4) == 0) { |
| 1048 | if (instr->Opc1Field() == 0x7) { |
| 1049 | // Other data processing instructions |
Steve Block | 8defd9f | 2010-07-08 12:39:36 +0100 | [diff] [blame^] | 1050 | if ((instr->Opc2Field() == 0x0) && (instr->Opc3Field() == 0x1)) { |
| 1051 | // vmov register to register. |
| 1052 | if (instr->SzField() == 0x1) { |
| 1053 | Format(instr, "vmov.f64'cond 'Dd, 'Dm"); |
| 1054 | } else { |
| 1055 | Unknown(instr); // Not used by V8. |
| 1056 | } |
| 1057 | } else if ((instr->Opc2Field() == 0x7) && (instr->Opc3Field() == 0x3)) { |
Steve Block | 6ded16b | 2010-05-10 14:33:55 +0100 | [diff] [blame] | 1058 | DecodeVCVTBetweenDoubleAndSingle(instr); |
| 1059 | } else if ((instr->Opc2Field() == 0x8) && (instr->Opc3Field() & 0x1)) { |
| 1060 | DecodeVCVTBetweenFloatingPointAndInteger(instr); |
| 1061 | } else if (((instr->Opc2Field() >> 1) == 0x6) && |
| 1062 | (instr->Opc3Field() & 0x1)) { |
| 1063 | DecodeVCVTBetweenFloatingPointAndInteger(instr); |
| 1064 | } else if (((instr->Opc2Field() == 0x4) || (instr->Opc2Field() == 0x5)) && |
| 1065 | (instr->Opc3Field() & 0x1)) { |
| 1066 | DecodeVCMP(instr); |
Steve Block | 8defd9f | 2010-07-08 12:39:36 +0100 | [diff] [blame^] | 1067 | } else if (((instr->Opc2Field() == 0x1)) && (instr->Opc3Field() == 0x3)) { |
| 1068 | Format(instr, "vsqrt.f64'cond 'Dd, 'Dm"); |
Steve Block | 6ded16b | 2010-05-10 14:33:55 +0100 | [diff] [blame] | 1069 | } else { |
| 1070 | Unknown(instr); // Not used by V8. |
| 1071 | } |
| 1072 | } else if (instr->Opc1Field() == 0x3) { |
| 1073 | if (instr->SzField() == 0x1) { |
| 1074 | if (instr->Opc3Field() & 0x1) { |
| 1075 | Format(instr, "vsub.f64'cond 'Dd, 'Dn, 'Dm"); |
| 1076 | } else { |
| 1077 | Format(instr, "vadd.f64'cond 'Dd, 'Dn, 'Dm"); |
| 1078 | } |
| 1079 | } else { |
| 1080 | Unknown(instr); // Not used by V8. |
| 1081 | } |
| 1082 | } else if ((instr->Opc1Field() == 0x2) && !(instr->Opc3Field() & 0x1)) { |
| 1083 | if (instr->SzField() == 0x1) { |
| 1084 | Format(instr, "vmul.f64'cond 'Dd, 'Dn, 'Dm"); |
| 1085 | } else { |
| 1086 | Unknown(instr); // Not used by V8. |
| 1087 | } |
| 1088 | } else if ((instr->Opc1Field() == 0x4) && !(instr->Opc3Field() & 0x1)) { |
| 1089 | if (instr->SzField() == 0x1) { |
Steve Block | d0582a6 | 2009-12-15 09:54:21 +0000 | [diff] [blame] | 1090 | Format(instr, "vdiv.f64'cond 'Dd, 'Dn, 'Dm"); |
Steve Block | 6ded16b | 2010-05-10 14:33:55 +0100 | [diff] [blame] | 1091 | } else { |
| 1092 | Unknown(instr); // Not used by V8. |
| 1093 | } |
Steve Block | d0582a6 | 2009-12-15 09:54:21 +0000 | [diff] [blame] | 1094 | } else { |
| 1095 | Unknown(instr); // Not used by V8. |
| 1096 | } |
| 1097 | } else { |
Steve Block | 6ded16b | 2010-05-10 14:33:55 +0100 | [diff] [blame] | 1098 | if ((instr->VCField() == 0x0) && |
| 1099 | (instr->VAField() == 0x0)) { |
| 1100 | DecodeVMOVBetweenCoreAndSinglePrecisionRegisters(instr); |
| 1101 | } else if ((instr->VLField() == 0x1) && |
| 1102 | (instr->VCField() == 0x0) && |
| 1103 | (instr->VAField() == 0x7) && |
| 1104 | (instr->Bits(19, 16) == 0x1)) { |
| 1105 | if (instr->Bits(15, 12) == 0xF) |
| 1106 | Format(instr, "vmrs'cond APSR, FPSCR"); |
| 1107 | else |
| 1108 | Unknown(instr); // Not used by V8. |
Steve Block | d0582a6 | 2009-12-15 09:54:21 +0000 | [diff] [blame] | 1109 | } else { |
| 1110 | Unknown(instr); // Not used by V8. |
| 1111 | } |
| 1112 | } |
| 1113 | } |
| 1114 | |
| 1115 | |
Steve Block | 6ded16b | 2010-05-10 14:33:55 +0100 | [diff] [blame] | 1116 | void Decoder::DecodeVMOVBetweenCoreAndSinglePrecisionRegisters(Instr* instr) { |
| 1117 | ASSERT((instr->Bit(4) == 1) && (instr->VCField() == 0x0) && |
| 1118 | (instr->VAField() == 0x0)); |
| 1119 | |
| 1120 | bool to_arm_register = (instr->VLField() == 0x1); |
| 1121 | |
| 1122 | if (to_arm_register) { |
| 1123 | Format(instr, "vmov'cond 'rt, 'Sn"); |
| 1124 | } else { |
| 1125 | Format(instr, "vmov'cond 'Sn, 'rt"); |
| 1126 | } |
| 1127 | } |
| 1128 | |
| 1129 | |
| 1130 | void Decoder::DecodeVCMP(Instr* instr) { |
| 1131 | ASSERT((instr->Bit(4) == 0) && (instr->Opc1Field() == 0x7)); |
| 1132 | ASSERT(((instr->Opc2Field() == 0x4) || (instr->Opc2Field() == 0x5)) && |
| 1133 | (instr->Opc3Field() & 0x1)); |
| 1134 | |
| 1135 | // Comparison. |
| 1136 | bool dp_operation = (instr->SzField() == 1); |
| 1137 | bool raise_exception_for_qnan = (instr->Bit(7) == 0x1); |
| 1138 | |
| 1139 | if (dp_operation && !raise_exception_for_qnan) { |
| 1140 | Format(instr, "vcmp.f64'cond 'Dd, 'Dm"); |
| 1141 | } else { |
| 1142 | Unknown(instr); // Not used by V8. |
| 1143 | } |
| 1144 | } |
| 1145 | |
| 1146 | |
| 1147 | void Decoder::DecodeVCVTBetweenDoubleAndSingle(Instr* instr) { |
| 1148 | ASSERT((instr->Bit(4) == 0) && (instr->Opc1Field() == 0x7)); |
| 1149 | ASSERT((instr->Opc2Field() == 0x7) && (instr->Opc3Field() == 0x3)); |
| 1150 | |
| 1151 | bool double_to_single = (instr->SzField() == 1); |
| 1152 | |
| 1153 | if (double_to_single) { |
| 1154 | Format(instr, "vcvt.f32.f64'cond 'Sd, 'Dm"); |
| 1155 | } else { |
| 1156 | Format(instr, "vcvt.f64.f32'cond 'Dd, 'Sm"); |
| 1157 | } |
| 1158 | } |
| 1159 | |
| 1160 | |
| 1161 | void Decoder::DecodeVCVTBetweenFloatingPointAndInteger(Instr* instr) { |
| 1162 | ASSERT((instr->Bit(4) == 0) && (instr->Opc1Field() == 0x7)); |
| 1163 | ASSERT(((instr->Opc2Field() == 0x8) && (instr->Opc3Field() & 0x1)) || |
| 1164 | (((instr->Opc2Field() >> 1) == 0x6) && (instr->Opc3Field() & 0x1))); |
| 1165 | |
| 1166 | bool to_integer = (instr->Bit(18) == 1); |
| 1167 | bool dp_operation = (instr->SzField() == 1); |
| 1168 | if (to_integer) { |
| 1169 | bool unsigned_integer = (instr->Bit(16) == 0); |
| 1170 | |
| 1171 | if (dp_operation) { |
| 1172 | if (unsigned_integer) { |
| 1173 | Format(instr, "vcvt.u32.f64'cond 'Sd, 'Dm"); |
| 1174 | } else { |
| 1175 | Format(instr, "vcvt.s32.f64'cond 'Sd, 'Dm"); |
| 1176 | } |
| 1177 | } else { |
| 1178 | if (unsigned_integer) { |
| 1179 | Format(instr, "vcvt.u32.f32'cond 'Sd, 'Sm"); |
| 1180 | } else { |
| 1181 | Format(instr, "vcvt.s32.f32'cond 'Sd, 'Sm"); |
| 1182 | } |
| 1183 | } |
| 1184 | } else { |
| 1185 | bool unsigned_integer = (instr->Bit(7) == 0); |
| 1186 | |
| 1187 | if (dp_operation) { |
| 1188 | if (unsigned_integer) { |
| 1189 | Format(instr, "vcvt.f64.u32'cond 'Dd, 'Sm"); |
| 1190 | } else { |
| 1191 | Format(instr, "vcvt.f64.s32'cond 'Dd, 'Sm"); |
| 1192 | } |
| 1193 | } else { |
| 1194 | if (unsigned_integer) { |
| 1195 | Format(instr, "vcvt.f32.u32'cond 'Sd, 'Sm"); |
| 1196 | } else { |
| 1197 | Format(instr, "vcvt.f32.s32'cond 'Sd, 'Sm"); |
| 1198 | } |
| 1199 | } |
| 1200 | } |
| 1201 | } |
| 1202 | |
| 1203 | |
Steve Block | d0582a6 | 2009-12-15 09:54:21 +0000 | [diff] [blame] | 1204 | // Decode Type 6 coprocessor instructions. |
Leon Clarke | e46be81 | 2010-01-19 14:06:41 +0000 | [diff] [blame] | 1205 | // Dm = vmov(Rt, Rt2) |
| 1206 | // <Rt, Rt2> = vmov(Dm) |
Leon Clarke | d91b9f7 | 2010-01-27 17:25:45 +0000 | [diff] [blame] | 1207 | // Ddst = MEM(Rbase + 4*offset). |
| 1208 | // MEM(Rbase + 4*offset) = Dsrc. |
Steve Block | d0582a6 | 2009-12-15 09:54:21 +0000 | [diff] [blame] | 1209 | void Decoder::DecodeType6CoprocessorIns(Instr* instr) { |
| 1210 | ASSERT((instr->TypeField() == 6)); |
| 1211 | |
Steve Block | 6ded16b | 2010-05-10 14:33:55 +0100 | [diff] [blame] | 1212 | if (instr->CoprocessorField() == 0xA) { |
| 1213 | switch (instr->OpcodeField()) { |
| 1214 | case 0x8: |
| 1215 | if (instr->HasL()) { |
| 1216 | Format(instr, "vldr'cond 'Sd, ['rn - 4*'off8]"); |
| 1217 | } else { |
| 1218 | Format(instr, "vstr'cond 'Sd, ['rn - 4*'off8]"); |
| 1219 | } |
| 1220 | break; |
| 1221 | case 0xC: |
| 1222 | if (instr->HasL()) { |
| 1223 | Format(instr, "vldr'cond 'Sd, ['rn + 4*'off8]"); |
| 1224 | } else { |
| 1225 | Format(instr, "vstr'cond 'Sd, ['rn + 4*'off8]"); |
| 1226 | } |
| 1227 | break; |
| 1228 | default: |
| 1229 | Unknown(instr); // Not used by V8. |
| 1230 | break; |
| 1231 | } |
| 1232 | } else if (instr->CoprocessorField() == 0xB) { |
Leon Clarke | d91b9f7 | 2010-01-27 17:25:45 +0000 | [diff] [blame] | 1233 | switch (instr->OpcodeField()) { |
| 1234 | case 0x2: |
| 1235 | // Load and store double to two GP registers |
| 1236 | if (instr->Bits(7, 4) != 0x1) { |
| 1237 | Unknown(instr); // Not used by V8. |
| 1238 | } else if (instr->HasL()) { |
| 1239 | Format(instr, "vmov'cond 'rt, 'rn, 'Dm"); |
| 1240 | } else { |
| 1241 | Format(instr, "vmov'cond 'Dm, 'rt, 'rn"); |
| 1242 | } |
| 1243 | break; |
| 1244 | case 0x8: |
| 1245 | if (instr->HasL()) { |
| 1246 | Format(instr, "vldr'cond 'Dd, ['rn - 4*'off8]"); |
| 1247 | } else { |
| 1248 | Format(instr, "vstr'cond 'Dd, ['rn - 4*'off8]"); |
| 1249 | } |
| 1250 | break; |
| 1251 | case 0xC: |
| 1252 | if (instr->HasL()) { |
| 1253 | Format(instr, "vldr'cond 'Dd, ['rn + 4*'off8]"); |
| 1254 | } else { |
| 1255 | Format(instr, "vstr'cond 'Dd, ['rn + 4*'off8]"); |
| 1256 | } |
| 1257 | break; |
| 1258 | default: |
| 1259 | Unknown(instr); // Not used by V8. |
| 1260 | break; |
| 1261 | } |
Steve Block | 6ded16b | 2010-05-10 14:33:55 +0100 | [diff] [blame] | 1262 | } else { |
| 1263 | UNIMPLEMENTED(); // Not used by V8. |
Steve Block | d0582a6 | 2009-12-15 09:54:21 +0000 | [diff] [blame] | 1264 | } |
| 1265 | } |
| 1266 | |
| 1267 | |
Steve Block | a7e24c1 | 2009-10-30 11:49:00 +0000 | [diff] [blame] | 1268 | // Disassemble the instruction at *instr_ptr into the output buffer. |
| 1269 | int Decoder::InstructionDecode(byte* instr_ptr) { |
| 1270 | Instr* instr = Instr::At(instr_ptr); |
| 1271 | // Print raw instruction bytes. |
| 1272 | out_buffer_pos_ += v8i::OS::SNPrintF(out_buffer_ + out_buffer_pos_, |
| 1273 | "%08x ", |
| 1274 | instr->InstructionBits()); |
| 1275 | if (instr->ConditionField() == special_condition) { |
| 1276 | DecodeUnconditional(instr); |
| 1277 | return Instr::kInstrSize; |
| 1278 | } |
| 1279 | switch (instr->TypeField()) { |
| 1280 | case 0: |
| 1281 | case 1: { |
| 1282 | DecodeType01(instr); |
| 1283 | break; |
| 1284 | } |
| 1285 | case 2: { |
| 1286 | DecodeType2(instr); |
| 1287 | break; |
| 1288 | } |
| 1289 | case 3: { |
| 1290 | DecodeType3(instr); |
| 1291 | break; |
| 1292 | } |
| 1293 | case 4: { |
| 1294 | DecodeType4(instr); |
| 1295 | break; |
| 1296 | } |
| 1297 | case 5: { |
| 1298 | DecodeType5(instr); |
| 1299 | break; |
| 1300 | } |
| 1301 | case 6: { |
| 1302 | DecodeType6(instr); |
| 1303 | break; |
| 1304 | } |
| 1305 | case 7: { |
| 1306 | DecodeType7(instr); |
| 1307 | break; |
| 1308 | } |
| 1309 | default: { |
| 1310 | // The type field is 3-bits in the ARM encoding. |
| 1311 | UNREACHABLE(); |
| 1312 | break; |
| 1313 | } |
| 1314 | } |
| 1315 | return Instr::kInstrSize; |
| 1316 | } |
| 1317 | |
| 1318 | |
| 1319 | } } // namespace assembler::arm |
| 1320 | |
| 1321 | |
| 1322 | |
| 1323 | //------------------------------------------------------------------------------ |
| 1324 | |
| 1325 | namespace disasm { |
| 1326 | |
| 1327 | namespace v8i = v8::internal; |
| 1328 | |
| 1329 | |
| 1330 | const char* NameConverter::NameOfAddress(byte* addr) const { |
| 1331 | static v8::internal::EmbeddedVector<char, 32> tmp_buffer; |
| 1332 | v8::internal::OS::SNPrintF(tmp_buffer, "%p", addr); |
| 1333 | return tmp_buffer.start(); |
| 1334 | } |
| 1335 | |
| 1336 | |
| 1337 | const char* NameConverter::NameOfConstant(byte* addr) const { |
| 1338 | return NameOfAddress(addr); |
| 1339 | } |
| 1340 | |
| 1341 | |
| 1342 | const char* NameConverter::NameOfCPURegister(int reg) const { |
| 1343 | return assembler::arm::Registers::Name(reg); |
| 1344 | } |
| 1345 | |
| 1346 | |
| 1347 | const char* NameConverter::NameOfByteCPURegister(int reg) const { |
| 1348 | UNREACHABLE(); // ARM does not have the concept of a byte register |
| 1349 | return "nobytereg"; |
| 1350 | } |
| 1351 | |
| 1352 | |
| 1353 | const char* NameConverter::NameOfXMMRegister(int reg) const { |
| 1354 | UNREACHABLE(); // ARM does not have any XMM registers |
| 1355 | return "noxmmreg"; |
| 1356 | } |
| 1357 | |
| 1358 | |
| 1359 | const char* NameConverter::NameInCode(byte* addr) const { |
| 1360 | // The default name converter is called for unknown code. So we will not try |
| 1361 | // to access any memory. |
| 1362 | return ""; |
| 1363 | } |
| 1364 | |
| 1365 | |
| 1366 | //------------------------------------------------------------------------------ |
| 1367 | |
| 1368 | Disassembler::Disassembler(const NameConverter& converter) |
| 1369 | : converter_(converter) {} |
| 1370 | |
| 1371 | |
| 1372 | Disassembler::~Disassembler() {} |
| 1373 | |
| 1374 | |
| 1375 | int Disassembler::InstructionDecode(v8::internal::Vector<char> buffer, |
| 1376 | byte* instruction) { |
| 1377 | assembler::arm::Decoder d(converter_, buffer); |
| 1378 | return d.InstructionDecode(instruction); |
| 1379 | } |
| 1380 | |
| 1381 | |
| 1382 | int Disassembler::ConstantPoolSizeAt(byte* instruction) { |
| 1383 | int instruction_bits = *(reinterpret_cast<int*>(instruction)); |
| 1384 | if ((instruction_bits & 0xfff00000) == 0x03000000) { |
| 1385 | return instruction_bits & 0x0000ffff; |
| 1386 | } else { |
| 1387 | return -1; |
| 1388 | } |
| 1389 | } |
| 1390 | |
| 1391 | |
| 1392 | void Disassembler::Disassemble(FILE* f, byte* begin, byte* end) { |
| 1393 | NameConverter converter; |
| 1394 | Disassembler d(converter); |
| 1395 | for (byte* pc = begin; pc < end;) { |
| 1396 | v8::internal::EmbeddedVector<char, 128> buffer; |
| 1397 | buffer[0] = '\0'; |
| 1398 | byte* prev_pc = pc; |
| 1399 | pc += d.InstructionDecode(buffer, pc); |
| 1400 | fprintf(f, "%p %08x %s\n", |
| 1401 | prev_pc, *reinterpret_cast<int32_t*>(prev_pc), buffer.start()); |
| 1402 | } |
| 1403 | } |
| 1404 | |
| 1405 | |
| 1406 | } // namespace disasm |
Leon Clarke | f7060e2 | 2010-06-03 12:02:55 +0100 | [diff] [blame] | 1407 | |
| 1408 | #endif // V8_TARGET_ARCH_ARM |