Andrei Popescu | 3100271 | 2010-02-23 13:46:05 +0000 | [diff] [blame] | 1 | // Copyright (c) 1994-2006 Sun Microsystems Inc. |
| 2 | // All Rights Reserved. |
| 3 | // |
| 4 | // Redistribution and use in source and binary forms, with or without |
| 5 | // modification, are permitted provided that the following conditions are |
| 6 | // met: |
| 7 | // |
| 8 | // - Redistributions of source code must retain the above copyright notice, |
| 9 | // this list of conditions and the following disclaimer. |
| 10 | // |
| 11 | // - Redistribution in binary form must reproduce the above copyright |
| 12 | // notice, this list of conditions and the following disclaimer in the |
| 13 | // documentation and/or other materials provided with the distribution. |
| 14 | // |
| 15 | // - Neither the name of Sun Microsystems or the names of contributors may |
| 16 | // be used to endorse or promote products derived from this software without |
| 17 | // specific prior written permission. |
| 18 | // |
| 19 | // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS |
| 20 | // IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, |
| 21 | // THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR |
| 22 | // PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR |
| 23 | // CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, |
| 24 | // EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, |
| 25 | // PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR |
| 26 | // PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF |
| 27 | // LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING |
| 28 | // NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS |
| 29 | // SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
| 30 | |
| 31 | // The original source code covered by the above license above has been |
| 32 | // modified significantly by Google Inc. |
Ben Murdoch | 3ef787d | 2012-04-12 10:51:47 +0100 | [diff] [blame] | 33 | // Copyright 2012 the V8 project authors. All rights reserved. |
Andrei Popescu | 3100271 | 2010-02-23 13:46:05 +0000 | [diff] [blame] | 34 | |
| 35 | |
Ben Murdoch | b8a8cc1 | 2014-11-26 15:28:44 +0000 | [diff] [blame] | 36 | #include "src/v8.h" |
Leon Clarke | f7060e2 | 2010-06-03 12:02:55 +0100 | [diff] [blame] | 37 | |
Ben Murdoch | b8a8cc1 | 2014-11-26 15:28:44 +0000 | [diff] [blame] | 38 | #if V8_TARGET_ARCH_MIPS |
Leon Clarke | f7060e2 | 2010-06-03 12:02:55 +0100 | [diff] [blame] | 39 | |
Ben Murdoch | b8a8cc1 | 2014-11-26 15:28:44 +0000 | [diff] [blame] | 40 | #include "src/base/bits.h" |
| 41 | #include "src/base/cpu.h" |
| 42 | #include "src/mips/assembler-mips-inl.h" |
| 43 | #include "src/serialize.h" |
Andrei Popescu | 3100271 | 2010-02-23 13:46:05 +0000 | [diff] [blame] | 44 | |
Andrei Popescu | 3100271 | 2010-02-23 13:46:05 +0000 | [diff] [blame] | 45 | namespace v8 { |
| 46 | namespace internal { |
| 47 | |
Ben Murdoch | 589d697 | 2011-11-30 16:04:58 +0000 | [diff] [blame] | 48 | // Get the CPU features enabled by the build. For cross compilation the |
| 49 | // preprocessor symbols CAN_USE_FPU_INSTRUCTIONS |
| 50 | // can be defined to enable FPU instructions when building the |
| 51 | // snapshot. |
Ben Murdoch | b8a8cc1 | 2014-11-26 15:28:44 +0000 | [diff] [blame] | 52 | static unsigned CpuFeaturesImpliedByCompiler() { |
| 53 | unsigned answer = 0; |
Ben Murdoch | 589d697 | 2011-11-30 16:04:58 +0000 | [diff] [blame] | 54 | #ifdef CAN_USE_FPU_INSTRUCTIONS |
| 55 | answer |= 1u << FPU; |
| 56 | #endif // def CAN_USE_FPU_INSTRUCTIONS |
| 57 | |
Ben Murdoch | 589d697 | 2011-11-30 16:04:58 +0000 | [diff] [blame] | 58 | // If the compiler is allowed to use FPU then we can use FPU too in our code |
| 59 | // generation even when generating snapshots. This won't work for cross |
| 60 | // compilation. |
Ben Murdoch | b8a8cc1 | 2014-11-26 15:28:44 +0000 | [diff] [blame] | 61 | #if defined(__mips__) && defined(__mips_hard_float) && __mips_hard_float != 0 |
Ben Murdoch | 589d697 | 2011-11-30 16:04:58 +0000 | [diff] [blame] | 62 | answer |= 1u << FPU; |
Ben Murdoch | b8a8cc1 | 2014-11-26 15:28:44 +0000 | [diff] [blame] | 63 | #endif |
Ben Murdoch | 589d697 | 2011-11-30 16:04:58 +0000 | [diff] [blame] | 64 | |
| 65 | return answer; |
| 66 | } |
| 67 | |
| 68 | |
Ben Murdoch | b8a8cc1 | 2014-11-26 15:28:44 +0000 | [diff] [blame] | 69 | const char* DoubleRegister::AllocationIndexToString(int index) { |
| 70 | DCHECK(index >= 0 && index < kMaxNumAllocatableRegisters); |
| 71 | const char* const names[] = { |
| 72 | "f0", |
| 73 | "f2", |
| 74 | "f4", |
| 75 | "f6", |
| 76 | "f8", |
| 77 | "f10", |
| 78 | "f12", |
| 79 | "f14", |
| 80 | "f16", |
| 81 | "f18", |
| 82 | "f20", |
| 83 | "f22", |
| 84 | "f24", |
| 85 | "f26" |
| 86 | }; |
| 87 | return names[index]; |
| 88 | } |
Ben Murdoch | 589d697 | 2011-11-30 16:04:58 +0000 | [diff] [blame] | 89 | |
Ben Murdoch | 589d697 | 2011-11-30 16:04:58 +0000 | [diff] [blame] | 90 | |
Ben Murdoch | b8a8cc1 | 2014-11-26 15:28:44 +0000 | [diff] [blame] | 91 | void CpuFeatures::ProbeImpl(bool cross_compile) { |
| 92 | supported_ |= CpuFeaturesImpliedByCompiler(); |
| 93 | |
| 94 | // Only use statically determined features for cross compile (snapshot). |
| 95 | if (cross_compile) return; |
Ben Murdoch | 589d697 | 2011-11-30 16:04:58 +0000 | [diff] [blame] | 96 | |
Steve Block | 44f0eee | 2011-05-26 01:26:41 +0100 | [diff] [blame] | 97 | // If the compiler is allowed to use fpu then we can use fpu too in our |
| 98 | // code generation. |
Ben Murdoch | b8a8cc1 | 2014-11-26 15:28:44 +0000 | [diff] [blame] | 99 | #ifndef __mips__ |
| 100 | // For the simulator build, use FPU. |
| 101 | supported_ |= 1u << FPU; |
| 102 | #if defined(_MIPS_ARCH_MIPS32R6) |
| 103 | // FP64 mode is implied on r6. |
| 104 | supported_ |= 1u << FP64FPU; |
| 105 | #endif |
| 106 | #if defined(FPU_MODE_FP64) |
| 107 | supported_ |= 1u << FP64FPU; |
| 108 | #endif |
Steve Block | 44f0eee | 2011-05-26 01:26:41 +0100 | [diff] [blame] | 109 | #else |
Ben Murdoch | b8a8cc1 | 2014-11-26 15:28:44 +0000 | [diff] [blame] | 110 | // Probe for additional features at runtime. |
| 111 | base::CPU cpu; |
| 112 | if (cpu.has_fpu()) supported_ |= 1u << FPU; |
| 113 | #if defined(FPU_MODE_FPXX) |
| 114 | if (cpu.is_fp64_mode()) supported_ |= 1u << FP64FPU; |
| 115 | #elif defined(FPU_MODE_FP64) |
| 116 | supported_ |= 1u << FP64FPU; |
| 117 | #endif |
| 118 | #if defined(_MIPS_ARCH_MIPS32RX) |
| 119 | if (cpu.architecture() == 6) { |
| 120 | supported_ |= 1u << MIPSr6; |
| 121 | } else if (cpu.architecture() == 2) { |
| 122 | supported_ |= 1u << MIPSr1; |
| 123 | supported_ |= 1u << MIPSr2; |
| 124 | } else { |
| 125 | supported_ |= 1u << MIPSr1; |
Steve Block | 44f0eee | 2011-05-26 01:26:41 +0100 | [diff] [blame] | 126 | } |
Steve Block | 44f0eee | 2011-05-26 01:26:41 +0100 | [diff] [blame] | 127 | #endif |
Ben Murdoch | b8a8cc1 | 2014-11-26 15:28:44 +0000 | [diff] [blame] | 128 | #endif |
Steve Block | 44f0eee | 2011-05-26 01:26:41 +0100 | [diff] [blame] | 129 | } |
Andrei Popescu | 3100271 | 2010-02-23 13:46:05 +0000 | [diff] [blame] | 130 | |
| 131 | |
Ben Murdoch | b8a8cc1 | 2014-11-26 15:28:44 +0000 | [diff] [blame] | 132 | void CpuFeatures::PrintTarget() { } |
| 133 | void CpuFeatures::PrintFeatures() { } |
| 134 | |
| 135 | |
Andrei Popescu | 3100271 | 2010-02-23 13:46:05 +0000 | [diff] [blame] | 136 | int ToNumber(Register reg) { |
Ben Murdoch | b8a8cc1 | 2014-11-26 15:28:44 +0000 | [diff] [blame] | 137 | DCHECK(reg.is_valid()); |
Andrei Popescu | 3100271 | 2010-02-23 13:46:05 +0000 | [diff] [blame] | 138 | const int kNumbers[] = { |
| 139 | 0, // zero_reg |
| 140 | 1, // at |
| 141 | 2, // v0 |
| 142 | 3, // v1 |
| 143 | 4, // a0 |
| 144 | 5, // a1 |
| 145 | 6, // a2 |
| 146 | 7, // a3 |
| 147 | 8, // t0 |
| 148 | 9, // t1 |
| 149 | 10, // t2 |
| 150 | 11, // t3 |
| 151 | 12, // t4 |
| 152 | 13, // t5 |
| 153 | 14, // t6 |
| 154 | 15, // t7 |
| 155 | 16, // s0 |
| 156 | 17, // s1 |
| 157 | 18, // s2 |
| 158 | 19, // s3 |
| 159 | 20, // s4 |
| 160 | 21, // s5 |
| 161 | 22, // s6 |
| 162 | 23, // s7 |
| 163 | 24, // t8 |
| 164 | 25, // t9 |
| 165 | 26, // k0 |
| 166 | 27, // k1 |
| 167 | 28, // gp |
| 168 | 29, // sp |
Ben Murdoch | db1b438 | 2012-04-26 19:03:50 +0100 | [diff] [blame] | 169 | 30, // fp |
Andrei Popescu | 3100271 | 2010-02-23 13:46:05 +0000 | [diff] [blame] | 170 | 31, // ra |
| 171 | }; |
| 172 | return kNumbers[reg.code()]; |
| 173 | } |
| 174 | |
Steve Block | 44f0eee | 2011-05-26 01:26:41 +0100 | [diff] [blame] | 175 | |
Andrei Popescu | 3100271 | 2010-02-23 13:46:05 +0000 | [diff] [blame] | 176 | Register ToRegister(int num) { |
Ben Murdoch | b8a8cc1 | 2014-11-26 15:28:44 +0000 | [diff] [blame] | 177 | DCHECK(num >= 0 && num < kNumRegisters); |
Andrei Popescu | 3100271 | 2010-02-23 13:46:05 +0000 | [diff] [blame] | 178 | const Register kRegisters[] = { |
| 179 | zero_reg, |
| 180 | at, |
| 181 | v0, v1, |
| 182 | a0, a1, a2, a3, |
| 183 | t0, t1, t2, t3, t4, t5, t6, t7, |
| 184 | s0, s1, s2, s3, s4, s5, s6, s7, |
| 185 | t8, t9, |
| 186 | k0, k1, |
| 187 | gp, |
| 188 | sp, |
Ben Murdoch | db1b438 | 2012-04-26 19:03:50 +0100 | [diff] [blame] | 189 | fp, |
Andrei Popescu | 3100271 | 2010-02-23 13:46:05 +0000 | [diff] [blame] | 190 | ra |
| 191 | }; |
| 192 | return kRegisters[num]; |
| 193 | } |
| 194 | |
| 195 | |
| 196 | // ----------------------------------------------------------------------------- |
| 197 | // Implementation of RelocInfo. |
| 198 | |
Ben Murdoch | 589d697 | 2011-11-30 16:04:58 +0000 | [diff] [blame] | 199 | const int RelocInfo::kApplyMask = RelocInfo::kCodeTargetMask | |
| 200 | 1 << RelocInfo::INTERNAL_REFERENCE; |
Andrei Popescu | 3100271 | 2010-02-23 13:46:05 +0000 | [diff] [blame] | 201 | |
Steve Block | 44f0eee | 2011-05-26 01:26:41 +0100 | [diff] [blame] | 202 | |
| 203 | bool RelocInfo::IsCodedSpecially() { |
| 204 | // The deserializer needs to know whether a pointer is specially coded. Being |
| 205 | // specially coded on MIPS means that it is a lui/ori instruction, and that is |
| 206 | // always the case inside code objects. |
| 207 | return true; |
| 208 | } |
| 209 | |
| 210 | |
Ben Murdoch | b8a8cc1 | 2014-11-26 15:28:44 +0000 | [diff] [blame] | 211 | bool RelocInfo::IsInConstantPool() { |
| 212 | return false; |
| 213 | } |
| 214 | |
| 215 | |
Andrei Popescu | 3100271 | 2010-02-23 13:46:05 +0000 | [diff] [blame] | 216 | // Patch the code at the current address with the supplied instructions. |
| 217 | void RelocInfo::PatchCode(byte* instructions, int instruction_count) { |
| 218 | Instr* pc = reinterpret_cast<Instr*>(pc_); |
| 219 | Instr* instr = reinterpret_cast<Instr*>(instructions); |
| 220 | for (int i = 0; i < instruction_count; i++) { |
| 221 | *(pc + i) = *(instr + i); |
| 222 | } |
| 223 | |
| 224 | // Indicate that code has changed. |
Ben Murdoch | b8a8cc1 | 2014-11-26 15:28:44 +0000 | [diff] [blame] | 225 | CpuFeatures::FlushICache(pc_, instruction_count * Assembler::kInstrSize); |
Andrei Popescu | 3100271 | 2010-02-23 13:46:05 +0000 | [diff] [blame] | 226 | } |
| 227 | |
| 228 | |
| 229 | // Patch the code at the current PC with a call to the target address. |
| 230 | // Additional guard instructions can be added if required. |
| 231 | void RelocInfo::PatchCodeWithCall(Address target, int guard_bytes) { |
| 232 | // Patch the code at the current address with a call to the target. |
| 233 | UNIMPLEMENTED_MIPS(); |
| 234 | } |
| 235 | |
| 236 | |
| 237 | // ----------------------------------------------------------------------------- |
| 238 | // Implementation of Operand and MemOperand. |
| 239 | // See assembler-mips-inl.h for inlined constructors. |
| 240 | |
| 241 | Operand::Operand(Handle<Object> handle) { |
Ben Murdoch | b8a8cc1 | 2014-11-26 15:28:44 +0000 | [diff] [blame] | 242 | AllowDeferredHandleDereference using_raw_address; |
Andrei Popescu | 3100271 | 2010-02-23 13:46:05 +0000 | [diff] [blame] | 243 | rm_ = no_reg; |
| 244 | // Verify all Objects referred by code are NOT in new space. |
| 245 | Object* obj = *handle; |
Andrei Popescu | 3100271 | 2010-02-23 13:46:05 +0000 | [diff] [blame] | 246 | if (obj->IsHeapObject()) { |
Ben Murdoch | b8a8cc1 | 2014-11-26 15:28:44 +0000 | [diff] [blame] | 247 | DCHECK(!HeapObject::cast(obj)->GetHeap()->InNewSpace(obj)); |
Andrei Popescu | 3100271 | 2010-02-23 13:46:05 +0000 | [diff] [blame] | 248 | imm32_ = reinterpret_cast<intptr_t>(handle.location()); |
| 249 | rmode_ = RelocInfo::EMBEDDED_OBJECT; |
| 250 | } else { |
| 251 | // No relocation needed. |
| 252 | imm32_ = reinterpret_cast<intptr_t>(obj); |
Ben Murdoch | b8a8cc1 | 2014-11-26 15:28:44 +0000 | [diff] [blame] | 253 | rmode_ = RelocInfo::NONE32; |
Andrei Popescu | 3100271 | 2010-02-23 13:46:05 +0000 | [diff] [blame] | 254 | } |
| 255 | } |
| 256 | |
Steve Block | 44f0eee | 2011-05-26 01:26:41 +0100 | [diff] [blame] | 257 | |
| 258 | MemOperand::MemOperand(Register rm, int32_t offset) : Operand(rm) { |
Andrei Popescu | 3100271 | 2010-02-23 13:46:05 +0000 | [diff] [blame] | 259 | offset_ = offset; |
| 260 | } |
| 261 | |
| 262 | |
Ben Murdoch | b8a8cc1 | 2014-11-26 15:28:44 +0000 | [diff] [blame] | 263 | MemOperand::MemOperand(Register rm, int32_t unit, int32_t multiplier, |
| 264 | OffsetAddend offset_addend) : Operand(rm) { |
| 265 | offset_ = unit * multiplier + offset_addend; |
| 266 | } |
| 267 | |
| 268 | |
Andrei Popescu | 3100271 | 2010-02-23 13:46:05 +0000 | [diff] [blame] | 269 | // ----------------------------------------------------------------------------- |
Steve Block | 44f0eee | 2011-05-26 01:26:41 +0100 | [diff] [blame] | 270 | // Specific instructions, constants, and masks. |
Andrei Popescu | 3100271 | 2010-02-23 13:46:05 +0000 | [diff] [blame] | 271 | |
Steve Block | 44f0eee | 2011-05-26 01:26:41 +0100 | [diff] [blame] | 272 | static const int kNegOffset = 0x00008000; |
| 273 | // addiu(sp, sp, 4) aka Pop() operation or part of Pop(r) |
| 274 | // operations as post-increment of sp. |
Ben Murdoch | db1b438 | 2012-04-26 19:03:50 +0100 | [diff] [blame] | 275 | const Instr kPopInstruction = ADDIU | (kRegister_sp_Code << kRsShift) |
Ben Murdoch | b8a8cc1 | 2014-11-26 15:28:44 +0000 | [diff] [blame] | 276 | | (kRegister_sp_Code << kRtShift) |
| 277 | | (kPointerSize & kImm16Mask); // NOLINT |
Steve Block | 44f0eee | 2011-05-26 01:26:41 +0100 | [diff] [blame] | 278 | // addiu(sp, sp, -4) part of Push(r) operation as pre-decrement of sp. |
Ben Murdoch | db1b438 | 2012-04-26 19:03:50 +0100 | [diff] [blame] | 279 | const Instr kPushInstruction = ADDIU | (kRegister_sp_Code << kRsShift) |
Ben Murdoch | b8a8cc1 | 2014-11-26 15:28:44 +0000 | [diff] [blame] | 280 | | (kRegister_sp_Code << kRtShift) |
| 281 | | (-kPointerSize & kImm16Mask); // NOLINT |
Steve Block | 44f0eee | 2011-05-26 01:26:41 +0100 | [diff] [blame] | 282 | // sw(r, MemOperand(sp, 0)) |
Ben Murdoch | db1b438 | 2012-04-26 19:03:50 +0100 | [diff] [blame] | 283 | const Instr kPushRegPattern = SW | (kRegister_sp_Code << kRsShift) |
Ben Murdoch | b8a8cc1 | 2014-11-26 15:28:44 +0000 | [diff] [blame] | 284 | | (0 & kImm16Mask); // NOLINT |
Steve Block | 44f0eee | 2011-05-26 01:26:41 +0100 | [diff] [blame] | 285 | // lw(r, MemOperand(sp, 0)) |
Ben Murdoch | db1b438 | 2012-04-26 19:03:50 +0100 | [diff] [blame] | 286 | const Instr kPopRegPattern = LW | (kRegister_sp_Code << kRsShift) |
Ben Murdoch | b8a8cc1 | 2014-11-26 15:28:44 +0000 | [diff] [blame] | 287 | | (0 & kImm16Mask); // NOLINT |
Andrei Popescu | 3100271 | 2010-02-23 13:46:05 +0000 | [diff] [blame] | 288 | |
Ben Murdoch | db1b438 | 2012-04-26 19:03:50 +0100 | [diff] [blame] | 289 | const Instr kLwRegFpOffsetPattern = LW | (kRegister_fp_Code << kRsShift) |
Ben Murdoch | b8a8cc1 | 2014-11-26 15:28:44 +0000 | [diff] [blame] | 290 | | (0 & kImm16Mask); // NOLINT |
Steve Block | 44f0eee | 2011-05-26 01:26:41 +0100 | [diff] [blame] | 291 | |
Ben Murdoch | db1b438 | 2012-04-26 19:03:50 +0100 | [diff] [blame] | 292 | const Instr kSwRegFpOffsetPattern = SW | (kRegister_fp_Code << kRsShift) |
Ben Murdoch | b8a8cc1 | 2014-11-26 15:28:44 +0000 | [diff] [blame] | 293 | | (0 & kImm16Mask); // NOLINT |
Steve Block | 44f0eee | 2011-05-26 01:26:41 +0100 | [diff] [blame] | 294 | |
Ben Murdoch | db1b438 | 2012-04-26 19:03:50 +0100 | [diff] [blame] | 295 | const Instr kLwRegFpNegOffsetPattern = LW | (kRegister_fp_Code << kRsShift) |
Ben Murdoch | b8a8cc1 | 2014-11-26 15:28:44 +0000 | [diff] [blame] | 296 | | (kNegOffset & kImm16Mask); // NOLINT |
Steve Block | 44f0eee | 2011-05-26 01:26:41 +0100 | [diff] [blame] | 297 | |
Ben Murdoch | db1b438 | 2012-04-26 19:03:50 +0100 | [diff] [blame] | 298 | const Instr kSwRegFpNegOffsetPattern = SW | (kRegister_fp_Code << kRsShift) |
Ben Murdoch | b8a8cc1 | 2014-11-26 15:28:44 +0000 | [diff] [blame] | 299 | | (kNegOffset & kImm16Mask); // NOLINT |
Steve Block | 44f0eee | 2011-05-26 01:26:41 +0100 | [diff] [blame] | 300 | // A mask for the Rt register for push, pop, lw, sw instructions. |
| 301 | const Instr kRtMask = kRtFieldMask; |
| 302 | const Instr kLwSwInstrTypeMask = 0xffe00000; |
| 303 | const Instr kLwSwInstrArgumentMask = ~kLwSwInstrTypeMask; |
| 304 | const Instr kLwSwOffsetMask = kImm16Mask; |
| 305 | |
| 306 | |
Ben Murdoch | b8a8cc1 | 2014-11-26 15:28:44 +0000 | [diff] [blame] | 307 | Assembler::Assembler(Isolate* isolate, void* buffer, int buffer_size) |
| 308 | : AssemblerBase(isolate, buffer, buffer_size), |
| 309 | recorded_ast_id_(TypeFeedbackId::None()), |
| 310 | positions_recorder_(this) { |
| 311 | reloc_info_writer.Reposition(buffer_ + buffer_size_, pc_); |
Steve Block | 44f0eee | 2011-05-26 01:26:41 +0100 | [diff] [blame] | 312 | |
| 313 | last_trampoline_pool_end_ = 0; |
| 314 | no_trampoline_pool_before_ = 0; |
| 315 | trampoline_pool_blocked_nesting_ = 0; |
Ben Murdoch | 3fb3ca8 | 2011-12-02 17:19:32 +0000 | [diff] [blame] | 316 | // We leave space (16 * kTrampolineSlotsSize) |
| 317 | // for BlockTrampolinePoolScope buffer. |
Ben Murdoch | b8a8cc1 | 2014-11-26 15:28:44 +0000 | [diff] [blame] | 318 | next_buffer_check_ = FLAG_force_long_branches |
| 319 | ? kMaxInt : kMaxBranchOffset - kTrampolineSlotsSize * 16; |
Ben Murdoch | 257744e | 2011-11-30 15:57:28 +0000 | [diff] [blame] | 320 | internal_trampoline_exception_ = false; |
| 321 | last_bound_pos_ = 0; |
| 322 | |
Ben Murdoch | b8a8cc1 | 2014-11-26 15:28:44 +0000 | [diff] [blame] | 323 | trampoline_emitted_ = FLAG_force_long_branches; |
Ben Murdoch | 3fb3ca8 | 2011-12-02 17:19:32 +0000 | [diff] [blame] | 324 | unbound_labels_count_ = 0; |
| 325 | block_buffer_growth_ = false; |
| 326 | |
| 327 | ClearRecordedAstId(); |
Andrei Popescu | 3100271 | 2010-02-23 13:46:05 +0000 | [diff] [blame] | 328 | } |
| 329 | |
| 330 | |
Andrei Popescu | 3100271 | 2010-02-23 13:46:05 +0000 | [diff] [blame] | 331 | void Assembler::GetCode(CodeDesc* desc) { |
Ben Murdoch | b8a8cc1 | 2014-11-26 15:28:44 +0000 | [diff] [blame] | 332 | DCHECK(pc_ <= reloc_info_writer.pos()); // No overlap. |
Ben Murdoch | 3ef787d | 2012-04-12 10:51:47 +0100 | [diff] [blame] | 333 | // Set up code descriptor. |
Andrei Popescu | 3100271 | 2010-02-23 13:46:05 +0000 | [diff] [blame] | 334 | desc->buffer = buffer_; |
| 335 | desc->buffer_size = buffer_size_; |
| 336 | desc->instr_size = pc_offset(); |
| 337 | desc->reloc_size = (buffer_ + buffer_size_) - reloc_info_writer.pos(); |
Ben Murdoch | b8a8cc1 | 2014-11-26 15:28:44 +0000 | [diff] [blame] | 338 | desc->origin = this; |
Andrei Popescu | 3100271 | 2010-02-23 13:46:05 +0000 | [diff] [blame] | 339 | } |
| 340 | |
| 341 | |
Steve Block | 44f0eee | 2011-05-26 01:26:41 +0100 | [diff] [blame] | 342 | void Assembler::Align(int m) { |
Ben Murdoch | b8a8cc1 | 2014-11-26 15:28:44 +0000 | [diff] [blame] | 343 | DCHECK(m >= 4 && base::bits::IsPowerOfTwo32(m)); |
Steve Block | 44f0eee | 2011-05-26 01:26:41 +0100 | [diff] [blame] | 344 | while ((pc_offset() & (m - 1)) != 0) { |
| 345 | nop(); |
| 346 | } |
| 347 | } |
| 348 | |
| 349 | |
| 350 | void Assembler::CodeTargetAlign() { |
| 351 | // No advantage to aligning branch/call targets to more than |
| 352 | // single instruction, that I am aware of. |
| 353 | Align(4); |
| 354 | } |
| 355 | |
| 356 | |
Ben Murdoch | 257744e | 2011-11-30 15:57:28 +0000 | [diff] [blame] | 357 | Register Assembler::GetRtReg(Instr instr) { |
Steve Block | 44f0eee | 2011-05-26 01:26:41 +0100 | [diff] [blame] | 358 | Register rt; |
Ben Murdoch | 257744e | 2011-11-30 15:57:28 +0000 | [diff] [blame] | 359 | rt.code_ = (instr & kRtFieldMask) >> kRtShift; |
Steve Block | 44f0eee | 2011-05-26 01:26:41 +0100 | [diff] [blame] | 360 | return rt; |
| 361 | } |
| 362 | |
| 363 | |
Ben Murdoch | 257744e | 2011-11-30 15:57:28 +0000 | [diff] [blame] | 364 | Register Assembler::GetRsReg(Instr instr) { |
| 365 | Register rs; |
| 366 | rs.code_ = (instr & kRsFieldMask) >> kRsShift; |
| 367 | return rs; |
| 368 | } |
| 369 | |
| 370 | |
| 371 | Register Assembler::GetRdReg(Instr instr) { |
| 372 | Register rd; |
| 373 | rd.code_ = (instr & kRdFieldMask) >> kRdShift; |
| 374 | return rd; |
| 375 | } |
| 376 | |
| 377 | |
| 378 | uint32_t Assembler::GetRt(Instr instr) { |
| 379 | return (instr & kRtFieldMask) >> kRtShift; |
| 380 | } |
| 381 | |
| 382 | |
| 383 | uint32_t Assembler::GetRtField(Instr instr) { |
| 384 | return instr & kRtFieldMask; |
| 385 | } |
| 386 | |
| 387 | |
| 388 | uint32_t Assembler::GetRs(Instr instr) { |
| 389 | return (instr & kRsFieldMask) >> kRsShift; |
| 390 | } |
| 391 | |
| 392 | |
| 393 | uint32_t Assembler::GetRsField(Instr instr) { |
| 394 | return instr & kRsFieldMask; |
| 395 | } |
| 396 | |
| 397 | |
| 398 | uint32_t Assembler::GetRd(Instr instr) { |
| 399 | return (instr & kRdFieldMask) >> kRdShift; |
| 400 | } |
| 401 | |
| 402 | |
| 403 | uint32_t Assembler::GetRdField(Instr instr) { |
| 404 | return instr & kRdFieldMask; |
| 405 | } |
| 406 | |
| 407 | |
| 408 | uint32_t Assembler::GetSa(Instr instr) { |
| 409 | return (instr & kSaFieldMask) >> kSaShift; |
| 410 | } |
| 411 | |
| 412 | |
| 413 | uint32_t Assembler::GetSaField(Instr instr) { |
| 414 | return instr & kSaFieldMask; |
| 415 | } |
| 416 | |
| 417 | |
| 418 | uint32_t Assembler::GetOpcodeField(Instr instr) { |
| 419 | return instr & kOpcodeMask; |
| 420 | } |
| 421 | |
| 422 | |
Ben Murdoch | 3fb3ca8 | 2011-12-02 17:19:32 +0000 | [diff] [blame] | 423 | uint32_t Assembler::GetFunction(Instr instr) { |
| 424 | return (instr & kFunctionFieldMask) >> kFunctionShift; |
| 425 | } |
| 426 | |
| 427 | |
| 428 | uint32_t Assembler::GetFunctionField(Instr instr) { |
| 429 | return instr & kFunctionFieldMask; |
| 430 | } |
| 431 | |
| 432 | |
Ben Murdoch | 257744e | 2011-11-30 15:57:28 +0000 | [diff] [blame] | 433 | uint32_t Assembler::GetImmediate16(Instr instr) { |
| 434 | return instr & kImm16Mask; |
| 435 | } |
| 436 | |
| 437 | |
| 438 | uint32_t Assembler::GetLabelConst(Instr instr) { |
| 439 | return instr & ~kImm16Mask; |
| 440 | } |
| 441 | |
| 442 | |
Steve Block | 44f0eee | 2011-05-26 01:26:41 +0100 | [diff] [blame] | 443 | bool Assembler::IsPop(Instr instr) { |
| 444 | return (instr & ~kRtMask) == kPopRegPattern; |
| 445 | } |
| 446 | |
| 447 | |
| 448 | bool Assembler::IsPush(Instr instr) { |
| 449 | return (instr & ~kRtMask) == kPushRegPattern; |
| 450 | } |
| 451 | |
| 452 | |
| 453 | bool Assembler::IsSwRegFpOffset(Instr instr) { |
| 454 | return ((instr & kLwSwInstrTypeMask) == kSwRegFpOffsetPattern); |
| 455 | } |
| 456 | |
| 457 | |
| 458 | bool Assembler::IsLwRegFpOffset(Instr instr) { |
| 459 | return ((instr & kLwSwInstrTypeMask) == kLwRegFpOffsetPattern); |
| 460 | } |
| 461 | |
| 462 | |
| 463 | bool Assembler::IsSwRegFpNegOffset(Instr instr) { |
| 464 | return ((instr & (kLwSwInstrTypeMask | kNegOffset)) == |
| 465 | kSwRegFpNegOffsetPattern); |
| 466 | } |
| 467 | |
| 468 | |
| 469 | bool Assembler::IsLwRegFpNegOffset(Instr instr) { |
| 470 | return ((instr & (kLwSwInstrTypeMask | kNegOffset)) == |
| 471 | kLwRegFpNegOffsetPattern); |
| 472 | } |
| 473 | |
| 474 | |
Andrei Popescu | 3100271 | 2010-02-23 13:46:05 +0000 | [diff] [blame] | 475 | // Labels refer to positions in the (to be) generated code. |
| 476 | // There are bound, linked, and unused labels. |
| 477 | // |
| 478 | // Bound labels refer to known positions in the already |
| 479 | // generated code. pos() is the position the label refers to. |
| 480 | // |
| 481 | // Linked labels refer to unknown positions in the code |
| 482 | // to be generated; pos() is the position of the last |
| 483 | // instruction using the label. |
| 484 | |
Steve Block | 44f0eee | 2011-05-26 01:26:41 +0100 | [diff] [blame] | 485 | // The link chain is terminated by a value in the instruction of -1, |
| 486 | // which is an otherwise illegal value (branch -1 is inf loop). |
| 487 | // The instruction 16-bit offset field addresses 32-bit words, but in |
| 488 | // code is conv to an 18-bit value addressing bytes, hence the -4 value. |
Andrei Popescu | 3100271 | 2010-02-23 13:46:05 +0000 | [diff] [blame] | 489 | |
Andrei Popescu | 3100271 | 2010-02-23 13:46:05 +0000 | [diff] [blame] | 490 | const int kEndOfChain = -4; |
Ben Murdoch | 3fb3ca8 | 2011-12-02 17:19:32 +0000 | [diff] [blame] | 491 | // Determines the end of the Jump chain (a subset of the label link chain). |
| 492 | const int kEndOfJumpChain = 0; |
Andrei Popescu | 3100271 | 2010-02-23 13:46:05 +0000 | [diff] [blame] | 493 | |
Steve Block | 44f0eee | 2011-05-26 01:26:41 +0100 | [diff] [blame] | 494 | |
| 495 | bool Assembler::IsBranch(Instr instr) { |
Ben Murdoch | 257744e | 2011-11-30 15:57:28 +0000 | [diff] [blame] | 496 | uint32_t opcode = GetOpcodeField(instr); |
| 497 | uint32_t rt_field = GetRtField(instr); |
| 498 | uint32_t rs_field = GetRsField(instr); |
Andrei Popescu | 3100271 | 2010-02-23 13:46:05 +0000 | [diff] [blame] | 499 | // Checks if the instruction is a branch. |
| 500 | return opcode == BEQ || |
| 501 | opcode == BNE || |
| 502 | opcode == BLEZ || |
| 503 | opcode == BGTZ || |
| 504 | opcode == BEQL || |
| 505 | opcode == BNEL || |
| 506 | opcode == BLEZL || |
Ben Murdoch | 257744e | 2011-11-30 15:57:28 +0000 | [diff] [blame] | 507 | opcode == BGTZL || |
Andrei Popescu | 3100271 | 2010-02-23 13:46:05 +0000 | [diff] [blame] | 508 | (opcode == REGIMM && (rt_field == BLTZ || rt_field == BGEZ || |
| 509 | rt_field == BLTZAL || rt_field == BGEZAL)) || |
Steve Block | 44f0eee | 2011-05-26 01:26:41 +0100 | [diff] [blame] | 510 | (opcode == COP1 && rs_field == BC1) || // Coprocessor branch. |
Ben Murdoch | b8a8cc1 | 2014-11-26 15:28:44 +0000 | [diff] [blame] | 511 | (opcode == COP1 && rs_field == BC1EQZ) || |
| 512 | (opcode == COP1 && rs_field == BC1NEZ); |
| 513 | } |
| 514 | |
| 515 | |
| 516 | bool Assembler::IsEmittedConstant(Instr instr) { |
| 517 | uint32_t label_constant = GetLabelConst(instr); |
| 518 | return label_constant == 0; // Emitted label const in reg-exp engine. |
Steve Block | 44f0eee | 2011-05-26 01:26:41 +0100 | [diff] [blame] | 519 | } |
| 520 | |
| 521 | |
Ben Murdoch | 257744e | 2011-11-30 15:57:28 +0000 | [diff] [blame] | 522 | bool Assembler::IsBeq(Instr instr) { |
| 523 | return GetOpcodeField(instr) == BEQ; |
| 524 | } |
| 525 | |
| 526 | |
| 527 | bool Assembler::IsBne(Instr instr) { |
| 528 | return GetOpcodeField(instr) == BNE; |
| 529 | } |
| 530 | |
| 531 | |
Ben Murdoch | 3fb3ca8 | 2011-12-02 17:19:32 +0000 | [diff] [blame] | 532 | bool Assembler::IsJump(Instr instr) { |
| 533 | uint32_t opcode = GetOpcodeField(instr); |
| 534 | uint32_t rt_field = GetRtField(instr); |
| 535 | uint32_t rd_field = GetRdField(instr); |
| 536 | uint32_t function_field = GetFunctionField(instr); |
| 537 | // Checks if the instruction is a jump. |
| 538 | return opcode == J || opcode == JAL || |
| 539 | (opcode == SPECIAL && rt_field == 0 && |
| 540 | ((function_field == JALR) || (rd_field == 0 && (function_field == JR)))); |
| 541 | } |
| 542 | |
| 543 | |
| 544 | bool Assembler::IsJ(Instr instr) { |
| 545 | uint32_t opcode = GetOpcodeField(instr); |
| 546 | // Checks if the instruction is a jump. |
| 547 | return opcode == J; |
| 548 | } |
| 549 | |
| 550 | |
Ben Murdoch | 589d697 | 2011-11-30 16:04:58 +0000 | [diff] [blame] | 551 | bool Assembler::IsJal(Instr instr) { |
| 552 | return GetOpcodeField(instr) == JAL; |
| 553 | } |
| 554 | |
Ben Murdoch | b8a8cc1 | 2014-11-26 15:28:44 +0000 | [diff] [blame] | 555 | |
Ben Murdoch | 589d697 | 2011-11-30 16:04:58 +0000 | [diff] [blame] | 556 | bool Assembler::IsJr(Instr instr) { |
Ben Murdoch | b8a8cc1 | 2014-11-26 15:28:44 +0000 | [diff] [blame] | 557 | if (!IsMipsArchVariant(kMips32r6)) { |
| 558 | return GetOpcodeField(instr) == SPECIAL && GetFunctionField(instr) == JR; |
| 559 | } else { |
| 560 | return GetOpcodeField(instr) == SPECIAL && |
| 561 | GetRdField(instr) == 0 && GetFunctionField(instr) == JALR; |
| 562 | } |
Ben Murdoch | 589d697 | 2011-11-30 16:04:58 +0000 | [diff] [blame] | 563 | } |
| 564 | |
Ben Murdoch | b8a8cc1 | 2014-11-26 15:28:44 +0000 | [diff] [blame] | 565 | |
Ben Murdoch | 589d697 | 2011-11-30 16:04:58 +0000 | [diff] [blame] | 566 | bool Assembler::IsJalr(Instr instr) { |
Ben Murdoch | b8a8cc1 | 2014-11-26 15:28:44 +0000 | [diff] [blame] | 567 | return GetOpcodeField(instr) == SPECIAL && |
| 568 | GetRdField(instr) != 0 && GetFunctionField(instr) == JALR; |
Ben Murdoch | 589d697 | 2011-11-30 16:04:58 +0000 | [diff] [blame] | 569 | } |
| 570 | |
| 571 | |
Ben Murdoch | 3fb3ca8 | 2011-12-02 17:19:32 +0000 | [diff] [blame] | 572 | bool Assembler::IsLui(Instr instr) { |
| 573 | uint32_t opcode = GetOpcodeField(instr); |
| 574 | // Checks if the instruction is a load upper immediate. |
| 575 | return opcode == LUI; |
| 576 | } |
| 577 | |
| 578 | |
| 579 | bool Assembler::IsOri(Instr instr) { |
| 580 | uint32_t opcode = GetOpcodeField(instr); |
| 581 | // Checks if the instruction is a load upper immediate. |
| 582 | return opcode == ORI; |
| 583 | } |
| 584 | |
| 585 | |
Steve Block | 44f0eee | 2011-05-26 01:26:41 +0100 | [diff] [blame] | 586 | bool Assembler::IsNop(Instr instr, unsigned int type) { |
| 587 | // See Assembler::nop(type). |
Ben Murdoch | b8a8cc1 | 2014-11-26 15:28:44 +0000 | [diff] [blame] | 588 | DCHECK(type < 32); |
Ben Murdoch | 257744e | 2011-11-30 15:57:28 +0000 | [diff] [blame] | 589 | uint32_t opcode = GetOpcodeField(instr); |
Ben Murdoch | b8a8cc1 | 2014-11-26 15:28:44 +0000 | [diff] [blame] | 590 | uint32_t function = GetFunctionField(instr); |
Ben Murdoch | 257744e | 2011-11-30 15:57:28 +0000 | [diff] [blame] | 591 | uint32_t rt = GetRt(instr); |
Ben Murdoch | b8a8cc1 | 2014-11-26 15:28:44 +0000 | [diff] [blame] | 592 | uint32_t rd = GetRd(instr); |
Ben Murdoch | 257744e | 2011-11-30 15:57:28 +0000 | [diff] [blame] | 593 | uint32_t sa = GetSa(instr); |
Steve Block | 44f0eee | 2011-05-26 01:26:41 +0100 | [diff] [blame] | 594 | |
Ben Murdoch | b8a8cc1 | 2014-11-26 15:28:44 +0000 | [diff] [blame] | 595 | // Traditional mips nop == sll(zero_reg, zero_reg, 0) |
| 596 | // When marking non-zero type, use sll(zero_reg, at, type) |
| 597 | // to avoid use of mips ssnop and ehb special encodings |
| 598 | // of the sll instruction. |
Steve Block | 44f0eee | 2011-05-26 01:26:41 +0100 | [diff] [blame] | 599 | |
Ben Murdoch | b8a8cc1 | 2014-11-26 15:28:44 +0000 | [diff] [blame] | 600 | Register nop_rt_reg = (type == 0) ? zero_reg : at; |
| 601 | bool ret = (opcode == SPECIAL && function == SLL && |
| 602 | rd == static_cast<uint32_t>(ToNumber(zero_reg)) && |
| 603 | rt == static_cast<uint32_t>(ToNumber(nop_rt_reg)) && |
Steve Block | 44f0eee | 2011-05-26 01:26:41 +0100 | [diff] [blame] | 604 | sa == type); |
| 605 | |
| 606 | return ret; |
| 607 | } |
| 608 | |
| 609 | |
| 610 | int32_t Assembler::GetBranchOffset(Instr instr) { |
Ben Murdoch | b8a8cc1 | 2014-11-26 15:28:44 +0000 | [diff] [blame] | 611 | DCHECK(IsBranch(instr)); |
| 612 | return (static_cast<int16_t>(instr & kImm16Mask)) << 2; |
Steve Block | 44f0eee | 2011-05-26 01:26:41 +0100 | [diff] [blame] | 613 | } |
| 614 | |
| 615 | |
| 616 | bool Assembler::IsLw(Instr instr) { |
| 617 | return ((instr & kOpcodeMask) == LW); |
| 618 | } |
| 619 | |
| 620 | |
| 621 | int16_t Assembler::GetLwOffset(Instr instr) { |
Ben Murdoch | b8a8cc1 | 2014-11-26 15:28:44 +0000 | [diff] [blame] | 622 | DCHECK(IsLw(instr)); |
Steve Block | 44f0eee | 2011-05-26 01:26:41 +0100 | [diff] [blame] | 623 | return ((instr & kImm16Mask)); |
| 624 | } |
| 625 | |
| 626 | |
| 627 | Instr Assembler::SetLwOffset(Instr instr, int16_t offset) { |
Ben Murdoch | b8a8cc1 | 2014-11-26 15:28:44 +0000 | [diff] [blame] | 628 | DCHECK(IsLw(instr)); |
Steve Block | 44f0eee | 2011-05-26 01:26:41 +0100 | [diff] [blame] | 629 | |
| 630 | // We actually create a new lw instruction based on the original one. |
| 631 | Instr temp_instr = LW | (instr & kRsFieldMask) | (instr & kRtFieldMask) |
| 632 | | (offset & kImm16Mask); |
| 633 | |
| 634 | return temp_instr; |
| 635 | } |
| 636 | |
| 637 | |
| 638 | bool Assembler::IsSw(Instr instr) { |
| 639 | return ((instr & kOpcodeMask) == SW); |
| 640 | } |
| 641 | |
| 642 | |
| 643 | Instr Assembler::SetSwOffset(Instr instr, int16_t offset) { |
Ben Murdoch | b8a8cc1 | 2014-11-26 15:28:44 +0000 | [diff] [blame] | 644 | DCHECK(IsSw(instr)); |
Steve Block | 44f0eee | 2011-05-26 01:26:41 +0100 | [diff] [blame] | 645 | return ((instr & ~kImm16Mask) | (offset & kImm16Mask)); |
| 646 | } |
| 647 | |
| 648 | |
| 649 | bool Assembler::IsAddImmediate(Instr instr) { |
| 650 | return ((instr & kOpcodeMask) == ADDIU); |
| 651 | } |
| 652 | |
| 653 | |
| 654 | Instr Assembler::SetAddImmediateOffset(Instr instr, int16_t offset) { |
Ben Murdoch | b8a8cc1 | 2014-11-26 15:28:44 +0000 | [diff] [blame] | 655 | DCHECK(IsAddImmediate(instr)); |
Steve Block | 44f0eee | 2011-05-26 01:26:41 +0100 | [diff] [blame] | 656 | return ((instr & ~kImm16Mask) | (offset & kImm16Mask)); |
Andrei Popescu | 3100271 | 2010-02-23 13:46:05 +0000 | [diff] [blame] | 657 | } |
| 658 | |
| 659 | |
Ben Murdoch | 257744e | 2011-11-30 15:57:28 +0000 | [diff] [blame] | 660 | bool Assembler::IsAndImmediate(Instr instr) { |
| 661 | return GetOpcodeField(instr) == ANDI; |
| 662 | } |
| 663 | |
| 664 | |
Andrei Popescu | 3100271 | 2010-02-23 13:46:05 +0000 | [diff] [blame] | 665 | int Assembler::target_at(int32_t pos) { |
| 666 | Instr instr = instr_at(pos); |
| 667 | if ((instr & ~kImm16Mask) == 0) { |
| 668 | // Emitted label constant, not part of a branch. |
Steve Block | 44f0eee | 2011-05-26 01:26:41 +0100 | [diff] [blame] | 669 | if (instr == 0) { |
| 670 | return kEndOfChain; |
| 671 | } else { |
| 672 | int32_t imm18 =((instr & static_cast<int32_t>(kImm16Mask)) << 16) >> 14; |
| 673 | return (imm18 + pos); |
| 674 | } |
Andrei Popescu | 3100271 | 2010-02-23 13:46:05 +0000 | [diff] [blame] | 675 | } |
Ben Murdoch | 3fb3ca8 | 2011-12-02 17:19:32 +0000 | [diff] [blame] | 676 | // Check we have a branch or jump instruction. |
Ben Murdoch | b8a8cc1 | 2014-11-26 15:28:44 +0000 | [diff] [blame] | 677 | DCHECK(IsBranch(instr) || IsJ(instr) || IsLui(instr)); |
Andrei Popescu | 3100271 | 2010-02-23 13:46:05 +0000 | [diff] [blame] | 678 | // Do NOT change this to <<2. We rely on arithmetic shifts here, assuming |
| 679 | // the compiler uses arithmectic shifts for signed integers. |
Ben Murdoch | 3fb3ca8 | 2011-12-02 17:19:32 +0000 | [diff] [blame] | 680 | if (IsBranch(instr)) { |
| 681 | int32_t imm18 = ((instr & static_cast<int32_t>(kImm16Mask)) << 16) >> 14; |
Andrei Popescu | 3100271 | 2010-02-23 13:46:05 +0000 | [diff] [blame] | 682 | |
Ben Murdoch | 3fb3ca8 | 2011-12-02 17:19:32 +0000 | [diff] [blame] | 683 | if (imm18 == kEndOfChain) { |
| 684 | // EndOfChain sentinel is returned directly, not relative to pc or pos. |
| 685 | return kEndOfChain; |
| 686 | } else { |
| 687 | return pos + kBranchPCOffset + imm18; |
| 688 | } |
| 689 | } else if (IsLui(instr)) { |
| 690 | Instr instr_lui = instr_at(pos + 0 * Assembler::kInstrSize); |
| 691 | Instr instr_ori = instr_at(pos + 1 * Assembler::kInstrSize); |
Ben Murdoch | b8a8cc1 | 2014-11-26 15:28:44 +0000 | [diff] [blame] | 692 | DCHECK(IsOri(instr_ori)); |
Ben Murdoch | 3fb3ca8 | 2011-12-02 17:19:32 +0000 | [diff] [blame] | 693 | int32_t imm = (instr_lui & static_cast<int32_t>(kImm16Mask)) << kLuiShift; |
| 694 | imm |= (instr_ori & static_cast<int32_t>(kImm16Mask)); |
| 695 | |
| 696 | if (imm == kEndOfJumpChain) { |
| 697 | // EndOfChain sentinel is returned directly, not relative to pc or pos. |
| 698 | return kEndOfChain; |
| 699 | } else { |
| 700 | uint32_t instr_address = reinterpret_cast<int32_t>(buffer_ + pos); |
| 701 | int32_t delta = instr_address - imm; |
Ben Murdoch | b8a8cc1 | 2014-11-26 15:28:44 +0000 | [diff] [blame] | 702 | DCHECK(pos > delta); |
Ben Murdoch | 3fb3ca8 | 2011-12-02 17:19:32 +0000 | [diff] [blame] | 703 | return pos - delta; |
| 704 | } |
Steve Block | 44f0eee | 2011-05-26 01:26:41 +0100 | [diff] [blame] | 705 | } else { |
Ben Murdoch | 3fb3ca8 | 2011-12-02 17:19:32 +0000 | [diff] [blame] | 706 | int32_t imm28 = (instr & static_cast<int32_t>(kImm26Mask)) << 2; |
| 707 | if (imm28 == kEndOfJumpChain) { |
| 708 | // EndOfChain sentinel is returned directly, not relative to pc or pos. |
| 709 | return kEndOfChain; |
| 710 | } else { |
| 711 | uint32_t instr_address = reinterpret_cast<int32_t>(buffer_ + pos); |
| 712 | instr_address &= kImm28Mask; |
| 713 | int32_t delta = instr_address - imm28; |
Ben Murdoch | b8a8cc1 | 2014-11-26 15:28:44 +0000 | [diff] [blame] | 714 | DCHECK(pos > delta); |
Ben Murdoch | 3fb3ca8 | 2011-12-02 17:19:32 +0000 | [diff] [blame] | 715 | return pos - delta; |
| 716 | } |
Steve Block | 44f0eee | 2011-05-26 01:26:41 +0100 | [diff] [blame] | 717 | } |
Andrei Popescu | 3100271 | 2010-02-23 13:46:05 +0000 | [diff] [blame] | 718 | } |
| 719 | |
| 720 | |
| 721 | void Assembler::target_at_put(int32_t pos, int32_t target_pos) { |
| 722 | Instr instr = instr_at(pos); |
| 723 | if ((instr & ~kImm16Mask) == 0) { |
Ben Murdoch | b8a8cc1 | 2014-11-26 15:28:44 +0000 | [diff] [blame] | 724 | DCHECK(target_pos == kEndOfChain || target_pos >= 0); |
Andrei Popescu | 3100271 | 2010-02-23 13:46:05 +0000 | [diff] [blame] | 725 | // Emitted label constant, not part of a branch. |
| 726 | // Make label relative to Code* of generated Code object. |
| 727 | instr_at_put(pos, target_pos + (Code::kHeaderSize - kHeapObjectTag)); |
| 728 | return; |
| 729 | } |
| 730 | |
Ben Murdoch | b8a8cc1 | 2014-11-26 15:28:44 +0000 | [diff] [blame] | 731 | DCHECK(IsBranch(instr) || IsJ(instr) || IsLui(instr)); |
Ben Murdoch | 3fb3ca8 | 2011-12-02 17:19:32 +0000 | [diff] [blame] | 732 | if (IsBranch(instr)) { |
| 733 | int32_t imm18 = target_pos - (pos + kBranchPCOffset); |
Ben Murdoch | b8a8cc1 | 2014-11-26 15:28:44 +0000 | [diff] [blame] | 734 | DCHECK((imm18 & 3) == 0); |
Andrei Popescu | 3100271 | 2010-02-23 13:46:05 +0000 | [diff] [blame] | 735 | |
Ben Murdoch | 3fb3ca8 | 2011-12-02 17:19:32 +0000 | [diff] [blame] | 736 | instr &= ~kImm16Mask; |
| 737 | int32_t imm16 = imm18 >> 2; |
Ben Murdoch | b8a8cc1 | 2014-11-26 15:28:44 +0000 | [diff] [blame] | 738 | DCHECK(is_int16(imm16)); |
Andrei Popescu | 3100271 | 2010-02-23 13:46:05 +0000 | [diff] [blame] | 739 | |
Ben Murdoch | 3fb3ca8 | 2011-12-02 17:19:32 +0000 | [diff] [blame] | 740 | instr_at_put(pos, instr | (imm16 & kImm16Mask)); |
| 741 | } else if (IsLui(instr)) { |
| 742 | Instr instr_lui = instr_at(pos + 0 * Assembler::kInstrSize); |
| 743 | Instr instr_ori = instr_at(pos + 1 * Assembler::kInstrSize); |
Ben Murdoch | b8a8cc1 | 2014-11-26 15:28:44 +0000 | [diff] [blame] | 744 | DCHECK(IsOri(instr_ori)); |
| 745 | uint32_t imm = reinterpret_cast<uint32_t>(buffer_) + target_pos; |
| 746 | DCHECK((imm & 3) == 0); |
Ben Murdoch | 3fb3ca8 | 2011-12-02 17:19:32 +0000 | [diff] [blame] | 747 | |
| 748 | instr_lui &= ~kImm16Mask; |
| 749 | instr_ori &= ~kImm16Mask; |
| 750 | |
| 751 | instr_at_put(pos + 0 * Assembler::kInstrSize, |
| 752 | instr_lui | ((imm & kHiMask) >> kLuiShift)); |
| 753 | instr_at_put(pos + 1 * Assembler::kInstrSize, |
| 754 | instr_ori | (imm & kImm16Mask)); |
| 755 | } else { |
Ben Murdoch | b8a8cc1 | 2014-11-26 15:28:44 +0000 | [diff] [blame] | 756 | uint32_t imm28 = reinterpret_cast<uint32_t>(buffer_) + target_pos; |
Ben Murdoch | 3fb3ca8 | 2011-12-02 17:19:32 +0000 | [diff] [blame] | 757 | imm28 &= kImm28Mask; |
Ben Murdoch | b8a8cc1 | 2014-11-26 15:28:44 +0000 | [diff] [blame] | 758 | DCHECK((imm28 & 3) == 0); |
Ben Murdoch | 3fb3ca8 | 2011-12-02 17:19:32 +0000 | [diff] [blame] | 759 | |
| 760 | instr &= ~kImm26Mask; |
| 761 | uint32_t imm26 = imm28 >> 2; |
Ben Murdoch | b8a8cc1 | 2014-11-26 15:28:44 +0000 | [diff] [blame] | 762 | DCHECK(is_uint26(imm26)); |
Ben Murdoch | 3fb3ca8 | 2011-12-02 17:19:32 +0000 | [diff] [blame] | 763 | |
| 764 | instr_at_put(pos, instr | (imm26 & kImm26Mask)); |
| 765 | } |
Andrei Popescu | 3100271 | 2010-02-23 13:46:05 +0000 | [diff] [blame] | 766 | } |
| 767 | |
| 768 | |
| 769 | void Assembler::print(Label* L) { |
| 770 | if (L->is_unused()) { |
| 771 | PrintF("unused label\n"); |
| 772 | } else if (L->is_bound()) { |
| 773 | PrintF("bound label to %d\n", L->pos()); |
| 774 | } else if (L->is_linked()) { |
| 775 | Label l = *L; |
| 776 | PrintF("unbound label"); |
| 777 | while (l.is_linked()) { |
| 778 | PrintF("@ %d ", l.pos()); |
| 779 | Instr instr = instr_at(l.pos()); |
| 780 | if ((instr & ~kImm16Mask) == 0) { |
| 781 | PrintF("value\n"); |
| 782 | } else { |
| 783 | PrintF("%d\n", instr); |
| 784 | } |
| 785 | next(&l); |
| 786 | } |
| 787 | } else { |
| 788 | PrintF("label in inconsistent state (pos = %d)\n", L->pos_); |
| 789 | } |
| 790 | } |
| 791 | |
| 792 | |
| 793 | void Assembler::bind_to(Label* L, int pos) { |
Ben Murdoch | b8a8cc1 | 2014-11-26 15:28:44 +0000 | [diff] [blame] | 794 | DCHECK(0 <= pos && pos <= pc_offset()); // Must have valid binding position. |
Ben Murdoch | 3fb3ca8 | 2011-12-02 17:19:32 +0000 | [diff] [blame] | 795 | int32_t trampoline_pos = kInvalidSlotPos; |
| 796 | if (L->is_linked() && !trampoline_emitted_) { |
| 797 | unbound_labels_count_--; |
| 798 | next_buffer_check_ += kTrampolineSlotsSize; |
| 799 | } |
| 800 | |
Andrei Popescu | 3100271 | 2010-02-23 13:46:05 +0000 | [diff] [blame] | 801 | while (L->is_linked()) { |
| 802 | int32_t fixup_pos = L->pos(); |
Steve Block | 44f0eee | 2011-05-26 01:26:41 +0100 | [diff] [blame] | 803 | int32_t dist = pos - fixup_pos; |
| 804 | next(L); // Call next before overwriting link with target at fixup_pos. |
Ben Murdoch | 3fb3ca8 | 2011-12-02 17:19:32 +0000 | [diff] [blame] | 805 | Instr instr = instr_at(fixup_pos); |
| 806 | if (IsBranch(instr)) { |
| 807 | if (dist > kMaxBranchOffset) { |
| 808 | if (trampoline_pos == kInvalidSlotPos) { |
| 809 | trampoline_pos = get_trampoline_entry(fixup_pos); |
| 810 | CHECK(trampoline_pos != kInvalidSlotPos); |
Ben Murdoch | 257744e | 2011-11-30 15:57:28 +0000 | [diff] [blame] | 811 | } |
Ben Murdoch | b8a8cc1 | 2014-11-26 15:28:44 +0000 | [diff] [blame] | 812 | DCHECK((trampoline_pos - fixup_pos) <= kMaxBranchOffset); |
Steve Block | 44f0eee | 2011-05-26 01:26:41 +0100 | [diff] [blame] | 813 | target_at_put(fixup_pos, trampoline_pos); |
| 814 | fixup_pos = trampoline_pos; |
| 815 | dist = pos - fixup_pos; |
Ben Murdoch | 3fb3ca8 | 2011-12-02 17:19:32 +0000 | [diff] [blame] | 816 | } |
| 817 | target_at_put(fixup_pos, pos); |
| 818 | } else { |
Ben Murdoch | b8a8cc1 | 2014-11-26 15:28:44 +0000 | [diff] [blame] | 819 | DCHECK(IsJ(instr) || IsLui(instr) || IsEmittedConstant(instr)); |
Ben Murdoch | 3fb3ca8 | 2011-12-02 17:19:32 +0000 | [diff] [blame] | 820 | target_at_put(fixup_pos, pos); |
| 821 | } |
Andrei Popescu | 3100271 | 2010-02-23 13:46:05 +0000 | [diff] [blame] | 822 | } |
| 823 | L->bind_to(pos); |
| 824 | |
| 825 | // Keep track of the last bound label so we don't eliminate any instructions |
| 826 | // before a bound label. |
| 827 | if (pos > last_bound_pos_) |
| 828 | last_bound_pos_ = pos; |
| 829 | } |
| 830 | |
| 831 | |
Andrei Popescu | 3100271 | 2010-02-23 13:46:05 +0000 | [diff] [blame] | 832 | void Assembler::bind(Label* L) { |
Ben Murdoch | b8a8cc1 | 2014-11-26 15:28:44 +0000 | [diff] [blame] | 833 | DCHECK(!L->is_bound()); // Label can only be bound once. |
Andrei Popescu | 3100271 | 2010-02-23 13:46:05 +0000 | [diff] [blame] | 834 | bind_to(L, pc_offset()); |
| 835 | } |
| 836 | |
| 837 | |
| 838 | void Assembler::next(Label* L) { |
Ben Murdoch | b8a8cc1 | 2014-11-26 15:28:44 +0000 | [diff] [blame] | 839 | DCHECK(L->is_linked()); |
Andrei Popescu | 3100271 | 2010-02-23 13:46:05 +0000 | [diff] [blame] | 840 | int link = target_at(L->pos()); |
Steve Block | 44f0eee | 2011-05-26 01:26:41 +0100 | [diff] [blame] | 841 | if (link == kEndOfChain) { |
Andrei Popescu | 3100271 | 2010-02-23 13:46:05 +0000 | [diff] [blame] | 842 | L->Unuse(); |
Ben Murdoch | 69a99ed | 2011-11-30 16:03:39 +0000 | [diff] [blame] | 843 | } else { |
Ben Murdoch | b8a8cc1 | 2014-11-26 15:28:44 +0000 | [diff] [blame] | 844 | DCHECK(link >= 0); |
Steve Block | 44f0eee | 2011-05-26 01:26:41 +0100 | [diff] [blame] | 845 | L->link_to(link); |
Andrei Popescu | 3100271 | 2010-02-23 13:46:05 +0000 | [diff] [blame] | 846 | } |
| 847 | } |
| 848 | |
Ben Murdoch | b8a8cc1 | 2014-11-26 15:28:44 +0000 | [diff] [blame] | 849 | |
Ben Murdoch | 3fb3ca8 | 2011-12-02 17:19:32 +0000 | [diff] [blame] | 850 | bool Assembler::is_near(Label* L) { |
| 851 | if (L->is_bound()) { |
| 852 | return ((pc_offset() - L->pos()) < kMaxBranchOffset - 4 * kInstrSize); |
| 853 | } |
| 854 | return false; |
| 855 | } |
Andrei Popescu | 3100271 | 2010-02-23 13:46:05 +0000 | [diff] [blame] | 856 | |
Ben Murdoch | b8a8cc1 | 2014-11-26 15:28:44 +0000 | [diff] [blame] | 857 | |
Andrei Popescu | 3100271 | 2010-02-23 13:46:05 +0000 | [diff] [blame] | 858 | // We have to use a temporary register for things that can be relocated even |
| 859 | // if they can be encoded in the MIPS's 16 bits of immediate-offset instruction |
| 860 | // space. There is no guarantee that the relocated location can be similarly |
| 861 | // encoded. |
Steve Block | 44f0eee | 2011-05-26 01:26:41 +0100 | [diff] [blame] | 862 | bool Assembler::MustUseReg(RelocInfo::Mode rmode) { |
Ben Murdoch | b8a8cc1 | 2014-11-26 15:28:44 +0000 | [diff] [blame] | 863 | return !RelocInfo::IsNone(rmode); |
Andrei Popescu | 3100271 | 2010-02-23 13:46:05 +0000 | [diff] [blame] | 864 | } |
| 865 | |
Andrei Popescu | 3100271 | 2010-02-23 13:46:05 +0000 | [diff] [blame] | 866 | void Assembler::GenInstrRegister(Opcode opcode, |
| 867 | Register rs, |
| 868 | Register rt, |
| 869 | Register rd, |
| 870 | uint16_t sa, |
| 871 | SecondaryField func) { |
Ben Murdoch | b8a8cc1 | 2014-11-26 15:28:44 +0000 | [diff] [blame] | 872 | DCHECK(rd.is_valid() && rs.is_valid() && rt.is_valid() && is_uint5(sa)); |
Andrei Popescu | 3100271 | 2010-02-23 13:46:05 +0000 | [diff] [blame] | 873 | Instr instr = opcode | (rs.code() << kRsShift) | (rt.code() << kRtShift) |
| 874 | | (rd.code() << kRdShift) | (sa << kSaShift) | func; |
| 875 | emit(instr); |
| 876 | } |
| 877 | |
| 878 | |
| 879 | void Assembler::GenInstrRegister(Opcode opcode, |
Steve Block | 44f0eee | 2011-05-26 01:26:41 +0100 | [diff] [blame] | 880 | Register rs, |
| 881 | Register rt, |
| 882 | uint16_t msb, |
| 883 | uint16_t lsb, |
| 884 | SecondaryField func) { |
Ben Murdoch | b8a8cc1 | 2014-11-26 15:28:44 +0000 | [diff] [blame] | 885 | DCHECK(rs.is_valid() && rt.is_valid() && is_uint5(msb) && is_uint5(lsb)); |
Steve Block | 44f0eee | 2011-05-26 01:26:41 +0100 | [diff] [blame] | 886 | Instr instr = opcode | (rs.code() << kRsShift) | (rt.code() << kRtShift) |
| 887 | | (msb << kRdShift) | (lsb << kSaShift) | func; |
| 888 | emit(instr); |
| 889 | } |
| 890 | |
| 891 | |
| 892 | void Assembler::GenInstrRegister(Opcode opcode, |
Andrei Popescu | 3100271 | 2010-02-23 13:46:05 +0000 | [diff] [blame] | 893 | SecondaryField fmt, |
| 894 | FPURegister ft, |
| 895 | FPURegister fs, |
| 896 | FPURegister fd, |
| 897 | SecondaryField func) { |
Ben Murdoch | b8a8cc1 | 2014-11-26 15:28:44 +0000 | [diff] [blame] | 898 | DCHECK(fd.is_valid() && fs.is_valid() && ft.is_valid()); |
Steve Block | 44f0eee | 2011-05-26 01:26:41 +0100 | [diff] [blame] | 899 | Instr instr = opcode | fmt | (ft.code() << kFtShift) | (fs.code() << kFsShift) |
| 900 | | (fd.code() << kFdShift) | func; |
Andrei Popescu | 3100271 | 2010-02-23 13:46:05 +0000 | [diff] [blame] | 901 | emit(instr); |
| 902 | } |
| 903 | |
| 904 | |
| 905 | void Assembler::GenInstrRegister(Opcode opcode, |
Ben Murdoch | b8a8cc1 | 2014-11-26 15:28:44 +0000 | [diff] [blame] | 906 | FPURegister fr, |
| 907 | FPURegister ft, |
| 908 | FPURegister fs, |
| 909 | FPURegister fd, |
| 910 | SecondaryField func) { |
| 911 | DCHECK(fd.is_valid() && fr.is_valid() && fs.is_valid() && ft.is_valid()); |
| 912 | Instr instr = opcode | (fr.code() << kFrShift) | (ft.code() << kFtShift) |
| 913 | | (fs.code() << kFsShift) | (fd.code() << kFdShift) | func; |
| 914 | emit(instr); |
| 915 | } |
| 916 | |
| 917 | |
| 918 | void Assembler::GenInstrRegister(Opcode opcode, |
Andrei Popescu | 3100271 | 2010-02-23 13:46:05 +0000 | [diff] [blame] | 919 | SecondaryField fmt, |
| 920 | Register rt, |
| 921 | FPURegister fs, |
| 922 | FPURegister fd, |
| 923 | SecondaryField func) { |
Ben Murdoch | b8a8cc1 | 2014-11-26 15:28:44 +0000 | [diff] [blame] | 924 | DCHECK(fd.is_valid() && fs.is_valid() && rt.is_valid()); |
Andrei Popescu | 3100271 | 2010-02-23 13:46:05 +0000 | [diff] [blame] | 925 | Instr instr = opcode | fmt | (rt.code() << kRtShift) |
Steve Block | 44f0eee | 2011-05-26 01:26:41 +0100 | [diff] [blame] | 926 | | (fs.code() << kFsShift) | (fd.code() << kFdShift) | func; |
| 927 | emit(instr); |
| 928 | } |
| 929 | |
| 930 | |
| 931 | void Assembler::GenInstrRegister(Opcode opcode, |
| 932 | SecondaryField fmt, |
| 933 | Register rt, |
| 934 | FPUControlRegister fs, |
| 935 | SecondaryField func) { |
Ben Murdoch | b8a8cc1 | 2014-11-26 15:28:44 +0000 | [diff] [blame] | 936 | DCHECK(fs.is_valid() && rt.is_valid()); |
Steve Block | 44f0eee | 2011-05-26 01:26:41 +0100 | [diff] [blame] | 937 | Instr instr = |
| 938 | opcode | fmt | (rt.code() << kRtShift) | (fs.code() << kFsShift) | func; |
Andrei Popescu | 3100271 | 2010-02-23 13:46:05 +0000 | [diff] [blame] | 939 | emit(instr); |
| 940 | } |
| 941 | |
| 942 | |
| 943 | // Instructions with immediate value. |
| 944 | // Registers are in the order of the instruction encoding, from left to right. |
| 945 | void Assembler::GenInstrImmediate(Opcode opcode, |
| 946 | Register rs, |
| 947 | Register rt, |
| 948 | int32_t j) { |
Ben Murdoch | b8a8cc1 | 2014-11-26 15:28:44 +0000 | [diff] [blame] | 949 | DCHECK(rs.is_valid() && rt.is_valid() && (is_int16(j) || is_uint16(j))); |
Andrei Popescu | 3100271 | 2010-02-23 13:46:05 +0000 | [diff] [blame] | 950 | Instr instr = opcode | (rs.code() << kRsShift) | (rt.code() << kRtShift) |
| 951 | | (j & kImm16Mask); |
| 952 | emit(instr); |
| 953 | } |
| 954 | |
| 955 | |
| 956 | void Assembler::GenInstrImmediate(Opcode opcode, |
| 957 | Register rs, |
| 958 | SecondaryField SF, |
| 959 | int32_t j) { |
Ben Murdoch | b8a8cc1 | 2014-11-26 15:28:44 +0000 | [diff] [blame] | 960 | DCHECK(rs.is_valid() && (is_int16(j) || is_uint16(j))); |
Andrei Popescu | 3100271 | 2010-02-23 13:46:05 +0000 | [diff] [blame] | 961 | Instr instr = opcode | (rs.code() << kRsShift) | SF | (j & kImm16Mask); |
| 962 | emit(instr); |
| 963 | } |
| 964 | |
| 965 | |
| 966 | void Assembler::GenInstrImmediate(Opcode opcode, |
| 967 | Register rs, |
| 968 | FPURegister ft, |
| 969 | int32_t j) { |
Ben Murdoch | b8a8cc1 | 2014-11-26 15:28:44 +0000 | [diff] [blame] | 970 | DCHECK(rs.is_valid() && ft.is_valid() && (is_int16(j) || is_uint16(j))); |
Andrei Popescu | 3100271 | 2010-02-23 13:46:05 +0000 | [diff] [blame] | 971 | Instr instr = opcode | (rs.code() << kRsShift) | (ft.code() << kFtShift) |
| 972 | | (j & kImm16Mask); |
| 973 | emit(instr); |
| 974 | } |
| 975 | |
| 976 | |
Andrei Popescu | 3100271 | 2010-02-23 13:46:05 +0000 | [diff] [blame] | 977 | void Assembler::GenInstrJump(Opcode opcode, |
Ben Murdoch | 589d697 | 2011-11-30 16:04:58 +0000 | [diff] [blame] | 978 | uint32_t address) { |
Steve Block | 44f0eee | 2011-05-26 01:26:41 +0100 | [diff] [blame] | 979 | BlockTrampolinePoolScope block_trampoline_pool(this); |
Ben Murdoch | b8a8cc1 | 2014-11-26 15:28:44 +0000 | [diff] [blame] | 980 | DCHECK(is_uint26(address)); |
Andrei Popescu | 3100271 | 2010-02-23 13:46:05 +0000 | [diff] [blame] | 981 | Instr instr = opcode | address; |
| 982 | emit(instr); |
Steve Block | 44f0eee | 2011-05-26 01:26:41 +0100 | [diff] [blame] | 983 | BlockTrampolinePoolFor(1); // For associated delay slot. |
| 984 | } |
| 985 | |
| 986 | |
Ben Murdoch | 3fb3ca8 | 2011-12-02 17:19:32 +0000 | [diff] [blame] | 987 | // Returns the next free trampoline entry. |
| 988 | int32_t Assembler::get_trampoline_entry(int32_t pos) { |
Ben Murdoch | 257744e | 2011-11-30 15:57:28 +0000 | [diff] [blame] | 989 | int32_t trampoline_entry = kInvalidSlotPos; |
Steve Block | 44f0eee | 2011-05-26 01:26:41 +0100 | [diff] [blame] | 990 | |
Ben Murdoch | 257744e | 2011-11-30 15:57:28 +0000 | [diff] [blame] | 991 | if (!internal_trampoline_exception_) { |
Ben Murdoch | 3fb3ca8 | 2011-12-02 17:19:32 +0000 | [diff] [blame] | 992 | if (trampoline_.start() > pos) { |
| 993 | trampoline_entry = trampoline_.take_slot(); |
Steve Block | 44f0eee | 2011-05-26 01:26:41 +0100 | [diff] [blame] | 994 | } |
Ben Murdoch | 3fb3ca8 | 2011-12-02 17:19:32 +0000 | [diff] [blame] | 995 | |
Ben Murdoch | 257744e | 2011-11-30 15:57:28 +0000 | [diff] [blame] | 996 | if (kInvalidSlotPos == trampoline_entry) { |
| 997 | internal_trampoline_exception_ = true; |
Steve Block | 44f0eee | 2011-05-26 01:26:41 +0100 | [diff] [blame] | 998 | } |
| 999 | } |
| 1000 | return trampoline_entry; |
Andrei Popescu | 3100271 | 2010-02-23 13:46:05 +0000 | [diff] [blame] | 1001 | } |
| 1002 | |
| 1003 | |
Ben Murdoch | 3fb3ca8 | 2011-12-02 17:19:32 +0000 | [diff] [blame] | 1004 | uint32_t Assembler::jump_address(Label* L) { |
Andrei Popescu | 3100271 | 2010-02-23 13:46:05 +0000 | [diff] [blame] | 1005 | int32_t target_pos; |
Steve Block | 44f0eee | 2011-05-26 01:26:41 +0100 | [diff] [blame] | 1006 | |
Andrei Popescu | 3100271 | 2010-02-23 13:46:05 +0000 | [diff] [blame] | 1007 | if (L->is_bound()) { |
| 1008 | target_pos = L->pos(); |
| 1009 | } else { |
| 1010 | if (L->is_linked()) { |
Steve Block | 44f0eee | 2011-05-26 01:26:41 +0100 | [diff] [blame] | 1011 | target_pos = L->pos(); // L's link. |
Steve Block | 44f0eee | 2011-05-26 01:26:41 +0100 | [diff] [blame] | 1012 | L->link_to(pc_offset()); |
Andrei Popescu | 3100271 | 2010-02-23 13:46:05 +0000 | [diff] [blame] | 1013 | } else { |
Steve Block | 44f0eee | 2011-05-26 01:26:41 +0100 | [diff] [blame] | 1014 | L->link_to(pc_offset()); |
Ben Murdoch | 3fb3ca8 | 2011-12-02 17:19:32 +0000 | [diff] [blame] | 1015 | return kEndOfJumpChain; |
| 1016 | } |
| 1017 | } |
| 1018 | |
Ben Murdoch | b8a8cc1 | 2014-11-26 15:28:44 +0000 | [diff] [blame] | 1019 | uint32_t imm = reinterpret_cast<uint32_t>(buffer_) + target_pos; |
| 1020 | DCHECK((imm & 3) == 0); |
Ben Murdoch | 3fb3ca8 | 2011-12-02 17:19:32 +0000 | [diff] [blame] | 1021 | |
| 1022 | return imm; |
| 1023 | } |
| 1024 | |
| 1025 | |
| 1026 | int32_t Assembler::branch_offset(Label* L, bool jump_elimination_allowed) { |
| 1027 | int32_t target_pos; |
| 1028 | |
| 1029 | if (L->is_bound()) { |
| 1030 | target_pos = L->pos(); |
| 1031 | } else { |
| 1032 | if (L->is_linked()) { |
| 1033 | target_pos = L->pos(); |
| 1034 | L->link_to(pc_offset()); |
| 1035 | } else { |
| 1036 | L->link_to(pc_offset()); |
| 1037 | if (!trampoline_emitted_) { |
| 1038 | unbound_labels_count_++; |
| 1039 | next_buffer_check_ -= kTrampolineSlotsSize; |
| 1040 | } |
Steve Block | 44f0eee | 2011-05-26 01:26:41 +0100 | [diff] [blame] | 1041 | return kEndOfChain; |
Andrei Popescu | 3100271 | 2010-02-23 13:46:05 +0000 | [diff] [blame] | 1042 | } |
Andrei Popescu | 3100271 | 2010-02-23 13:46:05 +0000 | [diff] [blame] | 1043 | } |
| 1044 | |
| 1045 | int32_t offset = target_pos - (pc_offset() + kBranchPCOffset); |
Ben Murdoch | b8a8cc1 | 2014-11-26 15:28:44 +0000 | [diff] [blame] | 1046 | DCHECK((offset & 3) == 0); |
| 1047 | DCHECK(is_int16(offset >> 2)); |
| 1048 | |
| 1049 | return offset; |
| 1050 | } |
| 1051 | |
| 1052 | |
| 1053 | int32_t Assembler::branch_offset_compact(Label* L, |
| 1054 | bool jump_elimination_allowed) { |
| 1055 | int32_t target_pos; |
| 1056 | if (L->is_bound()) { |
| 1057 | target_pos = L->pos(); |
| 1058 | } else { |
| 1059 | if (L->is_linked()) { |
| 1060 | target_pos = L->pos(); |
| 1061 | L->link_to(pc_offset()); |
| 1062 | } else { |
| 1063 | L->link_to(pc_offset()); |
| 1064 | if (!trampoline_emitted_) { |
| 1065 | unbound_labels_count_++; |
| 1066 | next_buffer_check_ -= kTrampolineSlotsSize; |
| 1067 | } |
| 1068 | return kEndOfChain; |
| 1069 | } |
| 1070 | } |
| 1071 | |
| 1072 | int32_t offset = target_pos - pc_offset(); |
| 1073 | DCHECK((offset & 3) == 0); |
| 1074 | DCHECK(is_int16(offset >> 2)); |
| 1075 | |
| 1076 | return offset; |
| 1077 | } |
| 1078 | |
| 1079 | |
| 1080 | int32_t Assembler::branch_offset21(Label* L, bool jump_elimination_allowed) { |
| 1081 | int32_t target_pos; |
| 1082 | |
| 1083 | if (L->is_bound()) { |
| 1084 | target_pos = L->pos(); |
| 1085 | } else { |
| 1086 | if (L->is_linked()) { |
| 1087 | target_pos = L->pos(); |
| 1088 | L->link_to(pc_offset()); |
| 1089 | } else { |
| 1090 | L->link_to(pc_offset()); |
| 1091 | if (!trampoline_emitted_) { |
| 1092 | unbound_labels_count_++; |
| 1093 | next_buffer_check_ -= kTrampolineSlotsSize; |
| 1094 | } |
| 1095 | return kEndOfChain; |
| 1096 | } |
| 1097 | } |
| 1098 | |
| 1099 | int32_t offset = target_pos - (pc_offset() + kBranchPCOffset); |
| 1100 | DCHECK((offset & 3) == 0); |
| 1101 | DCHECK(((offset >> 2) & 0xFFE00000) == 0); // Offset is 21bit width. |
| 1102 | |
| 1103 | return offset; |
| 1104 | } |
| 1105 | |
| 1106 | |
| 1107 | int32_t Assembler::branch_offset21_compact(Label* L, |
| 1108 | bool jump_elimination_allowed) { |
| 1109 | int32_t target_pos; |
| 1110 | |
| 1111 | if (L->is_bound()) { |
| 1112 | target_pos = L->pos(); |
| 1113 | } else { |
| 1114 | if (L->is_linked()) { |
| 1115 | target_pos = L->pos(); |
| 1116 | L->link_to(pc_offset()); |
| 1117 | } else { |
| 1118 | L->link_to(pc_offset()); |
| 1119 | if (!trampoline_emitted_) { |
| 1120 | unbound_labels_count_++; |
| 1121 | next_buffer_check_ -= kTrampolineSlotsSize; |
| 1122 | } |
| 1123 | return kEndOfChain; |
| 1124 | } |
| 1125 | } |
| 1126 | |
| 1127 | int32_t offset = target_pos - pc_offset(); |
| 1128 | DCHECK((offset & 3) == 0); |
| 1129 | DCHECK(((offset >> 2) & 0xFFe00000) == 0); // Offset is 21bit width. |
Steve Block | 44f0eee | 2011-05-26 01:26:41 +0100 | [diff] [blame] | 1130 | |
Andrei Popescu | 3100271 | 2010-02-23 13:46:05 +0000 | [diff] [blame] | 1131 | return offset; |
| 1132 | } |
| 1133 | |
| 1134 | |
| 1135 | void Assembler::label_at_put(Label* L, int at_offset) { |
| 1136 | int target_pos; |
| 1137 | if (L->is_bound()) { |
| 1138 | target_pos = L->pos(); |
Steve Block | 44f0eee | 2011-05-26 01:26:41 +0100 | [diff] [blame] | 1139 | instr_at_put(at_offset, target_pos + (Code::kHeaderSize - kHeapObjectTag)); |
Andrei Popescu | 3100271 | 2010-02-23 13:46:05 +0000 | [diff] [blame] | 1140 | } else { |
| 1141 | if (L->is_linked()) { |
Steve Block | 44f0eee | 2011-05-26 01:26:41 +0100 | [diff] [blame] | 1142 | target_pos = L->pos(); // L's link. |
| 1143 | int32_t imm18 = target_pos - at_offset; |
Ben Murdoch | b8a8cc1 | 2014-11-26 15:28:44 +0000 | [diff] [blame] | 1144 | DCHECK((imm18 & 3) == 0); |
Steve Block | 44f0eee | 2011-05-26 01:26:41 +0100 | [diff] [blame] | 1145 | int32_t imm16 = imm18 >> 2; |
Ben Murdoch | b8a8cc1 | 2014-11-26 15:28:44 +0000 | [diff] [blame] | 1146 | DCHECK(is_int16(imm16)); |
Steve Block | 44f0eee | 2011-05-26 01:26:41 +0100 | [diff] [blame] | 1147 | instr_at_put(at_offset, (imm16 & kImm16Mask)); |
Andrei Popescu | 3100271 | 2010-02-23 13:46:05 +0000 | [diff] [blame] | 1148 | } else { |
| 1149 | target_pos = kEndOfChain; |
Steve Block | 44f0eee | 2011-05-26 01:26:41 +0100 | [diff] [blame] | 1150 | instr_at_put(at_offset, 0); |
Ben Murdoch | 3fb3ca8 | 2011-12-02 17:19:32 +0000 | [diff] [blame] | 1151 | if (!trampoline_emitted_) { |
| 1152 | unbound_labels_count_++; |
| 1153 | next_buffer_check_ -= kTrampolineSlotsSize; |
| 1154 | } |
Andrei Popescu | 3100271 | 2010-02-23 13:46:05 +0000 | [diff] [blame] | 1155 | } |
| 1156 | L->link_to(at_offset); |
Andrei Popescu | 3100271 | 2010-02-23 13:46:05 +0000 | [diff] [blame] | 1157 | } |
| 1158 | } |
| 1159 | |
| 1160 | |
| 1161 | //------- Branch and jump instructions -------- |
| 1162 | |
| 1163 | void Assembler::b(int16_t offset) { |
| 1164 | beq(zero_reg, zero_reg, offset); |
| 1165 | } |
| 1166 | |
| 1167 | |
| 1168 | void Assembler::bal(int16_t offset) { |
Steve Block | 44f0eee | 2011-05-26 01:26:41 +0100 | [diff] [blame] | 1169 | positions_recorder()->WriteRecordedPositions(); |
Andrei Popescu | 3100271 | 2010-02-23 13:46:05 +0000 | [diff] [blame] | 1170 | bgezal(zero_reg, offset); |
| 1171 | } |
| 1172 | |
| 1173 | |
| 1174 | void Assembler::beq(Register rs, Register rt, int16_t offset) { |
Steve Block | 44f0eee | 2011-05-26 01:26:41 +0100 | [diff] [blame] | 1175 | BlockTrampolinePoolScope block_trampoline_pool(this); |
Andrei Popescu | 3100271 | 2010-02-23 13:46:05 +0000 | [diff] [blame] | 1176 | GenInstrImmediate(BEQ, rs, rt, offset); |
Steve Block | 44f0eee | 2011-05-26 01:26:41 +0100 | [diff] [blame] | 1177 | BlockTrampolinePoolFor(1); // For associated delay slot. |
Andrei Popescu | 3100271 | 2010-02-23 13:46:05 +0000 | [diff] [blame] | 1178 | } |
| 1179 | |
| 1180 | |
| 1181 | void Assembler::bgez(Register rs, int16_t offset) { |
Steve Block | 44f0eee | 2011-05-26 01:26:41 +0100 | [diff] [blame] | 1182 | BlockTrampolinePoolScope block_trampoline_pool(this); |
Andrei Popescu | 3100271 | 2010-02-23 13:46:05 +0000 | [diff] [blame] | 1183 | GenInstrImmediate(REGIMM, rs, BGEZ, offset); |
Steve Block | 44f0eee | 2011-05-26 01:26:41 +0100 | [diff] [blame] | 1184 | BlockTrampolinePoolFor(1); // For associated delay slot. |
Andrei Popescu | 3100271 | 2010-02-23 13:46:05 +0000 | [diff] [blame] | 1185 | } |
| 1186 | |
| 1187 | |
Ben Murdoch | b8a8cc1 | 2014-11-26 15:28:44 +0000 | [diff] [blame] | 1188 | void Assembler::bgezc(Register rt, int16_t offset) { |
| 1189 | DCHECK(IsMipsArchVariant(kMips32r6)); |
| 1190 | DCHECK(!(rt.is(zero_reg))); |
| 1191 | GenInstrImmediate(BLEZL, rt, rt, offset); |
| 1192 | } |
| 1193 | |
| 1194 | |
| 1195 | void Assembler::bgeuc(Register rs, Register rt, int16_t offset) { |
| 1196 | DCHECK(IsMipsArchVariant(kMips32r6)); |
| 1197 | DCHECK(!(rs.is(zero_reg))); |
| 1198 | DCHECK(!(rt.is(zero_reg))); |
| 1199 | DCHECK(rs.code() != rt.code()); |
| 1200 | GenInstrImmediate(BLEZ, rs, rt, offset); |
| 1201 | } |
| 1202 | |
| 1203 | |
| 1204 | void Assembler::bgec(Register rs, Register rt, int16_t offset) { |
| 1205 | DCHECK(IsMipsArchVariant(kMips32r6)); |
| 1206 | DCHECK(!(rs.is(zero_reg))); |
| 1207 | DCHECK(!(rt.is(zero_reg))); |
| 1208 | DCHECK(rs.code() != rt.code()); |
| 1209 | GenInstrImmediate(BLEZL, rs, rt, offset); |
| 1210 | } |
| 1211 | |
| 1212 | |
Andrei Popescu | 3100271 | 2010-02-23 13:46:05 +0000 | [diff] [blame] | 1213 | void Assembler::bgezal(Register rs, int16_t offset) { |
Ben Murdoch | b8a8cc1 | 2014-11-26 15:28:44 +0000 | [diff] [blame] | 1214 | DCHECK(!IsMipsArchVariant(kMips32r6) || rs.is(zero_reg)); |
Steve Block | 44f0eee | 2011-05-26 01:26:41 +0100 | [diff] [blame] | 1215 | BlockTrampolinePoolScope block_trampoline_pool(this); |
| 1216 | positions_recorder()->WriteRecordedPositions(); |
Andrei Popescu | 3100271 | 2010-02-23 13:46:05 +0000 | [diff] [blame] | 1217 | GenInstrImmediate(REGIMM, rs, BGEZAL, offset); |
Steve Block | 44f0eee | 2011-05-26 01:26:41 +0100 | [diff] [blame] | 1218 | BlockTrampolinePoolFor(1); // For associated delay slot. |
Andrei Popescu | 3100271 | 2010-02-23 13:46:05 +0000 | [diff] [blame] | 1219 | } |
| 1220 | |
| 1221 | |
| 1222 | void Assembler::bgtz(Register rs, int16_t offset) { |
Steve Block | 44f0eee | 2011-05-26 01:26:41 +0100 | [diff] [blame] | 1223 | BlockTrampolinePoolScope block_trampoline_pool(this); |
Andrei Popescu | 3100271 | 2010-02-23 13:46:05 +0000 | [diff] [blame] | 1224 | GenInstrImmediate(BGTZ, rs, zero_reg, offset); |
Steve Block | 44f0eee | 2011-05-26 01:26:41 +0100 | [diff] [blame] | 1225 | BlockTrampolinePoolFor(1); // For associated delay slot. |
Andrei Popescu | 3100271 | 2010-02-23 13:46:05 +0000 | [diff] [blame] | 1226 | } |
| 1227 | |
| 1228 | |
Ben Murdoch | b8a8cc1 | 2014-11-26 15:28:44 +0000 | [diff] [blame] | 1229 | void Assembler::bgtzc(Register rt, int16_t offset) { |
| 1230 | DCHECK(IsMipsArchVariant(kMips32r6)); |
| 1231 | DCHECK(!(rt.is(zero_reg))); |
| 1232 | GenInstrImmediate(BGTZL, zero_reg, rt, offset); |
| 1233 | } |
| 1234 | |
| 1235 | |
Andrei Popescu | 3100271 | 2010-02-23 13:46:05 +0000 | [diff] [blame] | 1236 | void Assembler::blez(Register rs, int16_t offset) { |
Steve Block | 44f0eee | 2011-05-26 01:26:41 +0100 | [diff] [blame] | 1237 | BlockTrampolinePoolScope block_trampoline_pool(this); |
Andrei Popescu | 3100271 | 2010-02-23 13:46:05 +0000 | [diff] [blame] | 1238 | GenInstrImmediate(BLEZ, rs, zero_reg, offset); |
Steve Block | 44f0eee | 2011-05-26 01:26:41 +0100 | [diff] [blame] | 1239 | BlockTrampolinePoolFor(1); // For associated delay slot. |
Andrei Popescu | 3100271 | 2010-02-23 13:46:05 +0000 | [diff] [blame] | 1240 | } |
| 1241 | |
| 1242 | |
Ben Murdoch | b8a8cc1 | 2014-11-26 15:28:44 +0000 | [diff] [blame] | 1243 | void Assembler::blezc(Register rt, int16_t offset) { |
| 1244 | DCHECK(IsMipsArchVariant(kMips32r6)); |
| 1245 | DCHECK(!(rt.is(zero_reg))); |
| 1246 | GenInstrImmediate(BLEZL, zero_reg, rt, offset); |
| 1247 | } |
| 1248 | |
| 1249 | |
| 1250 | void Assembler::bltzc(Register rt, int16_t offset) { |
| 1251 | DCHECK(IsMipsArchVariant(kMips32r6)); |
| 1252 | DCHECK(!(rt.is(zero_reg))); |
| 1253 | GenInstrImmediate(BGTZL, rt, rt, offset); |
| 1254 | } |
| 1255 | |
| 1256 | |
| 1257 | void Assembler::bltuc(Register rs, Register rt, int16_t offset) { |
| 1258 | DCHECK(IsMipsArchVariant(kMips32r6)); |
| 1259 | DCHECK(!(rs.is(zero_reg))); |
| 1260 | DCHECK(!(rt.is(zero_reg))); |
| 1261 | DCHECK(rs.code() != rt.code()); |
| 1262 | GenInstrImmediate(BGTZ, rs, rt, offset); |
| 1263 | } |
| 1264 | |
| 1265 | |
| 1266 | void Assembler::bltc(Register rs, Register rt, int16_t offset) { |
| 1267 | DCHECK(IsMipsArchVariant(kMips32r6)); |
| 1268 | DCHECK(!(rs.is(zero_reg))); |
| 1269 | DCHECK(!(rt.is(zero_reg))); |
| 1270 | DCHECK(rs.code() != rt.code()); |
| 1271 | GenInstrImmediate(BGTZL, rs, rt, offset); |
| 1272 | } |
| 1273 | |
| 1274 | |
Andrei Popescu | 3100271 | 2010-02-23 13:46:05 +0000 | [diff] [blame] | 1275 | void Assembler::bltz(Register rs, int16_t offset) { |
Steve Block | 44f0eee | 2011-05-26 01:26:41 +0100 | [diff] [blame] | 1276 | BlockTrampolinePoolScope block_trampoline_pool(this); |
Andrei Popescu | 3100271 | 2010-02-23 13:46:05 +0000 | [diff] [blame] | 1277 | GenInstrImmediate(REGIMM, rs, BLTZ, offset); |
Steve Block | 44f0eee | 2011-05-26 01:26:41 +0100 | [diff] [blame] | 1278 | BlockTrampolinePoolFor(1); // For associated delay slot. |
Andrei Popescu | 3100271 | 2010-02-23 13:46:05 +0000 | [diff] [blame] | 1279 | } |
| 1280 | |
| 1281 | |
| 1282 | void Assembler::bltzal(Register rs, int16_t offset) { |
Ben Murdoch | b8a8cc1 | 2014-11-26 15:28:44 +0000 | [diff] [blame] | 1283 | DCHECK(!IsMipsArchVariant(kMips32r6) || rs.is(zero_reg)); |
Steve Block | 44f0eee | 2011-05-26 01:26:41 +0100 | [diff] [blame] | 1284 | BlockTrampolinePoolScope block_trampoline_pool(this); |
| 1285 | positions_recorder()->WriteRecordedPositions(); |
Andrei Popescu | 3100271 | 2010-02-23 13:46:05 +0000 | [diff] [blame] | 1286 | GenInstrImmediate(REGIMM, rs, BLTZAL, offset); |
Steve Block | 44f0eee | 2011-05-26 01:26:41 +0100 | [diff] [blame] | 1287 | BlockTrampolinePoolFor(1); // For associated delay slot. |
Andrei Popescu | 3100271 | 2010-02-23 13:46:05 +0000 | [diff] [blame] | 1288 | } |
| 1289 | |
| 1290 | |
| 1291 | void Assembler::bne(Register rs, Register rt, int16_t offset) { |
Steve Block | 44f0eee | 2011-05-26 01:26:41 +0100 | [diff] [blame] | 1292 | BlockTrampolinePoolScope block_trampoline_pool(this); |
Andrei Popescu | 3100271 | 2010-02-23 13:46:05 +0000 | [diff] [blame] | 1293 | GenInstrImmediate(BNE, rs, rt, offset); |
Steve Block | 44f0eee | 2011-05-26 01:26:41 +0100 | [diff] [blame] | 1294 | BlockTrampolinePoolFor(1); // For associated delay slot. |
Andrei Popescu | 3100271 | 2010-02-23 13:46:05 +0000 | [diff] [blame] | 1295 | } |
| 1296 | |
| 1297 | |
Ben Murdoch | b8a8cc1 | 2014-11-26 15:28:44 +0000 | [diff] [blame] | 1298 | void Assembler::bovc(Register rs, Register rt, int16_t offset) { |
| 1299 | DCHECK(IsMipsArchVariant(kMips32r6)); |
| 1300 | DCHECK(!(rs.is(zero_reg))); |
| 1301 | DCHECK(rs.code() >= rt.code()); |
| 1302 | GenInstrImmediate(ADDI, rs, rt, offset); |
| 1303 | } |
| 1304 | |
| 1305 | |
| 1306 | void Assembler::bnvc(Register rs, Register rt, int16_t offset) { |
| 1307 | DCHECK(IsMipsArchVariant(kMips32r6)); |
| 1308 | DCHECK(!(rs.is(zero_reg))); |
| 1309 | DCHECK(rs.code() >= rt.code()); |
| 1310 | GenInstrImmediate(DADDI, rs, rt, offset); |
| 1311 | } |
| 1312 | |
| 1313 | |
| 1314 | void Assembler::blezalc(Register rt, int16_t offset) { |
| 1315 | DCHECK(IsMipsArchVariant(kMips32r6)); |
| 1316 | DCHECK(!(rt.is(zero_reg))); |
| 1317 | GenInstrImmediate(BLEZ, zero_reg, rt, offset); |
| 1318 | } |
| 1319 | |
| 1320 | |
| 1321 | void Assembler::bgezalc(Register rt, int16_t offset) { |
| 1322 | DCHECK(IsMipsArchVariant(kMips32r6)); |
| 1323 | DCHECK(!(rt.is(zero_reg))); |
| 1324 | GenInstrImmediate(BLEZ, rt, rt, offset); |
| 1325 | } |
| 1326 | |
| 1327 | |
| 1328 | void Assembler::bgezall(Register rs, int16_t offset) { |
| 1329 | DCHECK(IsMipsArchVariant(kMips32r6)); |
| 1330 | DCHECK(!(rs.is(zero_reg))); |
| 1331 | GenInstrImmediate(REGIMM, rs, BGEZALL, offset); |
| 1332 | } |
| 1333 | |
| 1334 | |
| 1335 | void Assembler::bltzalc(Register rt, int16_t offset) { |
| 1336 | DCHECK(IsMipsArchVariant(kMips32r6)); |
| 1337 | DCHECK(!(rt.is(zero_reg))); |
| 1338 | GenInstrImmediate(BGTZ, rt, rt, offset); |
| 1339 | } |
| 1340 | |
| 1341 | |
| 1342 | void Assembler::bgtzalc(Register rt, int16_t offset) { |
| 1343 | DCHECK(IsMipsArchVariant(kMips32r6)); |
| 1344 | DCHECK(!(rt.is(zero_reg))); |
| 1345 | GenInstrImmediate(BGTZ, zero_reg, rt, offset); |
| 1346 | } |
| 1347 | |
| 1348 | |
| 1349 | void Assembler::beqzalc(Register rt, int16_t offset) { |
| 1350 | DCHECK(IsMipsArchVariant(kMips32r6)); |
| 1351 | DCHECK(!(rt.is(zero_reg))); |
| 1352 | GenInstrImmediate(ADDI, zero_reg, rt, offset); |
| 1353 | } |
| 1354 | |
| 1355 | |
| 1356 | void Assembler::bnezalc(Register rt, int16_t offset) { |
| 1357 | DCHECK(IsMipsArchVariant(kMips32r6)); |
| 1358 | DCHECK(!(rt.is(zero_reg))); |
| 1359 | GenInstrImmediate(DADDI, zero_reg, rt, offset); |
| 1360 | } |
| 1361 | |
| 1362 | |
| 1363 | void Assembler::beqc(Register rs, Register rt, int16_t offset) { |
| 1364 | DCHECK(IsMipsArchVariant(kMips32r6)); |
| 1365 | DCHECK(rs.code() < rt.code()); |
| 1366 | GenInstrImmediate(ADDI, rs, rt, offset); |
| 1367 | } |
| 1368 | |
| 1369 | |
| 1370 | void Assembler::beqzc(Register rs, int32_t offset) { |
| 1371 | DCHECK(IsMipsArchVariant(kMips32r6)); |
| 1372 | DCHECK(!(rs.is(zero_reg))); |
| 1373 | Instr instr = BEQZC | (rs.code() << kRsShift) | offset; |
| 1374 | emit(instr); |
| 1375 | } |
| 1376 | |
| 1377 | |
| 1378 | void Assembler::bnec(Register rs, Register rt, int16_t offset) { |
| 1379 | DCHECK(IsMipsArchVariant(kMips32r6)); |
| 1380 | DCHECK(rs.code() < rt.code()); |
| 1381 | GenInstrImmediate(DADDI, rs, rt, offset); |
| 1382 | } |
| 1383 | |
| 1384 | |
| 1385 | void Assembler::bnezc(Register rs, int32_t offset) { |
| 1386 | DCHECK(IsMipsArchVariant(kMips32r6)); |
| 1387 | DCHECK(!(rs.is(zero_reg))); |
| 1388 | Instr instr = BNEZC | (rs.code() << kRsShift) | offset; |
| 1389 | emit(instr); |
| 1390 | } |
| 1391 | |
| 1392 | |
Andrei Popescu | 3100271 | 2010-02-23 13:46:05 +0000 | [diff] [blame] | 1393 | void Assembler::j(int32_t target) { |
Ben Murdoch | 589d697 | 2011-11-30 16:04:58 +0000 | [diff] [blame] | 1394 | #if DEBUG |
| 1395 | // Get pc of delay slot. |
| 1396 | uint32_t ipc = reinterpret_cast<uint32_t>(pc_ + 1 * kInstrSize); |
Ben Murdoch | b8a8cc1 | 2014-11-26 15:28:44 +0000 | [diff] [blame] | 1397 | bool in_range = (ipc ^ static_cast<uint32_t>(target) >> |
| 1398 | (kImm26Bits + kImmFieldShift)) == 0; |
| 1399 | DCHECK(in_range && ((target & 3) == 0)); |
Ben Murdoch | 589d697 | 2011-11-30 16:04:58 +0000 | [diff] [blame] | 1400 | #endif |
Andrei Popescu | 3100271 | 2010-02-23 13:46:05 +0000 | [diff] [blame] | 1401 | GenInstrJump(J, target >> 2); |
| 1402 | } |
| 1403 | |
| 1404 | |
| 1405 | void Assembler::jr(Register rs) { |
Ben Murdoch | b8a8cc1 | 2014-11-26 15:28:44 +0000 | [diff] [blame] | 1406 | if (!IsMipsArchVariant(kMips32r6)) { |
| 1407 | BlockTrampolinePoolScope block_trampoline_pool(this); |
| 1408 | if (rs.is(ra)) { |
| 1409 | positions_recorder()->WriteRecordedPositions(); |
| 1410 | } |
| 1411 | GenInstrRegister(SPECIAL, rs, zero_reg, zero_reg, 0, JR); |
| 1412 | BlockTrampolinePoolFor(1); // For associated delay slot. |
| 1413 | } else { |
| 1414 | jalr(rs, zero_reg); |
Steve Block | 44f0eee | 2011-05-26 01:26:41 +0100 | [diff] [blame] | 1415 | } |
Andrei Popescu | 3100271 | 2010-02-23 13:46:05 +0000 | [diff] [blame] | 1416 | } |
| 1417 | |
| 1418 | |
| 1419 | void Assembler::jal(int32_t target) { |
Ben Murdoch | 589d697 | 2011-11-30 16:04:58 +0000 | [diff] [blame] | 1420 | #ifdef DEBUG |
| 1421 | // Get pc of delay slot. |
| 1422 | uint32_t ipc = reinterpret_cast<uint32_t>(pc_ + 1 * kInstrSize); |
Ben Murdoch | b8a8cc1 | 2014-11-26 15:28:44 +0000 | [diff] [blame] | 1423 | bool in_range = (ipc ^ static_cast<uint32_t>(target) >> |
| 1424 | (kImm26Bits + kImmFieldShift)) == 0; |
| 1425 | DCHECK(in_range && ((target & 3) == 0)); |
Ben Murdoch | 589d697 | 2011-11-30 16:04:58 +0000 | [diff] [blame] | 1426 | #endif |
Steve Block | 44f0eee | 2011-05-26 01:26:41 +0100 | [diff] [blame] | 1427 | positions_recorder()->WriteRecordedPositions(); |
Andrei Popescu | 3100271 | 2010-02-23 13:46:05 +0000 | [diff] [blame] | 1428 | GenInstrJump(JAL, target >> 2); |
| 1429 | } |
| 1430 | |
| 1431 | |
| 1432 | void Assembler::jalr(Register rs, Register rd) { |
Steve Block | 44f0eee | 2011-05-26 01:26:41 +0100 | [diff] [blame] | 1433 | BlockTrampolinePoolScope block_trampoline_pool(this); |
| 1434 | positions_recorder()->WriteRecordedPositions(); |
Andrei Popescu | 3100271 | 2010-02-23 13:46:05 +0000 | [diff] [blame] | 1435 | GenInstrRegister(SPECIAL, rs, zero_reg, rd, 0, JALR); |
Steve Block | 44f0eee | 2011-05-26 01:26:41 +0100 | [diff] [blame] | 1436 | BlockTrampolinePoolFor(1); // For associated delay slot. |
Andrei Popescu | 3100271 | 2010-02-23 13:46:05 +0000 | [diff] [blame] | 1437 | } |
| 1438 | |
| 1439 | |
Ben Murdoch | 589d697 | 2011-11-30 16:04:58 +0000 | [diff] [blame] | 1440 | void Assembler::j_or_jr(int32_t target, Register rs) { |
| 1441 | // Get pc of delay slot. |
| 1442 | uint32_t ipc = reinterpret_cast<uint32_t>(pc_ + 1 * kInstrSize); |
Ben Murdoch | b8a8cc1 | 2014-11-26 15:28:44 +0000 | [diff] [blame] | 1443 | bool in_range = (ipc ^ static_cast<uint32_t>(target) >> |
| 1444 | (kImm26Bits + kImmFieldShift)) == 0; |
Ben Murdoch | 589d697 | 2011-11-30 16:04:58 +0000 | [diff] [blame] | 1445 | if (in_range) { |
| 1446 | j(target); |
| 1447 | } else { |
| 1448 | jr(t9); |
| 1449 | } |
| 1450 | } |
| 1451 | |
| 1452 | |
| 1453 | void Assembler::jal_or_jalr(int32_t target, Register rs) { |
| 1454 | // Get pc of delay slot. |
| 1455 | uint32_t ipc = reinterpret_cast<uint32_t>(pc_ + 1 * kInstrSize); |
Ben Murdoch | b8a8cc1 | 2014-11-26 15:28:44 +0000 | [diff] [blame] | 1456 | bool in_range = (ipc ^ static_cast<uint32_t>(target) >> |
| 1457 | (kImm26Bits+kImmFieldShift)) == 0; |
Ben Murdoch | 589d697 | 2011-11-30 16:04:58 +0000 | [diff] [blame] | 1458 | if (in_range) { |
| 1459 | jal(target); |
| 1460 | } else { |
| 1461 | jalr(t9); |
| 1462 | } |
| 1463 | } |
| 1464 | |
| 1465 | |
Ben Murdoch | b8a8cc1 | 2014-11-26 15:28:44 +0000 | [diff] [blame] | 1466 | // -------Data-processing-instructions--------- |
Andrei Popescu | 3100271 | 2010-02-23 13:46:05 +0000 | [diff] [blame] | 1467 | |
| 1468 | // Arithmetic. |
| 1469 | |
Andrei Popescu | 3100271 | 2010-02-23 13:46:05 +0000 | [diff] [blame] | 1470 | void Assembler::addu(Register rd, Register rs, Register rt) { |
| 1471 | GenInstrRegister(SPECIAL, rs, rt, rd, 0, ADDU); |
| 1472 | } |
| 1473 | |
| 1474 | |
Andrei Popescu | 3100271 | 2010-02-23 13:46:05 +0000 | [diff] [blame] | 1475 | void Assembler::addiu(Register rd, Register rs, int32_t j) { |
| 1476 | GenInstrImmediate(ADDIU, rs, rd, j); |
Andrei Popescu | 3100271 | 2010-02-23 13:46:05 +0000 | [diff] [blame] | 1477 | } |
| 1478 | |
| 1479 | |
| 1480 | void Assembler::subu(Register rd, Register rs, Register rt) { |
| 1481 | GenInstrRegister(SPECIAL, rs, rt, rd, 0, SUBU); |
| 1482 | } |
| 1483 | |
| 1484 | |
| 1485 | void Assembler::mul(Register rd, Register rs, Register rt) { |
Ben Murdoch | b8a8cc1 | 2014-11-26 15:28:44 +0000 | [diff] [blame] | 1486 | if (!IsMipsArchVariant(kMips32r6)) { |
| 1487 | GenInstrRegister(SPECIAL2, rs, rt, rd, 0, MUL); |
| 1488 | } else { |
| 1489 | GenInstrRegister(SPECIAL, rs, rt, rd, MUL_OP, MUL_MUH); |
| 1490 | } |
| 1491 | } |
| 1492 | |
| 1493 | |
| 1494 | void Assembler::mulu(Register rd, Register rs, Register rt) { |
| 1495 | DCHECK(IsMipsArchVariant(kMips32r6)); |
| 1496 | GenInstrRegister(SPECIAL, rs, rt, rd, MUL_OP, MUL_MUH_U); |
| 1497 | } |
| 1498 | |
| 1499 | |
| 1500 | void Assembler::muh(Register rd, Register rs, Register rt) { |
| 1501 | DCHECK(IsMipsArchVariant(kMips32r6)); |
| 1502 | GenInstrRegister(SPECIAL, rs, rt, rd, MUH_OP, MUL_MUH); |
| 1503 | } |
| 1504 | |
| 1505 | |
| 1506 | void Assembler::muhu(Register rd, Register rs, Register rt) { |
| 1507 | DCHECK(IsMipsArchVariant(kMips32r6)); |
| 1508 | GenInstrRegister(SPECIAL, rs, rt, rd, MUH_OP, MUL_MUH_U); |
| 1509 | } |
| 1510 | |
| 1511 | |
| 1512 | void Assembler::mod(Register rd, Register rs, Register rt) { |
| 1513 | DCHECK(IsMipsArchVariant(kMips32r6)); |
| 1514 | GenInstrRegister(SPECIAL, rs, rt, rd, MOD_OP, DIV_MOD); |
| 1515 | } |
| 1516 | |
| 1517 | |
| 1518 | void Assembler::modu(Register rd, Register rs, Register rt) { |
| 1519 | DCHECK(IsMipsArchVariant(kMips32r6)); |
| 1520 | GenInstrRegister(SPECIAL, rs, rt, rd, MOD_OP, DIV_MOD_U); |
Andrei Popescu | 3100271 | 2010-02-23 13:46:05 +0000 | [diff] [blame] | 1521 | } |
| 1522 | |
| 1523 | |
| 1524 | void Assembler::mult(Register rs, Register rt) { |
| 1525 | GenInstrRegister(SPECIAL, rs, rt, zero_reg, 0, MULT); |
| 1526 | } |
| 1527 | |
| 1528 | |
| 1529 | void Assembler::multu(Register rs, Register rt) { |
| 1530 | GenInstrRegister(SPECIAL, rs, rt, zero_reg, 0, MULTU); |
| 1531 | } |
| 1532 | |
| 1533 | |
| 1534 | void Assembler::div(Register rs, Register rt) { |
| 1535 | GenInstrRegister(SPECIAL, rs, rt, zero_reg, 0, DIV); |
| 1536 | } |
| 1537 | |
| 1538 | |
Ben Murdoch | b8a8cc1 | 2014-11-26 15:28:44 +0000 | [diff] [blame] | 1539 | void Assembler::div(Register rd, Register rs, Register rt) { |
| 1540 | DCHECK(IsMipsArchVariant(kMips32r6)); |
| 1541 | GenInstrRegister(SPECIAL, rs, rt, rd, DIV_OP, DIV_MOD); |
| 1542 | } |
| 1543 | |
| 1544 | |
Andrei Popescu | 3100271 | 2010-02-23 13:46:05 +0000 | [diff] [blame] | 1545 | void Assembler::divu(Register rs, Register rt) { |
| 1546 | GenInstrRegister(SPECIAL, rs, rt, zero_reg, 0, DIVU); |
| 1547 | } |
| 1548 | |
| 1549 | |
Ben Murdoch | b8a8cc1 | 2014-11-26 15:28:44 +0000 | [diff] [blame] | 1550 | void Assembler::divu(Register rd, Register rs, Register rt) { |
| 1551 | DCHECK(IsMipsArchVariant(kMips32r6)); |
| 1552 | GenInstrRegister(SPECIAL, rs, rt, rd, DIV_OP, DIV_MOD_U); |
| 1553 | } |
| 1554 | |
| 1555 | |
Andrei Popescu | 3100271 | 2010-02-23 13:46:05 +0000 | [diff] [blame] | 1556 | // Logical. |
| 1557 | |
| 1558 | void Assembler::and_(Register rd, Register rs, Register rt) { |
| 1559 | GenInstrRegister(SPECIAL, rs, rt, rd, 0, AND); |
| 1560 | } |
| 1561 | |
| 1562 | |
| 1563 | void Assembler::andi(Register rt, Register rs, int32_t j) { |
Ben Murdoch | b8a8cc1 | 2014-11-26 15:28:44 +0000 | [diff] [blame] | 1564 | DCHECK(is_uint16(j)); |
Andrei Popescu | 3100271 | 2010-02-23 13:46:05 +0000 | [diff] [blame] | 1565 | GenInstrImmediate(ANDI, rs, rt, j); |
| 1566 | } |
| 1567 | |
| 1568 | |
| 1569 | void Assembler::or_(Register rd, Register rs, Register rt) { |
| 1570 | GenInstrRegister(SPECIAL, rs, rt, rd, 0, OR); |
| 1571 | } |
| 1572 | |
| 1573 | |
| 1574 | void Assembler::ori(Register rt, Register rs, int32_t j) { |
Ben Murdoch | b8a8cc1 | 2014-11-26 15:28:44 +0000 | [diff] [blame] | 1575 | DCHECK(is_uint16(j)); |
Andrei Popescu | 3100271 | 2010-02-23 13:46:05 +0000 | [diff] [blame] | 1576 | GenInstrImmediate(ORI, rs, rt, j); |
| 1577 | } |
| 1578 | |
| 1579 | |
| 1580 | void Assembler::xor_(Register rd, Register rs, Register rt) { |
| 1581 | GenInstrRegister(SPECIAL, rs, rt, rd, 0, XOR); |
| 1582 | } |
| 1583 | |
| 1584 | |
| 1585 | void Assembler::xori(Register rt, Register rs, int32_t j) { |
Ben Murdoch | b8a8cc1 | 2014-11-26 15:28:44 +0000 | [diff] [blame] | 1586 | DCHECK(is_uint16(j)); |
Andrei Popescu | 3100271 | 2010-02-23 13:46:05 +0000 | [diff] [blame] | 1587 | GenInstrImmediate(XORI, rs, rt, j); |
| 1588 | } |
| 1589 | |
| 1590 | |
| 1591 | void Assembler::nor(Register rd, Register rs, Register rt) { |
| 1592 | GenInstrRegister(SPECIAL, rs, rt, rd, 0, NOR); |
| 1593 | } |
| 1594 | |
| 1595 | |
| 1596 | // Shifts. |
Steve Block | 44f0eee | 2011-05-26 01:26:41 +0100 | [diff] [blame] | 1597 | void Assembler::sll(Register rd, |
| 1598 | Register rt, |
| 1599 | uint16_t sa, |
| 1600 | bool coming_from_nop) { |
| 1601 | // Don't allow nop instructions in the form sll zero_reg, zero_reg to be |
| 1602 | // generated using the sll instruction. They must be generated using |
| 1603 | // nop(int/NopMarkerTypes) or MarkCode(int/NopMarkerTypes) pseudo |
| 1604 | // instructions. |
Ben Murdoch | b8a8cc1 | 2014-11-26 15:28:44 +0000 | [diff] [blame] | 1605 | DCHECK(coming_from_nop || !(rd.is(zero_reg) && rt.is(zero_reg))); |
Andrei Popescu | 3100271 | 2010-02-23 13:46:05 +0000 | [diff] [blame] | 1606 | GenInstrRegister(SPECIAL, zero_reg, rt, rd, sa, SLL); |
| 1607 | } |
| 1608 | |
| 1609 | |
| 1610 | void Assembler::sllv(Register rd, Register rt, Register rs) { |
| 1611 | GenInstrRegister(SPECIAL, rs, rt, rd, 0, SLLV); |
| 1612 | } |
| 1613 | |
| 1614 | |
| 1615 | void Assembler::srl(Register rd, Register rt, uint16_t sa) { |
| 1616 | GenInstrRegister(SPECIAL, zero_reg, rt, rd, sa, SRL); |
| 1617 | } |
| 1618 | |
| 1619 | |
| 1620 | void Assembler::srlv(Register rd, Register rt, Register rs) { |
| 1621 | GenInstrRegister(SPECIAL, rs, rt, rd, 0, SRLV); |
| 1622 | } |
| 1623 | |
| 1624 | |
| 1625 | void Assembler::sra(Register rd, Register rt, uint16_t sa) { |
| 1626 | GenInstrRegister(SPECIAL, zero_reg, rt, rd, sa, SRA); |
| 1627 | } |
| 1628 | |
| 1629 | |
| 1630 | void Assembler::srav(Register rd, Register rt, Register rs) { |
| 1631 | GenInstrRegister(SPECIAL, rs, rt, rd, 0, SRAV); |
| 1632 | } |
| 1633 | |
| 1634 | |
Steve Block | 44f0eee | 2011-05-26 01:26:41 +0100 | [diff] [blame] | 1635 | void Assembler::rotr(Register rd, Register rt, uint16_t sa) { |
| 1636 | // Should be called via MacroAssembler::Ror. |
Ben Murdoch | b8a8cc1 | 2014-11-26 15:28:44 +0000 | [diff] [blame] | 1637 | DCHECK(rd.is_valid() && rt.is_valid() && is_uint5(sa)); |
| 1638 | DCHECK(IsMipsArchVariant(kMips32r2)); |
Steve Block | 44f0eee | 2011-05-26 01:26:41 +0100 | [diff] [blame] | 1639 | Instr instr = SPECIAL | (1 << kRsShift) | (rt.code() << kRtShift) |
| 1640 | | (rd.code() << kRdShift) | (sa << kSaShift) | SRL; |
| 1641 | emit(instr); |
| 1642 | } |
| 1643 | |
| 1644 | |
| 1645 | void Assembler::rotrv(Register rd, Register rt, Register rs) { |
| 1646 | // Should be called via MacroAssembler::Ror. |
Ben Murdoch | b8a8cc1 | 2014-11-26 15:28:44 +0000 | [diff] [blame] | 1647 | DCHECK(rd.is_valid() && rt.is_valid() && rs.is_valid() ); |
| 1648 | DCHECK(IsMipsArchVariant(kMips32r2)); |
Steve Block | 44f0eee | 2011-05-26 01:26:41 +0100 | [diff] [blame] | 1649 | Instr instr = SPECIAL | (rs.code() << kRsShift) | (rt.code() << kRtShift) |
| 1650 | | (rd.code() << kRdShift) | (1 << kSaShift) | SRLV; |
| 1651 | emit(instr); |
| 1652 | } |
| 1653 | |
| 1654 | |
Ben Murdoch | b8a8cc1 | 2014-11-26 15:28:44 +0000 | [diff] [blame] | 1655 | // ------------Memory-instructions------------- |
Andrei Popescu | 3100271 | 2010-02-23 13:46:05 +0000 | [diff] [blame] | 1656 | |
Steve Block | 44f0eee | 2011-05-26 01:26:41 +0100 | [diff] [blame] | 1657 | // Helper for base-reg + offset, when offset is larger than int16. |
| 1658 | void Assembler::LoadRegPlusOffsetToAt(const MemOperand& src) { |
Ben Murdoch | b8a8cc1 | 2014-11-26 15:28:44 +0000 | [diff] [blame] | 1659 | DCHECK(!src.rm().is(at)); |
| 1660 | lui(at, (src.offset_ >> kLuiShift) & kImm16Mask); |
Steve Block | 44f0eee | 2011-05-26 01:26:41 +0100 | [diff] [blame] | 1661 | ori(at, at, src.offset_ & kImm16Mask); // Load 32-bit offset. |
| 1662 | addu(at, at, src.rm()); // Add base register. |
| 1663 | } |
| 1664 | |
| 1665 | |
Andrei Popescu | 3100271 | 2010-02-23 13:46:05 +0000 | [diff] [blame] | 1666 | void Assembler::lb(Register rd, const MemOperand& rs) { |
Steve Block | 44f0eee | 2011-05-26 01:26:41 +0100 | [diff] [blame] | 1667 | if (is_int16(rs.offset_)) { |
| 1668 | GenInstrImmediate(LB, rs.rm(), rd, rs.offset_); |
| 1669 | } else { // Offset > 16 bits, use multiple instructions to load. |
| 1670 | LoadRegPlusOffsetToAt(rs); |
| 1671 | GenInstrImmediate(LB, at, rd, 0); // Equiv to lb(rd, MemOperand(at, 0)); |
| 1672 | } |
Andrei Popescu | 3100271 | 2010-02-23 13:46:05 +0000 | [diff] [blame] | 1673 | } |
| 1674 | |
| 1675 | |
| 1676 | void Assembler::lbu(Register rd, const MemOperand& rs) { |
Steve Block | 44f0eee | 2011-05-26 01:26:41 +0100 | [diff] [blame] | 1677 | if (is_int16(rs.offset_)) { |
| 1678 | GenInstrImmediate(LBU, rs.rm(), rd, rs.offset_); |
| 1679 | } else { // Offset > 16 bits, use multiple instructions to load. |
| 1680 | LoadRegPlusOffsetToAt(rs); |
| 1681 | GenInstrImmediate(LBU, at, rd, 0); // Equiv to lbu(rd, MemOperand(at, 0)); |
| 1682 | } |
| 1683 | } |
| 1684 | |
| 1685 | |
| 1686 | void Assembler::lh(Register rd, const MemOperand& rs) { |
| 1687 | if (is_int16(rs.offset_)) { |
| 1688 | GenInstrImmediate(LH, rs.rm(), rd, rs.offset_); |
| 1689 | } else { // Offset > 16 bits, use multiple instructions to load. |
| 1690 | LoadRegPlusOffsetToAt(rs); |
| 1691 | GenInstrImmediate(LH, at, rd, 0); // Equiv to lh(rd, MemOperand(at, 0)); |
| 1692 | } |
| 1693 | } |
| 1694 | |
| 1695 | |
| 1696 | void Assembler::lhu(Register rd, const MemOperand& rs) { |
| 1697 | if (is_int16(rs.offset_)) { |
| 1698 | GenInstrImmediate(LHU, rs.rm(), rd, rs.offset_); |
| 1699 | } else { // Offset > 16 bits, use multiple instructions to load. |
| 1700 | LoadRegPlusOffsetToAt(rs); |
| 1701 | GenInstrImmediate(LHU, at, rd, 0); // Equiv to lhu(rd, MemOperand(at, 0)); |
| 1702 | } |
Andrei Popescu | 3100271 | 2010-02-23 13:46:05 +0000 | [diff] [blame] | 1703 | } |
| 1704 | |
| 1705 | |
| 1706 | void Assembler::lw(Register rd, const MemOperand& rs) { |
Steve Block | 44f0eee | 2011-05-26 01:26:41 +0100 | [diff] [blame] | 1707 | if (is_int16(rs.offset_)) { |
| 1708 | GenInstrImmediate(LW, rs.rm(), rd, rs.offset_); |
| 1709 | } else { // Offset > 16 bits, use multiple instructions to load. |
| 1710 | LoadRegPlusOffsetToAt(rs); |
| 1711 | GenInstrImmediate(LW, at, rd, 0); // Equiv to lw(rd, MemOperand(at, 0)); |
| 1712 | } |
Steve Block | 44f0eee | 2011-05-26 01:26:41 +0100 | [diff] [blame] | 1713 | } |
| 1714 | |
| 1715 | |
| 1716 | void Assembler::lwl(Register rd, const MemOperand& rs) { |
| 1717 | GenInstrImmediate(LWL, rs.rm(), rd, rs.offset_); |
| 1718 | } |
| 1719 | |
| 1720 | |
| 1721 | void Assembler::lwr(Register rd, const MemOperand& rs) { |
| 1722 | GenInstrImmediate(LWR, rs.rm(), rd, rs.offset_); |
Andrei Popescu | 3100271 | 2010-02-23 13:46:05 +0000 | [diff] [blame] | 1723 | } |
| 1724 | |
| 1725 | |
| 1726 | void Assembler::sb(Register rd, const MemOperand& rs) { |
Steve Block | 44f0eee | 2011-05-26 01:26:41 +0100 | [diff] [blame] | 1727 | if (is_int16(rs.offset_)) { |
| 1728 | GenInstrImmediate(SB, rs.rm(), rd, rs.offset_); |
| 1729 | } else { // Offset > 16 bits, use multiple instructions to store. |
| 1730 | LoadRegPlusOffsetToAt(rs); |
| 1731 | GenInstrImmediate(SB, at, rd, 0); // Equiv to sb(rd, MemOperand(at, 0)); |
| 1732 | } |
| 1733 | } |
| 1734 | |
| 1735 | |
| 1736 | void Assembler::sh(Register rd, const MemOperand& rs) { |
| 1737 | if (is_int16(rs.offset_)) { |
| 1738 | GenInstrImmediate(SH, rs.rm(), rd, rs.offset_); |
| 1739 | } else { // Offset > 16 bits, use multiple instructions to store. |
| 1740 | LoadRegPlusOffsetToAt(rs); |
| 1741 | GenInstrImmediate(SH, at, rd, 0); // Equiv to sh(rd, MemOperand(at, 0)); |
| 1742 | } |
Andrei Popescu | 3100271 | 2010-02-23 13:46:05 +0000 | [diff] [blame] | 1743 | } |
| 1744 | |
| 1745 | |
| 1746 | void Assembler::sw(Register rd, const MemOperand& rs) { |
Steve Block | 44f0eee | 2011-05-26 01:26:41 +0100 | [diff] [blame] | 1747 | if (is_int16(rs.offset_)) { |
| 1748 | GenInstrImmediate(SW, rs.rm(), rd, rs.offset_); |
| 1749 | } else { // Offset > 16 bits, use multiple instructions to store. |
| 1750 | LoadRegPlusOffsetToAt(rs); |
| 1751 | GenInstrImmediate(SW, at, rd, 0); // Equiv to sw(rd, MemOperand(at, 0)); |
| 1752 | } |
Steve Block | 44f0eee | 2011-05-26 01:26:41 +0100 | [diff] [blame] | 1753 | } |
| 1754 | |
| 1755 | |
| 1756 | void Assembler::swl(Register rd, const MemOperand& rs) { |
| 1757 | GenInstrImmediate(SWL, rs.rm(), rd, rs.offset_); |
| 1758 | } |
| 1759 | |
| 1760 | |
| 1761 | void Assembler::swr(Register rd, const MemOperand& rs) { |
| 1762 | GenInstrImmediate(SWR, rs.rm(), rd, rs.offset_); |
Andrei Popescu | 3100271 | 2010-02-23 13:46:05 +0000 | [diff] [blame] | 1763 | } |
| 1764 | |
| 1765 | |
| 1766 | void Assembler::lui(Register rd, int32_t j) { |
Ben Murdoch | b8a8cc1 | 2014-11-26 15:28:44 +0000 | [diff] [blame] | 1767 | DCHECK(is_uint16(j)); |
Andrei Popescu | 3100271 | 2010-02-23 13:46:05 +0000 | [diff] [blame] | 1768 | GenInstrImmediate(LUI, zero_reg, rd, j); |
| 1769 | } |
| 1770 | |
| 1771 | |
Ben Murdoch | b8a8cc1 | 2014-11-26 15:28:44 +0000 | [diff] [blame] | 1772 | void Assembler::aui(Register rs, Register rt, int32_t j) { |
| 1773 | // This instruction uses same opcode as 'lui'. The difference in encoding is |
| 1774 | // 'lui' has zero reg. for rs field. |
| 1775 | DCHECK(is_uint16(j)); |
| 1776 | GenInstrImmediate(LUI, rs, rt, j); |
| 1777 | } |
| 1778 | |
| 1779 | |
| 1780 | // -------------Misc-instructions-------------- |
Andrei Popescu | 3100271 | 2010-02-23 13:46:05 +0000 | [diff] [blame] | 1781 | |
| 1782 | // Break / Trap instructions. |
Ben Murdoch | 3fb3ca8 | 2011-12-02 17:19:32 +0000 | [diff] [blame] | 1783 | void Assembler::break_(uint32_t code, bool break_as_stop) { |
Ben Murdoch | b8a8cc1 | 2014-11-26 15:28:44 +0000 | [diff] [blame] | 1784 | DCHECK((code & ~0xfffff) == 0); |
Ben Murdoch | 3fb3ca8 | 2011-12-02 17:19:32 +0000 | [diff] [blame] | 1785 | // We need to invalidate breaks that could be stops as well because the |
| 1786 | // simulator expects a char pointer after the stop instruction. |
| 1787 | // See constants-mips.h for explanation. |
Ben Murdoch | b8a8cc1 | 2014-11-26 15:28:44 +0000 | [diff] [blame] | 1788 | DCHECK((break_as_stop && |
Ben Murdoch | 3fb3ca8 | 2011-12-02 17:19:32 +0000 | [diff] [blame] | 1789 | code <= kMaxStopCode && |
| 1790 | code > kMaxWatchpointCode) || |
| 1791 | (!break_as_stop && |
| 1792 | (code > kMaxStopCode || |
| 1793 | code <= kMaxWatchpointCode))); |
Andrei Popescu | 3100271 | 2010-02-23 13:46:05 +0000 | [diff] [blame] | 1794 | Instr break_instr = SPECIAL | BREAK | (code << 6); |
| 1795 | emit(break_instr); |
| 1796 | } |
| 1797 | |
| 1798 | |
Ben Murdoch | 3fb3ca8 | 2011-12-02 17:19:32 +0000 | [diff] [blame] | 1799 | void Assembler::stop(const char* msg, uint32_t code) { |
Ben Murdoch | b8a8cc1 | 2014-11-26 15:28:44 +0000 | [diff] [blame] | 1800 | DCHECK(code > kMaxWatchpointCode); |
| 1801 | DCHECK(code <= kMaxStopCode); |
| 1802 | #if V8_HOST_ARCH_MIPS |
Ben Murdoch | 3fb3ca8 | 2011-12-02 17:19:32 +0000 | [diff] [blame] | 1803 | break_(0x54321); |
| 1804 | #else // V8_HOST_ARCH_MIPS |
| 1805 | BlockTrampolinePoolFor(2); |
| 1806 | // The Simulator will handle the stop instruction and get the message address. |
| 1807 | // On MIPS stop() is just a special kind of break_(). |
| 1808 | break_(code, true); |
| 1809 | emit(reinterpret_cast<Instr>(msg)); |
| 1810 | #endif |
| 1811 | } |
| 1812 | |
| 1813 | |
Andrei Popescu | 3100271 | 2010-02-23 13:46:05 +0000 | [diff] [blame] | 1814 | void Assembler::tge(Register rs, Register rt, uint16_t code) { |
Ben Murdoch | b8a8cc1 | 2014-11-26 15:28:44 +0000 | [diff] [blame] | 1815 | DCHECK(is_uint10(code)); |
Andrei Popescu | 3100271 | 2010-02-23 13:46:05 +0000 | [diff] [blame] | 1816 | Instr instr = SPECIAL | TGE | rs.code() << kRsShift |
| 1817 | | rt.code() << kRtShift | code << 6; |
| 1818 | emit(instr); |
| 1819 | } |
| 1820 | |
| 1821 | |
| 1822 | void Assembler::tgeu(Register rs, Register rt, uint16_t code) { |
Ben Murdoch | b8a8cc1 | 2014-11-26 15:28:44 +0000 | [diff] [blame] | 1823 | DCHECK(is_uint10(code)); |
Andrei Popescu | 3100271 | 2010-02-23 13:46:05 +0000 | [diff] [blame] | 1824 | Instr instr = SPECIAL | TGEU | rs.code() << kRsShift |
| 1825 | | rt.code() << kRtShift | code << 6; |
| 1826 | emit(instr); |
| 1827 | } |
| 1828 | |
| 1829 | |
| 1830 | void Assembler::tlt(Register rs, Register rt, uint16_t code) { |
Ben Murdoch | b8a8cc1 | 2014-11-26 15:28:44 +0000 | [diff] [blame] | 1831 | DCHECK(is_uint10(code)); |
Andrei Popescu | 3100271 | 2010-02-23 13:46:05 +0000 | [diff] [blame] | 1832 | Instr instr = |
| 1833 | SPECIAL | TLT | rs.code() << kRsShift | rt.code() << kRtShift | code << 6; |
| 1834 | emit(instr); |
| 1835 | } |
| 1836 | |
| 1837 | |
| 1838 | void Assembler::tltu(Register rs, Register rt, uint16_t code) { |
Ben Murdoch | b8a8cc1 | 2014-11-26 15:28:44 +0000 | [diff] [blame] | 1839 | DCHECK(is_uint10(code)); |
Steve Block | 44f0eee | 2011-05-26 01:26:41 +0100 | [diff] [blame] | 1840 | Instr instr = |
| 1841 | SPECIAL | TLTU | rs.code() << kRsShift |
Andrei Popescu | 3100271 | 2010-02-23 13:46:05 +0000 | [diff] [blame] | 1842 | | rt.code() << kRtShift | code << 6; |
| 1843 | emit(instr); |
| 1844 | } |
| 1845 | |
| 1846 | |
| 1847 | void Assembler::teq(Register rs, Register rt, uint16_t code) { |
Ben Murdoch | b8a8cc1 | 2014-11-26 15:28:44 +0000 | [diff] [blame] | 1848 | DCHECK(is_uint10(code)); |
Andrei Popescu | 3100271 | 2010-02-23 13:46:05 +0000 | [diff] [blame] | 1849 | Instr instr = |
| 1850 | SPECIAL | TEQ | rs.code() << kRsShift | rt.code() << kRtShift | code << 6; |
| 1851 | emit(instr); |
| 1852 | } |
| 1853 | |
| 1854 | |
| 1855 | void Assembler::tne(Register rs, Register rt, uint16_t code) { |
Ben Murdoch | b8a8cc1 | 2014-11-26 15:28:44 +0000 | [diff] [blame] | 1856 | DCHECK(is_uint10(code)); |
Andrei Popescu | 3100271 | 2010-02-23 13:46:05 +0000 | [diff] [blame] | 1857 | Instr instr = |
| 1858 | SPECIAL | TNE | rs.code() << kRsShift | rt.code() << kRtShift | code << 6; |
| 1859 | emit(instr); |
| 1860 | } |
| 1861 | |
| 1862 | |
| 1863 | // Move from HI/LO register. |
| 1864 | |
| 1865 | void Assembler::mfhi(Register rd) { |
| 1866 | GenInstrRegister(SPECIAL, zero_reg, zero_reg, rd, 0, MFHI); |
| 1867 | } |
| 1868 | |
| 1869 | |
| 1870 | void Assembler::mflo(Register rd) { |
| 1871 | GenInstrRegister(SPECIAL, zero_reg, zero_reg, rd, 0, MFLO); |
| 1872 | } |
| 1873 | |
| 1874 | |
| 1875 | // Set on less than instructions. |
| 1876 | void Assembler::slt(Register rd, Register rs, Register rt) { |
| 1877 | GenInstrRegister(SPECIAL, rs, rt, rd, 0, SLT); |
| 1878 | } |
| 1879 | |
| 1880 | |
| 1881 | void Assembler::sltu(Register rd, Register rs, Register rt) { |
| 1882 | GenInstrRegister(SPECIAL, rs, rt, rd, 0, SLTU); |
| 1883 | } |
| 1884 | |
| 1885 | |
| 1886 | void Assembler::slti(Register rt, Register rs, int32_t j) { |
| 1887 | GenInstrImmediate(SLTI, rs, rt, j); |
| 1888 | } |
| 1889 | |
| 1890 | |
| 1891 | void Assembler::sltiu(Register rt, Register rs, int32_t j) { |
| 1892 | GenInstrImmediate(SLTIU, rs, rt, j); |
| 1893 | } |
| 1894 | |
| 1895 | |
Steve Block | 44f0eee | 2011-05-26 01:26:41 +0100 | [diff] [blame] | 1896 | // Conditional move. |
| 1897 | void Assembler::movz(Register rd, Register rs, Register rt) { |
| 1898 | GenInstrRegister(SPECIAL, rs, rt, rd, 0, MOVZ); |
| 1899 | } |
| 1900 | |
| 1901 | |
| 1902 | void Assembler::movn(Register rd, Register rs, Register rt) { |
| 1903 | GenInstrRegister(SPECIAL, rs, rt, rd, 0, MOVN); |
| 1904 | } |
| 1905 | |
| 1906 | |
| 1907 | void Assembler::movt(Register rd, Register rs, uint16_t cc) { |
| 1908 | Register rt; |
Ben Murdoch | 257744e | 2011-11-30 15:57:28 +0000 | [diff] [blame] | 1909 | rt.code_ = (cc & 0x0007) << 2 | 1; |
Steve Block | 44f0eee | 2011-05-26 01:26:41 +0100 | [diff] [blame] | 1910 | GenInstrRegister(SPECIAL, rs, rt, rd, 0, MOVCI); |
| 1911 | } |
| 1912 | |
| 1913 | |
| 1914 | void Assembler::movf(Register rd, Register rs, uint16_t cc) { |
| 1915 | Register rt; |
Ben Murdoch | 257744e | 2011-11-30 15:57:28 +0000 | [diff] [blame] | 1916 | rt.code_ = (cc & 0x0007) << 2 | 0; |
Steve Block | 44f0eee | 2011-05-26 01:26:41 +0100 | [diff] [blame] | 1917 | GenInstrRegister(SPECIAL, rs, rt, rd, 0, MOVCI); |
| 1918 | } |
| 1919 | |
| 1920 | |
| 1921 | // Bit twiddling. |
| 1922 | void Assembler::clz(Register rd, Register rs) { |
Ben Murdoch | b8a8cc1 | 2014-11-26 15:28:44 +0000 | [diff] [blame] | 1923 | if (!IsMipsArchVariant(kMips32r6)) { |
| 1924 | // Clz instr requires same GPR number in 'rd' and 'rt' fields. |
| 1925 | GenInstrRegister(SPECIAL2, rs, rd, rd, 0, CLZ); |
| 1926 | } else { |
| 1927 | GenInstrRegister(SPECIAL, rs, zero_reg, rd, 1, CLZ_R6); |
| 1928 | } |
Steve Block | 44f0eee | 2011-05-26 01:26:41 +0100 | [diff] [blame] | 1929 | } |
| 1930 | |
| 1931 | |
| 1932 | void Assembler::ins_(Register rt, Register rs, uint16_t pos, uint16_t size) { |
| 1933 | // Should be called via MacroAssembler::Ins. |
| 1934 | // Ins instr has 'rt' field as dest, and two uint5: msb, lsb. |
Ben Murdoch | b8a8cc1 | 2014-11-26 15:28:44 +0000 | [diff] [blame] | 1935 | DCHECK(IsMipsArchVariant(kMips32r2) || IsMipsArchVariant(kMips32r6)); |
Steve Block | 44f0eee | 2011-05-26 01:26:41 +0100 | [diff] [blame] | 1936 | GenInstrRegister(SPECIAL3, rs, rt, pos + size - 1, pos, INS); |
| 1937 | } |
| 1938 | |
| 1939 | |
| 1940 | void Assembler::ext_(Register rt, Register rs, uint16_t pos, uint16_t size) { |
| 1941 | // Should be called via MacroAssembler::Ext. |
| 1942 | // Ext instr has 'rt' field as dest, and two uint5: msb, lsb. |
Ben Murdoch | b8a8cc1 | 2014-11-26 15:28:44 +0000 | [diff] [blame] | 1943 | DCHECK(IsMipsArchVariant(kMips32r2) || IsMipsArchVariant(kMips32r6)); |
Steve Block | 44f0eee | 2011-05-26 01:26:41 +0100 | [diff] [blame] | 1944 | GenInstrRegister(SPECIAL3, rs, rt, size - 1, pos, EXT); |
| 1945 | } |
| 1946 | |
| 1947 | |
Ben Murdoch | b8a8cc1 | 2014-11-26 15:28:44 +0000 | [diff] [blame] | 1948 | void Assembler::pref(int32_t hint, const MemOperand& rs) { |
| 1949 | DCHECK(!IsMipsArchVariant(kLoongson)); |
| 1950 | DCHECK(is_uint5(hint) && is_uint16(rs.offset_)); |
| 1951 | Instr instr = PREF | (rs.rm().code() << kRsShift) | (hint << kRtShift) |
| 1952 | | (rs.offset_); |
| 1953 | emit(instr); |
| 1954 | } |
| 1955 | |
| 1956 | |
| 1957 | // --------Coprocessor-instructions---------------- |
Andrei Popescu | 3100271 | 2010-02-23 13:46:05 +0000 | [diff] [blame] | 1958 | |
| 1959 | // Load, store, move. |
| 1960 | void Assembler::lwc1(FPURegister fd, const MemOperand& src) { |
| 1961 | GenInstrImmediate(LWC1, src.rm(), fd, src.offset_); |
| 1962 | } |
| 1963 | |
| 1964 | |
| 1965 | void Assembler::ldc1(FPURegister fd, const MemOperand& src) { |
Steve Block | 44f0eee | 2011-05-26 01:26:41 +0100 | [diff] [blame] | 1966 | // Workaround for non-8-byte alignment of HeapNumber, convert 64-bit |
| 1967 | // load to two 32-bit loads. |
Ben Murdoch | b8a8cc1 | 2014-11-26 15:28:44 +0000 | [diff] [blame] | 1968 | if (IsFp64Mode()) { |
| 1969 | GenInstrImmediate(LWC1, src.rm(), fd, src.offset_ + |
| 1970 | Register::kMantissaOffset); |
| 1971 | GenInstrImmediate(LW, src.rm(), at, src.offset_ + |
| 1972 | Register::kExponentOffset); |
| 1973 | mthc1(at, fd); |
| 1974 | } else { |
| 1975 | GenInstrImmediate(LWC1, src.rm(), fd, src.offset_ + |
| 1976 | Register::kMantissaOffset); |
| 1977 | FPURegister nextfpreg; |
| 1978 | nextfpreg.setcode(fd.code() + 1); |
| 1979 | GenInstrImmediate(LWC1, src.rm(), nextfpreg, src.offset_ + |
| 1980 | Register::kExponentOffset); |
| 1981 | } |
Andrei Popescu | 3100271 | 2010-02-23 13:46:05 +0000 | [diff] [blame] | 1982 | } |
| 1983 | |
| 1984 | |
| 1985 | void Assembler::swc1(FPURegister fd, const MemOperand& src) { |
| 1986 | GenInstrImmediate(SWC1, src.rm(), fd, src.offset_); |
| 1987 | } |
| 1988 | |
| 1989 | |
| 1990 | void Assembler::sdc1(FPURegister fd, const MemOperand& src) { |
Steve Block | 44f0eee | 2011-05-26 01:26:41 +0100 | [diff] [blame] | 1991 | // Workaround for non-8-byte alignment of HeapNumber, convert 64-bit |
| 1992 | // store to two 32-bit stores. |
Ben Murdoch | b8a8cc1 | 2014-11-26 15:28:44 +0000 | [diff] [blame] | 1993 | if (IsFp64Mode()) { |
| 1994 | GenInstrImmediate(SWC1, src.rm(), fd, src.offset_ + |
| 1995 | Register::kMantissaOffset); |
| 1996 | mfhc1(at, fd); |
| 1997 | GenInstrImmediate(SW, src.rm(), at, src.offset_ + |
| 1998 | Register::kExponentOffset); |
| 1999 | } else { |
| 2000 | GenInstrImmediate(SWC1, src.rm(), fd, src.offset_ + |
| 2001 | Register::kMantissaOffset); |
| 2002 | FPURegister nextfpreg; |
| 2003 | nextfpreg.setcode(fd.code() + 1); |
| 2004 | GenInstrImmediate(SWC1, src.rm(), nextfpreg, src.offset_ + |
| 2005 | Register::kExponentOffset); |
| 2006 | } |
Andrei Popescu | 3100271 | 2010-02-23 13:46:05 +0000 | [diff] [blame] | 2007 | } |
| 2008 | |
| 2009 | |
Steve Block | 44f0eee | 2011-05-26 01:26:41 +0100 | [diff] [blame] | 2010 | void Assembler::mtc1(Register rt, FPURegister fs) { |
Andrei Popescu | 3100271 | 2010-02-23 13:46:05 +0000 | [diff] [blame] | 2011 | GenInstrRegister(COP1, MTC1, rt, fs, f0); |
| 2012 | } |
| 2013 | |
| 2014 | |
Ben Murdoch | b8a8cc1 | 2014-11-26 15:28:44 +0000 | [diff] [blame] | 2015 | void Assembler::mthc1(Register rt, FPURegister fs) { |
| 2016 | GenInstrRegister(COP1, MTHC1, rt, fs, f0); |
| 2017 | } |
| 2018 | |
| 2019 | |
Steve Block | 44f0eee | 2011-05-26 01:26:41 +0100 | [diff] [blame] | 2020 | void Assembler::mfc1(Register rt, FPURegister fs) { |
Andrei Popescu | 3100271 | 2010-02-23 13:46:05 +0000 | [diff] [blame] | 2021 | GenInstrRegister(COP1, MFC1, rt, fs, f0); |
| 2022 | } |
| 2023 | |
| 2024 | |
Ben Murdoch | b8a8cc1 | 2014-11-26 15:28:44 +0000 | [diff] [blame] | 2025 | void Assembler::mfhc1(Register rt, FPURegister fs) { |
| 2026 | GenInstrRegister(COP1, MFHC1, rt, fs, f0); |
| 2027 | } |
| 2028 | |
| 2029 | |
Steve Block | 44f0eee | 2011-05-26 01:26:41 +0100 | [diff] [blame] | 2030 | void Assembler::ctc1(Register rt, FPUControlRegister fs) { |
| 2031 | GenInstrRegister(COP1, CTC1, rt, fs); |
| 2032 | } |
| 2033 | |
| 2034 | |
| 2035 | void Assembler::cfc1(Register rt, FPUControlRegister fs) { |
| 2036 | GenInstrRegister(COP1, CFC1, rt, fs); |
| 2037 | } |
| 2038 | |
Ben Murdoch | b8a8cc1 | 2014-11-26 15:28:44 +0000 | [diff] [blame] | 2039 | |
Ben Murdoch | 589d697 | 2011-11-30 16:04:58 +0000 | [diff] [blame] | 2040 | void Assembler::DoubleAsTwoUInt32(double d, uint32_t* lo, uint32_t* hi) { |
| 2041 | uint64_t i; |
| 2042 | memcpy(&i, &d, 8); |
| 2043 | |
| 2044 | *lo = i & 0xffffffff; |
| 2045 | *hi = i >> 32; |
| 2046 | } |
Steve Block | 44f0eee | 2011-05-26 01:26:41 +0100 | [diff] [blame] | 2047 | |
Ben Murdoch | b8a8cc1 | 2014-11-26 15:28:44 +0000 | [diff] [blame] | 2048 | |
Steve Block | 44f0eee | 2011-05-26 01:26:41 +0100 | [diff] [blame] | 2049 | // Arithmetic. |
| 2050 | |
| 2051 | void Assembler::add_d(FPURegister fd, FPURegister fs, FPURegister ft) { |
| 2052 | GenInstrRegister(COP1, D, ft, fs, fd, ADD_D); |
| 2053 | } |
| 2054 | |
| 2055 | |
| 2056 | void Assembler::sub_d(FPURegister fd, FPURegister fs, FPURegister ft) { |
| 2057 | GenInstrRegister(COP1, D, ft, fs, fd, SUB_D); |
| 2058 | } |
| 2059 | |
| 2060 | |
| 2061 | void Assembler::mul_d(FPURegister fd, FPURegister fs, FPURegister ft) { |
| 2062 | GenInstrRegister(COP1, D, ft, fs, fd, MUL_D); |
| 2063 | } |
| 2064 | |
| 2065 | |
Ben Murdoch | b8a8cc1 | 2014-11-26 15:28:44 +0000 | [diff] [blame] | 2066 | void Assembler::madd_d(FPURegister fd, FPURegister fr, FPURegister fs, |
| 2067 | FPURegister ft) { |
Emily Bernier | d0a1eb7 | 2015-03-24 16:35:39 -0400 | [diff] [blame^] | 2068 | DCHECK(IsMipsArchVariant(kMips32r2)); |
Ben Murdoch | b8a8cc1 | 2014-11-26 15:28:44 +0000 | [diff] [blame] | 2069 | GenInstrRegister(COP1X, fr, ft, fs, fd, MADD_D); |
| 2070 | } |
| 2071 | |
| 2072 | |
Steve Block | 44f0eee | 2011-05-26 01:26:41 +0100 | [diff] [blame] | 2073 | void Assembler::div_d(FPURegister fd, FPURegister fs, FPURegister ft) { |
| 2074 | GenInstrRegister(COP1, D, ft, fs, fd, DIV_D); |
| 2075 | } |
| 2076 | |
| 2077 | |
| 2078 | void Assembler::abs_d(FPURegister fd, FPURegister fs) { |
| 2079 | GenInstrRegister(COP1, D, f0, fs, fd, ABS_D); |
| 2080 | } |
| 2081 | |
| 2082 | |
| 2083 | void Assembler::mov_d(FPURegister fd, FPURegister fs) { |
| 2084 | GenInstrRegister(COP1, D, f0, fs, fd, MOV_D); |
| 2085 | } |
| 2086 | |
| 2087 | |
| 2088 | void Assembler::neg_d(FPURegister fd, FPURegister fs) { |
| 2089 | GenInstrRegister(COP1, D, f0, fs, fd, NEG_D); |
| 2090 | } |
| 2091 | |
| 2092 | |
| 2093 | void Assembler::sqrt_d(FPURegister fd, FPURegister fs) { |
| 2094 | GenInstrRegister(COP1, D, f0, fs, fd, SQRT_D); |
Andrei Popescu | 3100271 | 2010-02-23 13:46:05 +0000 | [diff] [blame] | 2095 | } |
| 2096 | |
| 2097 | |
| 2098 | // Conversions. |
| 2099 | |
| 2100 | void Assembler::cvt_w_s(FPURegister fd, FPURegister fs) { |
| 2101 | GenInstrRegister(COP1, S, f0, fs, fd, CVT_W_S); |
| 2102 | } |
| 2103 | |
| 2104 | |
| 2105 | void Assembler::cvt_w_d(FPURegister fd, FPURegister fs) { |
| 2106 | GenInstrRegister(COP1, D, f0, fs, fd, CVT_W_D); |
| 2107 | } |
| 2108 | |
| 2109 | |
Steve Block | 44f0eee | 2011-05-26 01:26:41 +0100 | [diff] [blame] | 2110 | void Assembler::trunc_w_s(FPURegister fd, FPURegister fs) { |
| 2111 | GenInstrRegister(COP1, S, f0, fs, fd, TRUNC_W_S); |
| 2112 | } |
| 2113 | |
| 2114 | |
| 2115 | void Assembler::trunc_w_d(FPURegister fd, FPURegister fs) { |
| 2116 | GenInstrRegister(COP1, D, f0, fs, fd, TRUNC_W_D); |
| 2117 | } |
| 2118 | |
| 2119 | |
| 2120 | void Assembler::round_w_s(FPURegister fd, FPURegister fs) { |
| 2121 | GenInstrRegister(COP1, S, f0, fs, fd, ROUND_W_S); |
| 2122 | } |
| 2123 | |
| 2124 | |
| 2125 | void Assembler::round_w_d(FPURegister fd, FPURegister fs) { |
| 2126 | GenInstrRegister(COP1, D, f0, fs, fd, ROUND_W_D); |
| 2127 | } |
| 2128 | |
| 2129 | |
| 2130 | void Assembler::floor_w_s(FPURegister fd, FPURegister fs) { |
| 2131 | GenInstrRegister(COP1, S, f0, fs, fd, FLOOR_W_S); |
| 2132 | } |
| 2133 | |
| 2134 | |
| 2135 | void Assembler::floor_w_d(FPURegister fd, FPURegister fs) { |
| 2136 | GenInstrRegister(COP1, D, f0, fs, fd, FLOOR_W_D); |
| 2137 | } |
| 2138 | |
| 2139 | |
| 2140 | void Assembler::ceil_w_s(FPURegister fd, FPURegister fs) { |
| 2141 | GenInstrRegister(COP1, S, f0, fs, fd, CEIL_W_S); |
| 2142 | } |
| 2143 | |
| 2144 | |
| 2145 | void Assembler::ceil_w_d(FPURegister fd, FPURegister fs) { |
| 2146 | GenInstrRegister(COP1, D, f0, fs, fd, CEIL_W_D); |
| 2147 | } |
| 2148 | |
| 2149 | |
Andrei Popescu | 3100271 | 2010-02-23 13:46:05 +0000 | [diff] [blame] | 2150 | void Assembler::cvt_l_s(FPURegister fd, FPURegister fs) { |
Ben Murdoch | b8a8cc1 | 2014-11-26 15:28:44 +0000 | [diff] [blame] | 2151 | DCHECK(IsMipsArchVariant(kMips32r2)); |
Andrei Popescu | 3100271 | 2010-02-23 13:46:05 +0000 | [diff] [blame] | 2152 | GenInstrRegister(COP1, S, f0, fs, fd, CVT_L_S); |
| 2153 | } |
| 2154 | |
| 2155 | |
| 2156 | void Assembler::cvt_l_d(FPURegister fd, FPURegister fs) { |
Ben Murdoch | b8a8cc1 | 2014-11-26 15:28:44 +0000 | [diff] [blame] | 2157 | DCHECK(IsMipsArchVariant(kMips32r2)); |
Andrei Popescu | 3100271 | 2010-02-23 13:46:05 +0000 | [diff] [blame] | 2158 | GenInstrRegister(COP1, D, f0, fs, fd, CVT_L_D); |
| 2159 | } |
| 2160 | |
| 2161 | |
Steve Block | 44f0eee | 2011-05-26 01:26:41 +0100 | [diff] [blame] | 2162 | void Assembler::trunc_l_s(FPURegister fd, FPURegister fs) { |
Ben Murdoch | b8a8cc1 | 2014-11-26 15:28:44 +0000 | [diff] [blame] | 2163 | DCHECK(IsMipsArchVariant(kMips32r2)); |
Steve Block | 44f0eee | 2011-05-26 01:26:41 +0100 | [diff] [blame] | 2164 | GenInstrRegister(COP1, S, f0, fs, fd, TRUNC_L_S); |
| 2165 | } |
| 2166 | |
| 2167 | |
| 2168 | void Assembler::trunc_l_d(FPURegister fd, FPURegister fs) { |
Ben Murdoch | b8a8cc1 | 2014-11-26 15:28:44 +0000 | [diff] [blame] | 2169 | DCHECK(IsMipsArchVariant(kMips32r2)); |
Steve Block | 44f0eee | 2011-05-26 01:26:41 +0100 | [diff] [blame] | 2170 | GenInstrRegister(COP1, D, f0, fs, fd, TRUNC_L_D); |
| 2171 | } |
| 2172 | |
| 2173 | |
| 2174 | void Assembler::round_l_s(FPURegister fd, FPURegister fs) { |
| 2175 | GenInstrRegister(COP1, S, f0, fs, fd, ROUND_L_S); |
| 2176 | } |
| 2177 | |
| 2178 | |
| 2179 | void Assembler::round_l_d(FPURegister fd, FPURegister fs) { |
| 2180 | GenInstrRegister(COP1, D, f0, fs, fd, ROUND_L_D); |
| 2181 | } |
| 2182 | |
| 2183 | |
| 2184 | void Assembler::floor_l_s(FPURegister fd, FPURegister fs) { |
| 2185 | GenInstrRegister(COP1, S, f0, fs, fd, FLOOR_L_S); |
| 2186 | } |
| 2187 | |
| 2188 | |
| 2189 | void Assembler::floor_l_d(FPURegister fd, FPURegister fs) { |
| 2190 | GenInstrRegister(COP1, D, f0, fs, fd, FLOOR_L_D); |
| 2191 | } |
| 2192 | |
| 2193 | |
| 2194 | void Assembler::ceil_l_s(FPURegister fd, FPURegister fs) { |
| 2195 | GenInstrRegister(COP1, S, f0, fs, fd, CEIL_L_S); |
| 2196 | } |
| 2197 | |
| 2198 | |
| 2199 | void Assembler::ceil_l_d(FPURegister fd, FPURegister fs) { |
| 2200 | GenInstrRegister(COP1, D, f0, fs, fd, CEIL_L_D); |
| 2201 | } |
| 2202 | |
| 2203 | |
Ben Murdoch | b8a8cc1 | 2014-11-26 15:28:44 +0000 | [diff] [blame] | 2204 | void Assembler::min(SecondaryField fmt, FPURegister fd, FPURegister ft, |
| 2205 | FPURegister fs) { |
| 2206 | DCHECK(IsMipsArchVariant(kMips32r6)); |
| 2207 | DCHECK((fmt == D) || (fmt == S)); |
| 2208 | GenInstrRegister(COP1, fmt, ft, fs, fd, MIN); |
| 2209 | } |
| 2210 | |
| 2211 | |
| 2212 | void Assembler::mina(SecondaryField fmt, FPURegister fd, FPURegister ft, |
| 2213 | FPURegister fs) { |
| 2214 | DCHECK(IsMipsArchVariant(kMips32r6)); |
| 2215 | DCHECK((fmt == D) || (fmt == S)); |
| 2216 | GenInstrRegister(COP1, fmt, ft, fs, fd, MINA); |
| 2217 | } |
| 2218 | |
| 2219 | |
| 2220 | void Assembler::max(SecondaryField fmt, FPURegister fd, FPURegister ft, |
| 2221 | FPURegister fs) { |
| 2222 | DCHECK(IsMipsArchVariant(kMips32r6)); |
| 2223 | DCHECK((fmt == D) || (fmt == S)); |
| 2224 | GenInstrRegister(COP1, fmt, ft, fs, fd, MAX); |
| 2225 | } |
| 2226 | |
| 2227 | |
| 2228 | void Assembler::maxa(SecondaryField fmt, FPURegister fd, FPURegister ft, |
| 2229 | FPURegister fs) { |
| 2230 | DCHECK(IsMipsArchVariant(kMips32r6)); |
| 2231 | DCHECK((fmt == D) || (fmt == S)); |
| 2232 | GenInstrRegister(COP1, fmt, ft, fs, fd, MAXA); |
| 2233 | } |
| 2234 | |
| 2235 | |
Andrei Popescu | 3100271 | 2010-02-23 13:46:05 +0000 | [diff] [blame] | 2236 | void Assembler::cvt_s_w(FPURegister fd, FPURegister fs) { |
| 2237 | GenInstrRegister(COP1, W, f0, fs, fd, CVT_S_W); |
| 2238 | } |
| 2239 | |
| 2240 | |
| 2241 | void Assembler::cvt_s_l(FPURegister fd, FPURegister fs) { |
Ben Murdoch | b8a8cc1 | 2014-11-26 15:28:44 +0000 | [diff] [blame] | 2242 | DCHECK(IsMipsArchVariant(kMips32r2)); |
Andrei Popescu | 3100271 | 2010-02-23 13:46:05 +0000 | [diff] [blame] | 2243 | GenInstrRegister(COP1, L, f0, fs, fd, CVT_S_L); |
| 2244 | } |
| 2245 | |
| 2246 | |
| 2247 | void Assembler::cvt_s_d(FPURegister fd, FPURegister fs) { |
| 2248 | GenInstrRegister(COP1, D, f0, fs, fd, CVT_S_D); |
| 2249 | } |
| 2250 | |
| 2251 | |
| 2252 | void Assembler::cvt_d_w(FPURegister fd, FPURegister fs) { |
| 2253 | GenInstrRegister(COP1, W, f0, fs, fd, CVT_D_W); |
| 2254 | } |
| 2255 | |
| 2256 | |
| 2257 | void Assembler::cvt_d_l(FPURegister fd, FPURegister fs) { |
Ben Murdoch | b8a8cc1 | 2014-11-26 15:28:44 +0000 | [diff] [blame] | 2258 | DCHECK(IsMipsArchVariant(kMips32r2)); |
Andrei Popescu | 3100271 | 2010-02-23 13:46:05 +0000 | [diff] [blame] | 2259 | GenInstrRegister(COP1, L, f0, fs, fd, CVT_D_L); |
| 2260 | } |
| 2261 | |
| 2262 | |
| 2263 | void Assembler::cvt_d_s(FPURegister fd, FPURegister fs) { |
| 2264 | GenInstrRegister(COP1, S, f0, fs, fd, CVT_D_S); |
| 2265 | } |
| 2266 | |
| 2267 | |
Ben Murdoch | b8a8cc1 | 2014-11-26 15:28:44 +0000 | [diff] [blame] | 2268 | // Conditions for >= MIPSr6. |
| 2269 | void Assembler::cmp(FPUCondition cond, SecondaryField fmt, |
| 2270 | FPURegister fd, FPURegister fs, FPURegister ft) { |
| 2271 | DCHECK(IsMipsArchVariant(kMips32r6)); |
| 2272 | DCHECK((fmt & ~(31 << kRsShift)) == 0); |
| 2273 | Instr instr = COP1 | fmt | ft.code() << kFtShift | |
| 2274 | fs.code() << kFsShift | fd.code() << kFdShift | (0 << 5) | cond; |
| 2275 | emit(instr); |
| 2276 | } |
| 2277 | |
| 2278 | |
| 2279 | void Assembler::bc1eqz(int16_t offset, FPURegister ft) { |
| 2280 | DCHECK(IsMipsArchVariant(kMips32r6)); |
| 2281 | Instr instr = COP1 | BC1EQZ | ft.code() << kFtShift | (offset & kImm16Mask); |
| 2282 | emit(instr); |
| 2283 | } |
| 2284 | |
| 2285 | |
| 2286 | void Assembler::bc1nez(int16_t offset, FPURegister ft) { |
| 2287 | DCHECK(IsMipsArchVariant(kMips32r6)); |
| 2288 | Instr instr = COP1 | BC1NEZ | ft.code() << kFtShift | (offset & kImm16Mask); |
| 2289 | emit(instr); |
| 2290 | } |
| 2291 | |
| 2292 | |
| 2293 | // Conditions for < MIPSr6. |
Andrei Popescu | 3100271 | 2010-02-23 13:46:05 +0000 | [diff] [blame] | 2294 | void Assembler::c(FPUCondition cond, SecondaryField fmt, |
Steve Block | 44f0eee | 2011-05-26 01:26:41 +0100 | [diff] [blame] | 2295 | FPURegister fs, FPURegister ft, uint16_t cc) { |
Ben Murdoch | b8a8cc1 | 2014-11-26 15:28:44 +0000 | [diff] [blame] | 2296 | DCHECK(is_uint3(cc)); |
| 2297 | DCHECK((fmt & ~(31 << kRsShift)) == 0); |
Andrei Popescu | 3100271 | 2010-02-23 13:46:05 +0000 | [diff] [blame] | 2298 | Instr instr = COP1 | fmt | ft.code() << 16 | fs.code() << kFsShift |
| 2299 | | cc << 8 | 3 << 4 | cond; |
| 2300 | emit(instr); |
| 2301 | } |
| 2302 | |
| 2303 | |
Steve Block | 44f0eee | 2011-05-26 01:26:41 +0100 | [diff] [blame] | 2304 | void Assembler::fcmp(FPURegister src1, const double src2, |
| 2305 | FPUCondition cond) { |
Ben Murdoch | b8a8cc1 | 2014-11-26 15:28:44 +0000 | [diff] [blame] | 2306 | DCHECK(src2 == 0.0); |
Steve Block | 44f0eee | 2011-05-26 01:26:41 +0100 | [diff] [blame] | 2307 | mtc1(zero_reg, f14); |
| 2308 | cvt_d_w(f14, f14); |
| 2309 | c(cond, D, src1, f14, 0); |
| 2310 | } |
| 2311 | |
| 2312 | |
Andrei Popescu | 3100271 | 2010-02-23 13:46:05 +0000 | [diff] [blame] | 2313 | void Assembler::bc1f(int16_t offset, uint16_t cc) { |
Ben Murdoch | b8a8cc1 | 2014-11-26 15:28:44 +0000 | [diff] [blame] | 2314 | DCHECK(is_uint3(cc)); |
Andrei Popescu | 3100271 | 2010-02-23 13:46:05 +0000 | [diff] [blame] | 2315 | Instr instr = COP1 | BC1 | cc << 18 | 0 << 16 | (offset & kImm16Mask); |
| 2316 | emit(instr); |
| 2317 | } |
| 2318 | |
| 2319 | |
| 2320 | void Assembler::bc1t(int16_t offset, uint16_t cc) { |
Ben Murdoch | b8a8cc1 | 2014-11-26 15:28:44 +0000 | [diff] [blame] | 2321 | DCHECK(is_uint3(cc)); |
Andrei Popescu | 3100271 | 2010-02-23 13:46:05 +0000 | [diff] [blame] | 2322 | Instr instr = COP1 | BC1 | cc << 18 | 1 << 16 | (offset & kImm16Mask); |
| 2323 | emit(instr); |
| 2324 | } |
| 2325 | |
| 2326 | |
| 2327 | // Debugging. |
| 2328 | void Assembler::RecordJSReturn() { |
Steve Block | 44f0eee | 2011-05-26 01:26:41 +0100 | [diff] [blame] | 2329 | positions_recorder()->WriteRecordedPositions(); |
Andrei Popescu | 3100271 | 2010-02-23 13:46:05 +0000 | [diff] [blame] | 2330 | CheckBuffer(); |
| 2331 | RecordRelocInfo(RelocInfo::JS_RETURN); |
| 2332 | } |
| 2333 | |
| 2334 | |
Steve Block | 44f0eee | 2011-05-26 01:26:41 +0100 | [diff] [blame] | 2335 | void Assembler::RecordDebugBreakSlot() { |
| 2336 | positions_recorder()->WriteRecordedPositions(); |
| 2337 | CheckBuffer(); |
| 2338 | RecordRelocInfo(RelocInfo::DEBUG_BREAK_SLOT); |
| 2339 | } |
| 2340 | |
| 2341 | |
Andrei Popescu | 3100271 | 2010-02-23 13:46:05 +0000 | [diff] [blame] | 2342 | void Assembler::RecordComment(const char* msg) { |
Steve Block | 44f0eee | 2011-05-26 01:26:41 +0100 | [diff] [blame] | 2343 | if (FLAG_code_comments) { |
Andrei Popescu | 3100271 | 2010-02-23 13:46:05 +0000 | [diff] [blame] | 2344 | CheckBuffer(); |
| 2345 | RecordRelocInfo(RelocInfo::COMMENT, reinterpret_cast<intptr_t>(msg)); |
| 2346 | } |
| 2347 | } |
| 2348 | |
| 2349 | |
Ben Murdoch | 3fb3ca8 | 2011-12-02 17:19:32 +0000 | [diff] [blame] | 2350 | int Assembler::RelocateInternalReference(byte* pc, intptr_t pc_delta) { |
| 2351 | Instr instr = instr_at(pc); |
Ben Murdoch | b8a8cc1 | 2014-11-26 15:28:44 +0000 | [diff] [blame] | 2352 | DCHECK(IsJ(instr) || IsLui(instr)); |
Ben Murdoch | 3fb3ca8 | 2011-12-02 17:19:32 +0000 | [diff] [blame] | 2353 | if (IsLui(instr)) { |
| 2354 | Instr instr_lui = instr_at(pc + 0 * Assembler::kInstrSize); |
| 2355 | Instr instr_ori = instr_at(pc + 1 * Assembler::kInstrSize); |
Ben Murdoch | b8a8cc1 | 2014-11-26 15:28:44 +0000 | [diff] [blame] | 2356 | DCHECK(IsOri(instr_ori)); |
Ben Murdoch | 3fb3ca8 | 2011-12-02 17:19:32 +0000 | [diff] [blame] | 2357 | int32_t imm = (instr_lui & static_cast<int32_t>(kImm16Mask)) << kLuiShift; |
| 2358 | imm |= (instr_ori & static_cast<int32_t>(kImm16Mask)); |
| 2359 | if (imm == kEndOfJumpChain) { |
| 2360 | return 0; // Number of instructions patched. |
| 2361 | } |
| 2362 | imm += pc_delta; |
Ben Murdoch | b8a8cc1 | 2014-11-26 15:28:44 +0000 | [diff] [blame] | 2363 | DCHECK((imm & 3) == 0); |
Ben Murdoch | 3fb3ca8 | 2011-12-02 17:19:32 +0000 | [diff] [blame] | 2364 | |
| 2365 | instr_lui &= ~kImm16Mask; |
| 2366 | instr_ori &= ~kImm16Mask; |
| 2367 | |
| 2368 | instr_at_put(pc + 0 * Assembler::kInstrSize, |
| 2369 | instr_lui | ((imm >> kLuiShift) & kImm16Mask)); |
| 2370 | instr_at_put(pc + 1 * Assembler::kInstrSize, |
| 2371 | instr_ori | (imm & kImm16Mask)); |
| 2372 | return 2; // Number of instructions patched. |
| 2373 | } else { |
| 2374 | uint32_t imm28 = (instr & static_cast<int32_t>(kImm26Mask)) << 2; |
Ben Murdoch | b8a8cc1 | 2014-11-26 15:28:44 +0000 | [diff] [blame] | 2375 | if (static_cast<int32_t>(imm28) == kEndOfJumpChain) { |
Ben Murdoch | 3fb3ca8 | 2011-12-02 17:19:32 +0000 | [diff] [blame] | 2376 | return 0; // Number of instructions patched. |
| 2377 | } |
| 2378 | imm28 += pc_delta; |
| 2379 | imm28 &= kImm28Mask; |
Ben Murdoch | b8a8cc1 | 2014-11-26 15:28:44 +0000 | [diff] [blame] | 2380 | DCHECK((imm28 & 3) == 0); |
Ben Murdoch | 3fb3ca8 | 2011-12-02 17:19:32 +0000 | [diff] [blame] | 2381 | |
| 2382 | instr &= ~kImm26Mask; |
| 2383 | uint32_t imm26 = imm28 >> 2; |
Ben Murdoch | b8a8cc1 | 2014-11-26 15:28:44 +0000 | [diff] [blame] | 2384 | DCHECK(is_uint26(imm26)); |
Ben Murdoch | 3fb3ca8 | 2011-12-02 17:19:32 +0000 | [diff] [blame] | 2385 | |
| 2386 | instr_at_put(pc, instr | (imm26 & kImm26Mask)); |
| 2387 | return 1; // Number of instructions patched. |
| 2388 | } |
| 2389 | } |
| 2390 | |
| 2391 | |
Andrei Popescu | 3100271 | 2010-02-23 13:46:05 +0000 | [diff] [blame] | 2392 | void Assembler::GrowBuffer() { |
| 2393 | if (!own_buffer_) FATAL("external code buffer is too small"); |
| 2394 | |
| 2395 | // Compute new buffer size. |
Steve Block | 44f0eee | 2011-05-26 01:26:41 +0100 | [diff] [blame] | 2396 | CodeDesc desc; // The new buffer. |
Ben Murdoch | b8a8cc1 | 2014-11-26 15:28:44 +0000 | [diff] [blame] | 2397 | if (buffer_size_ < 1 * MB) { |
Andrei Popescu | 3100271 | 2010-02-23 13:46:05 +0000 | [diff] [blame] | 2398 | desc.buffer_size = 2*buffer_size_; |
| 2399 | } else { |
| 2400 | desc.buffer_size = buffer_size_ + 1*MB; |
| 2401 | } |
Steve Block | 44f0eee | 2011-05-26 01:26:41 +0100 | [diff] [blame] | 2402 | CHECK_GT(desc.buffer_size, 0); // No overflow. |
Andrei Popescu | 3100271 | 2010-02-23 13:46:05 +0000 | [diff] [blame] | 2403 | |
Ben Murdoch | 3ef787d | 2012-04-12 10:51:47 +0100 | [diff] [blame] | 2404 | // Set up new buffer. |
Andrei Popescu | 3100271 | 2010-02-23 13:46:05 +0000 | [diff] [blame] | 2405 | desc.buffer = NewArray<byte>(desc.buffer_size); |
| 2406 | |
| 2407 | desc.instr_size = pc_offset(); |
| 2408 | desc.reloc_size = (buffer_ + buffer_size_) - reloc_info_writer.pos(); |
| 2409 | |
| 2410 | // Copy the data. |
| 2411 | int pc_delta = desc.buffer - buffer_; |
| 2412 | int rc_delta = (desc.buffer + desc.buffer_size) - (buffer_ + buffer_size_); |
Ben Murdoch | b8a8cc1 | 2014-11-26 15:28:44 +0000 | [diff] [blame] | 2413 | MemMove(desc.buffer, buffer_, desc.instr_size); |
| 2414 | MemMove(reloc_info_writer.pos() + rc_delta, reloc_info_writer.pos(), |
| 2415 | desc.reloc_size); |
Andrei Popescu | 3100271 | 2010-02-23 13:46:05 +0000 | [diff] [blame] | 2416 | |
| 2417 | // Switch buffers. |
| 2418 | DeleteArray(buffer_); |
| 2419 | buffer_ = desc.buffer; |
| 2420 | buffer_size_ = desc.buffer_size; |
| 2421 | pc_ += pc_delta; |
| 2422 | reloc_info_writer.Reposition(reloc_info_writer.pos() + rc_delta, |
| 2423 | reloc_info_writer.last_pc() + pc_delta); |
| 2424 | |
Ben Murdoch | 3fb3ca8 | 2011-12-02 17:19:32 +0000 | [diff] [blame] | 2425 | // Relocate runtime entries. |
| 2426 | for (RelocIterator it(desc); !it.done(); it.next()) { |
| 2427 | RelocInfo::Mode rmode = it.rinfo()->rmode(); |
| 2428 | if (rmode == RelocInfo::INTERNAL_REFERENCE) { |
| 2429 | byte* p = reinterpret_cast<byte*>(it.rinfo()->pc()); |
| 2430 | RelocateInternalReference(p, pc_delta); |
| 2431 | } |
| 2432 | } |
Andrei Popescu | 3100271 | 2010-02-23 13:46:05 +0000 | [diff] [blame] | 2433 | |
Ben Murdoch | b8a8cc1 | 2014-11-26 15:28:44 +0000 | [diff] [blame] | 2434 | DCHECK(!overflow()); |
Andrei Popescu | 3100271 | 2010-02-23 13:46:05 +0000 | [diff] [blame] | 2435 | } |
| 2436 | |
| 2437 | |
Steve Block | 44f0eee | 2011-05-26 01:26:41 +0100 | [diff] [blame] | 2438 | void Assembler::db(uint8_t data) { |
| 2439 | CheckBuffer(); |
| 2440 | *reinterpret_cast<uint8_t*>(pc_) = data; |
| 2441 | pc_ += sizeof(uint8_t); |
| 2442 | } |
| 2443 | |
| 2444 | |
| 2445 | void Assembler::dd(uint32_t data) { |
| 2446 | CheckBuffer(); |
| 2447 | *reinterpret_cast<uint32_t*>(pc_) = data; |
| 2448 | pc_ += sizeof(uint32_t); |
| 2449 | } |
| 2450 | |
| 2451 | |
Ben Murdoch | b8a8cc1 | 2014-11-26 15:28:44 +0000 | [diff] [blame] | 2452 | void Assembler::emit_code_stub_address(Code* stub) { |
| 2453 | CheckBuffer(); |
| 2454 | *reinterpret_cast<uint32_t*>(pc_) = |
| 2455 | reinterpret_cast<uint32_t>(stub->instruction_start()); |
| 2456 | pc_ += sizeof(uint32_t); |
| 2457 | } |
| 2458 | |
| 2459 | |
Andrei Popescu | 3100271 | 2010-02-23 13:46:05 +0000 | [diff] [blame] | 2460 | void Assembler::RecordRelocInfo(RelocInfo::Mode rmode, intptr_t data) { |
Ben Murdoch | 3ef787d | 2012-04-12 10:51:47 +0100 | [diff] [blame] | 2461 | // We do not try to reuse pool constants. |
| 2462 | RelocInfo rinfo(pc_, rmode, data, NULL); |
Steve Block | 44f0eee | 2011-05-26 01:26:41 +0100 | [diff] [blame] | 2463 | if (rmode >= RelocInfo::JS_RETURN && rmode <= RelocInfo::DEBUG_BREAK_SLOT) { |
Andrei Popescu | 3100271 | 2010-02-23 13:46:05 +0000 | [diff] [blame] | 2464 | // Adjust code for new modes. |
Ben Murdoch | b8a8cc1 | 2014-11-26 15:28:44 +0000 | [diff] [blame] | 2465 | DCHECK(RelocInfo::IsDebugBreakSlot(rmode) |
Steve Block | 44f0eee | 2011-05-26 01:26:41 +0100 | [diff] [blame] | 2466 | || RelocInfo::IsJSReturn(rmode) |
Andrei Popescu | 3100271 | 2010-02-23 13:46:05 +0000 | [diff] [blame] | 2467 | || RelocInfo::IsComment(rmode) |
| 2468 | || RelocInfo::IsPosition(rmode)); |
| 2469 | // These modes do not need an entry in the constant pool. |
| 2470 | } |
Ben Murdoch | b8a8cc1 | 2014-11-26 15:28:44 +0000 | [diff] [blame] | 2471 | if (!RelocInfo::IsNone(rinfo.rmode())) { |
Andrei Popescu | 3100271 | 2010-02-23 13:46:05 +0000 | [diff] [blame] | 2472 | // Don't record external references unless the heap will be serialized. |
Ben Murdoch | b8a8cc1 | 2014-11-26 15:28:44 +0000 | [diff] [blame] | 2473 | if (rmode == RelocInfo::EXTERNAL_REFERENCE && |
| 2474 | !serializer_enabled() && !emit_debug_code()) { |
| 2475 | return; |
Andrei Popescu | 3100271 | 2010-02-23 13:46:05 +0000 | [diff] [blame] | 2476 | } |
Ben Murdoch | b8a8cc1 | 2014-11-26 15:28:44 +0000 | [diff] [blame] | 2477 | DCHECK(buffer_space() >= kMaxRelocSize); // Too late to grow buffer here. |
Ben Murdoch | 257744e | 2011-11-30 15:57:28 +0000 | [diff] [blame] | 2478 | if (rmode == RelocInfo::CODE_TARGET_WITH_ID) { |
Ben Murdoch | b8a8cc1 | 2014-11-26 15:28:44 +0000 | [diff] [blame] | 2479 | RelocInfo reloc_info_with_ast_id(pc_, |
| 2480 | rmode, |
| 2481 | RecordedAstId().ToInt(), |
| 2482 | NULL); |
Ben Murdoch | 3fb3ca8 | 2011-12-02 17:19:32 +0000 | [diff] [blame] | 2483 | ClearRecordedAstId(); |
Ben Murdoch | 257744e | 2011-11-30 15:57:28 +0000 | [diff] [blame] | 2484 | reloc_info_writer.Write(&reloc_info_with_ast_id); |
| 2485 | } else { |
| 2486 | reloc_info_writer.Write(&rinfo); |
| 2487 | } |
Andrei Popescu | 3100271 | 2010-02-23 13:46:05 +0000 | [diff] [blame] | 2488 | } |
| 2489 | } |
| 2490 | |
| 2491 | |
Steve Block | 44f0eee | 2011-05-26 01:26:41 +0100 | [diff] [blame] | 2492 | void Assembler::BlockTrampolinePoolFor(int instructions) { |
| 2493 | BlockTrampolinePoolBefore(pc_offset() + instructions * kInstrSize); |
| 2494 | } |
| 2495 | |
| 2496 | |
Ben Murdoch | 3fb3ca8 | 2011-12-02 17:19:32 +0000 | [diff] [blame] | 2497 | void Assembler::CheckTrampolinePool() { |
Steve Block | 44f0eee | 2011-05-26 01:26:41 +0100 | [diff] [blame] | 2498 | // Some small sequences of instructions must not be broken up by the |
| 2499 | // insertion of a trampoline pool; such sequences are protected by setting |
| 2500 | // either trampoline_pool_blocked_nesting_ or no_trampoline_pool_before_, |
| 2501 | // which are both checked here. Also, recursive calls to CheckTrampolinePool |
| 2502 | // are blocked by trampoline_pool_blocked_nesting_. |
| 2503 | if ((trampoline_pool_blocked_nesting_ > 0) || |
| 2504 | (pc_offset() < no_trampoline_pool_before_)) { |
| 2505 | // Emission is currently blocked; make sure we try again as soon as |
| 2506 | // possible. |
| 2507 | if (trampoline_pool_blocked_nesting_ > 0) { |
| 2508 | next_buffer_check_ = pc_offset() + kInstrSize; |
| 2509 | } else { |
| 2510 | next_buffer_check_ = no_trampoline_pool_before_; |
| 2511 | } |
| 2512 | return; |
| 2513 | } |
| 2514 | |
Ben Murdoch | b8a8cc1 | 2014-11-26 15:28:44 +0000 | [diff] [blame] | 2515 | DCHECK(!trampoline_emitted_); |
| 2516 | DCHECK(unbound_labels_count_ >= 0); |
Ben Murdoch | 3fb3ca8 | 2011-12-02 17:19:32 +0000 | [diff] [blame] | 2517 | if (unbound_labels_count_ > 0) { |
| 2518 | // First we emit jump (2 instructions), then we emit trampoline pool. |
| 2519 | { BlockTrampolinePoolScope block_trampoline_pool(this); |
| 2520 | Label after_pool; |
Steve Block | 44f0eee | 2011-05-26 01:26:41 +0100 | [diff] [blame] | 2521 | b(&after_pool); |
| 2522 | nop(); |
Steve Block | 44f0eee | 2011-05-26 01:26:41 +0100 | [diff] [blame] | 2523 | |
Ben Murdoch | 3fb3ca8 | 2011-12-02 17:19:32 +0000 | [diff] [blame] | 2524 | int pool_start = pc_offset(); |
| 2525 | for (int i = 0; i < unbound_labels_count_; i++) { |
| 2526 | uint32_t imm32; |
| 2527 | imm32 = jump_address(&after_pool); |
| 2528 | { BlockGrowBufferScope block_buf_growth(this); |
| 2529 | // Buffer growth (and relocation) must be blocked for internal |
| 2530 | // references until associated instructions are emitted and available |
| 2531 | // to be patched. |
| 2532 | RecordRelocInfo(RelocInfo::INTERNAL_REFERENCE); |
| 2533 | lui(at, (imm32 & kHiMask) >> kLuiShift); |
| 2534 | ori(at, at, (imm32 & kImm16Mask)); |
| 2535 | } |
| 2536 | jr(at); |
| 2537 | nop(); |
| 2538 | } |
| 2539 | bind(&after_pool); |
| 2540 | trampoline_ = Trampoline(pool_start, unbound_labels_count_); |
| 2541 | |
| 2542 | trampoline_emitted_ = true; |
| 2543 | // As we are only going to emit trampoline once, we need to prevent any |
| 2544 | // further emission. |
| 2545 | next_buffer_check_ = kMaxInt; |
| 2546 | } |
| 2547 | } else { |
| 2548 | // Number of branches to unbound label at this point is zero, so we can |
| 2549 | // move next buffer check to maximum. |
| 2550 | next_buffer_check_ = pc_offset() + |
| 2551 | kMaxBranchOffset - kTrampolineSlotsSize * 16; |
Steve Block | 44f0eee | 2011-05-26 01:26:41 +0100 | [diff] [blame] | 2552 | } |
| 2553 | return; |
| 2554 | } |
| 2555 | |
| 2556 | |
Andrei Popescu | 3100271 | 2010-02-23 13:46:05 +0000 | [diff] [blame] | 2557 | Address Assembler::target_address_at(Address pc) { |
| 2558 | Instr instr1 = instr_at(pc); |
| 2559 | Instr instr2 = instr_at(pc + kInstrSize); |
Ben Murdoch | 257744e | 2011-11-30 15:57:28 +0000 | [diff] [blame] | 2560 | // Interpret 2 instructions generated by li: lui/ori |
| 2561 | if ((GetOpcodeField(instr1) == LUI) && (GetOpcodeField(instr2) == ORI)) { |
| 2562 | // Assemble the 32 bit value. |
Andrei Popescu | 3100271 | 2010-02-23 13:46:05 +0000 | [diff] [blame] | 2563 | return reinterpret_cast<Address>( |
Ben Murdoch | 257744e | 2011-11-30 15:57:28 +0000 | [diff] [blame] | 2564 | (GetImmediate16(instr1) << 16) | GetImmediate16(instr2)); |
Andrei Popescu | 3100271 | 2010-02-23 13:46:05 +0000 | [diff] [blame] | 2565 | } |
| 2566 | |
Ben Murdoch | 257744e | 2011-11-30 15:57:28 +0000 | [diff] [blame] | 2567 | // We should never get here, force a bad address if we do. |
Andrei Popescu | 3100271 | 2010-02-23 13:46:05 +0000 | [diff] [blame] | 2568 | UNREACHABLE(); |
| 2569 | return (Address)0x0; |
| 2570 | } |
| 2571 | |
| 2572 | |
Ben Murdoch | db1b438 | 2012-04-26 19:03:50 +0100 | [diff] [blame] | 2573 | // MIPS and ia32 use opposite encoding for qNaN and sNaN, such that ia32 |
| 2574 | // qNaN is a MIPS sNaN, and ia32 sNaN is MIPS qNaN. If running from a heap |
| 2575 | // snapshot generated on ia32, the resulting MIPS sNaN must be quieted. |
| 2576 | // OS::nan_value() returns a qNaN. |
| 2577 | void Assembler::QuietNaN(HeapObject* object) { |
Ben Murdoch | b8a8cc1 | 2014-11-26 15:28:44 +0000 | [diff] [blame] | 2578 | HeapNumber::cast(object)->set_value(base::OS::nan_value()); |
Ben Murdoch | db1b438 | 2012-04-26 19:03:50 +0100 | [diff] [blame] | 2579 | } |
| 2580 | |
| 2581 | |
Ben Murdoch | 589d697 | 2011-11-30 16:04:58 +0000 | [diff] [blame] | 2582 | // On Mips, a target address is stored in a lui/ori instruction pair, each |
| 2583 | // of which load 16 bits of the 32-bit address to a register. |
| 2584 | // Patching the address must replace both instr, and flush the i-cache. |
| 2585 | // |
| 2586 | // There is an optimization below, which emits a nop when the address |
| 2587 | // fits in just 16 bits. This is unlikely to help, and should be benchmarked, |
| 2588 | // and possibly removed. |
Ben Murdoch | b8a8cc1 | 2014-11-26 15:28:44 +0000 | [diff] [blame] | 2589 | void Assembler::set_target_address_at(Address pc, |
| 2590 | Address target, |
| 2591 | ICacheFlushMode icache_flush_mode) { |
Andrei Popescu | 3100271 | 2010-02-23 13:46:05 +0000 | [diff] [blame] | 2592 | Instr instr2 = instr_at(pc + kInstrSize); |
Ben Murdoch | 257744e | 2011-11-30 15:57:28 +0000 | [diff] [blame] | 2593 | uint32_t rt_code = GetRtField(instr2); |
Andrei Popescu | 3100271 | 2010-02-23 13:46:05 +0000 | [diff] [blame] | 2594 | uint32_t* p = reinterpret_cast<uint32_t*>(pc); |
| 2595 | uint32_t itarget = reinterpret_cast<uint32_t>(target); |
| 2596 | |
Ben Murdoch | 589d697 | 2011-11-30 16:04:58 +0000 | [diff] [blame] | 2597 | #ifdef DEBUG |
| 2598 | // Check we have the result from a li macro-instruction, using instr pair. |
| 2599 | Instr instr1 = instr_at(pc); |
| 2600 | CHECK((GetOpcodeField(instr1) == LUI && GetOpcodeField(instr2) == ORI)); |
| 2601 | #endif |
| 2602 | |
| 2603 | // Must use 2 instructions to insure patchable code => just use lui and ori. |
| 2604 | // lui rt, upper-16. |
| 2605 | // ori rt rt, lower-16. |
Ben Murdoch | 257744e | 2011-11-30 15:57:28 +0000 | [diff] [blame] | 2606 | *p = LUI | rt_code | ((itarget & kHiMask) >> kLuiShift); |
Ben Murdoch | b8a8cc1 | 2014-11-26 15:28:44 +0000 | [diff] [blame] | 2607 | *(p + 1) = ORI | rt_code | (rt_code << 5) | (itarget & kImm16Mask); |
Andrei Popescu | 3100271 | 2010-02-23 13:46:05 +0000 | [diff] [blame] | 2608 | |
Ben Murdoch | 589d697 | 2011-11-30 16:04:58 +0000 | [diff] [blame] | 2609 | // The following code is an optimization for the common case of Call() |
| 2610 | // or Jump() which is load to register, and jump through register: |
| 2611 | // li(t9, address); jalr(t9) (or jr(t9)). |
| 2612 | // If the destination address is in the same 256 MB page as the call, it |
| 2613 | // is faster to do a direct jal, or j, rather than jump thru register, since |
| 2614 | // that lets the cpu pipeline prefetch the target address. However each |
| 2615 | // time the address above is patched, we have to patch the direct jal/j |
| 2616 | // instruction, as well as possibly revert to jalr/jr if we now cross a |
| 2617 | // 256 MB page. Note that with the jal/j instructions, we do not need to |
| 2618 | // load the register, but that code is left, since it makes it easy to |
| 2619 | // revert this process. A further optimization could try replacing the |
| 2620 | // li sequence with nops. |
| 2621 | // This optimization can only be applied if the rt-code from instr2 is the |
| 2622 | // register used for the jalr/jr. Finally, we have to skip 'jr ra', which is |
| 2623 | // mips return. Occasionally this lands after an li(). |
| 2624 | |
| 2625 | Instr instr3 = instr_at(pc + 2 * kInstrSize); |
| 2626 | uint32_t ipc = reinterpret_cast<uint32_t>(pc + 3 * kInstrSize); |
Ben Murdoch | b8a8cc1 | 2014-11-26 15:28:44 +0000 | [diff] [blame] | 2627 | bool in_range = ((ipc ^ itarget) >> (kImm26Bits + kImmFieldShift)) == 0; |
| 2628 | uint32_t target_field = |
| 2629 | static_cast<uint32_t>(itarget & kJumpAddrMask) >> kImmFieldShift; |
Ben Murdoch | 589d697 | 2011-11-30 16:04:58 +0000 | [diff] [blame] | 2630 | bool patched_jump = false; |
| 2631 | |
| 2632 | #ifndef ALLOW_JAL_IN_BOUNDARY_REGION |
| 2633 | // This is a workaround to the 24k core E156 bug (affect some 34k cores also). |
| 2634 | // Since the excluded space is only 64KB out of 256MB (0.02 %), we will just |
| 2635 | // apply this workaround for all cores so we don't have to identify the core. |
| 2636 | if (in_range) { |
| 2637 | // The 24k core E156 bug has some very specific requirements, we only check |
| 2638 | // the most simple one: if the address of the delay slot instruction is in |
| 2639 | // the first or last 32 KB of the 256 MB segment. |
| 2640 | uint32_t segment_mask = ((256 * MB) - 1) ^ ((32 * KB) - 1); |
| 2641 | uint32_t ipc_segment_addr = ipc & segment_mask; |
| 2642 | if (ipc_segment_addr == 0 || ipc_segment_addr == segment_mask) |
| 2643 | in_range = false; |
| 2644 | } |
| 2645 | #endif |
| 2646 | |
| 2647 | if (IsJalr(instr3)) { |
| 2648 | // Try to convert JALR to JAL. |
| 2649 | if (in_range && GetRt(instr2) == GetRs(instr3)) { |
Ben Murdoch | b8a8cc1 | 2014-11-26 15:28:44 +0000 | [diff] [blame] | 2650 | *(p + 2) = JAL | target_field; |
Ben Murdoch | 589d697 | 2011-11-30 16:04:58 +0000 | [diff] [blame] | 2651 | patched_jump = true; |
| 2652 | } |
| 2653 | } else if (IsJr(instr3)) { |
| 2654 | // Try to convert JR to J, skip returns (jr ra). |
| 2655 | bool is_ret = static_cast<int>(GetRs(instr3)) == ra.code(); |
| 2656 | if (in_range && !is_ret && GetRt(instr2) == GetRs(instr3)) { |
Ben Murdoch | b8a8cc1 | 2014-11-26 15:28:44 +0000 | [diff] [blame] | 2657 | *(p + 2) = J | target_field; |
Ben Murdoch | 589d697 | 2011-11-30 16:04:58 +0000 | [diff] [blame] | 2658 | patched_jump = true; |
| 2659 | } |
| 2660 | } else if (IsJal(instr3)) { |
| 2661 | if (in_range) { |
| 2662 | // We are patching an already converted JAL. |
Ben Murdoch | b8a8cc1 | 2014-11-26 15:28:44 +0000 | [diff] [blame] | 2663 | *(p + 2) = JAL | target_field; |
Ben Murdoch | 589d697 | 2011-11-30 16:04:58 +0000 | [diff] [blame] | 2664 | } else { |
| 2665 | // Patch JAL, but out of range, revert to JALR. |
| 2666 | // JALR rs reg is the rt reg specified in the ORI instruction. |
| 2667 | uint32_t rs_field = GetRt(instr2) << kRsShift; |
| 2668 | uint32_t rd_field = ra.code() << kRdShift; // Return-address (ra) reg. |
| 2669 | *(p+2) = SPECIAL | rs_field | rd_field | JALR; |
| 2670 | } |
| 2671 | patched_jump = true; |
| 2672 | } else if (IsJ(instr3)) { |
| 2673 | if (in_range) { |
| 2674 | // We are patching an already converted J (jump). |
Ben Murdoch | b8a8cc1 | 2014-11-26 15:28:44 +0000 | [diff] [blame] | 2675 | *(p + 2) = J | target_field; |
Ben Murdoch | 589d697 | 2011-11-30 16:04:58 +0000 | [diff] [blame] | 2676 | } else { |
| 2677 | // Trying patch J, but out of range, just go back to JR. |
| 2678 | // JR 'rs' reg is the 'rt' reg specified in the ORI instruction (instr2). |
| 2679 | uint32_t rs_field = GetRt(instr2) << kRsShift; |
Ben Murdoch | b8a8cc1 | 2014-11-26 15:28:44 +0000 | [diff] [blame] | 2680 | if (IsMipsArchVariant(kMips32r6)) { |
| 2681 | *(p + 2) = SPECIAL | rs_field | (zero_reg.code() << kRdShift) | JALR; |
| 2682 | } else { |
| 2683 | *(p + 2) = SPECIAL | rs_field | JR; |
| 2684 | } |
Ben Murdoch | 589d697 | 2011-11-30 16:04:58 +0000 | [diff] [blame] | 2685 | } |
| 2686 | patched_jump = true; |
| 2687 | } |
| 2688 | |
Ben Murdoch | b8a8cc1 | 2014-11-26 15:28:44 +0000 | [diff] [blame] | 2689 | if (icache_flush_mode != SKIP_ICACHE_FLUSH) { |
| 2690 | CpuFeatures::FlushICache(pc, (patched_jump ? 3 : 2) * sizeof(int32_t)); |
| 2691 | } |
Andrei Popescu | 3100271 | 2010-02-23 13:46:05 +0000 | [diff] [blame] | 2692 | } |
| 2693 | |
Ben Murdoch | b8a8cc1 | 2014-11-26 15:28:44 +0000 | [diff] [blame] | 2694 | |
Ben Murdoch | 589d697 | 2011-11-30 16:04:58 +0000 | [diff] [blame] | 2695 | void Assembler::JumpLabelToJumpRegister(Address pc) { |
| 2696 | // Address pc points to lui/ori instructions. |
| 2697 | // Jump to label may follow at pc + 2 * kInstrSize. |
| 2698 | uint32_t* p = reinterpret_cast<uint32_t*>(pc); |
| 2699 | #ifdef DEBUG |
| 2700 | Instr instr1 = instr_at(pc); |
| 2701 | #endif |
| 2702 | Instr instr2 = instr_at(pc + 1 * kInstrSize); |
| 2703 | Instr instr3 = instr_at(pc + 2 * kInstrSize); |
| 2704 | bool patched = false; |
| 2705 | |
| 2706 | if (IsJal(instr3)) { |
Ben Murdoch | b8a8cc1 | 2014-11-26 15:28:44 +0000 | [diff] [blame] | 2707 | DCHECK(GetOpcodeField(instr1) == LUI); |
| 2708 | DCHECK(GetOpcodeField(instr2) == ORI); |
Ben Murdoch | 589d697 | 2011-11-30 16:04:58 +0000 | [diff] [blame] | 2709 | |
| 2710 | uint32_t rs_field = GetRt(instr2) << kRsShift; |
| 2711 | uint32_t rd_field = ra.code() << kRdShift; // Return-address (ra) reg. |
Ben Murdoch | b8a8cc1 | 2014-11-26 15:28:44 +0000 | [diff] [blame] | 2712 | *(p + 2) = SPECIAL | rs_field | rd_field | JALR; |
Ben Murdoch | 589d697 | 2011-11-30 16:04:58 +0000 | [diff] [blame] | 2713 | patched = true; |
| 2714 | } else if (IsJ(instr3)) { |
Ben Murdoch | b8a8cc1 | 2014-11-26 15:28:44 +0000 | [diff] [blame] | 2715 | DCHECK(GetOpcodeField(instr1) == LUI); |
| 2716 | DCHECK(GetOpcodeField(instr2) == ORI); |
Ben Murdoch | 589d697 | 2011-11-30 16:04:58 +0000 | [diff] [blame] | 2717 | |
| 2718 | uint32_t rs_field = GetRt(instr2) << kRsShift; |
Ben Murdoch | b8a8cc1 | 2014-11-26 15:28:44 +0000 | [diff] [blame] | 2719 | if (IsMipsArchVariant(kMips32r6)) { |
| 2720 | *(p + 2) = SPECIAL | rs_field | (zero_reg.code() << kRdShift) | JALR; |
| 2721 | } else { |
| 2722 | *(p + 2) = SPECIAL | rs_field | JR; |
| 2723 | } |
Ben Murdoch | 589d697 | 2011-11-30 16:04:58 +0000 | [diff] [blame] | 2724 | patched = true; |
| 2725 | } |
| 2726 | |
| 2727 | if (patched) { |
Ben Murdoch | b8a8cc1 | 2014-11-26 15:28:44 +0000 | [diff] [blame] | 2728 | CpuFeatures::FlushICache(pc + 2, sizeof(Address)); |
Ben Murdoch | 589d697 | 2011-11-30 16:04:58 +0000 | [diff] [blame] | 2729 | } |
| 2730 | } |
Andrei Popescu | 3100271 | 2010-02-23 13:46:05 +0000 | [diff] [blame] | 2731 | |
Ben Murdoch | b8a8cc1 | 2014-11-26 15:28:44 +0000 | [diff] [blame] | 2732 | |
| 2733 | Handle<ConstantPoolArray> Assembler::NewConstantPool(Isolate* isolate) { |
| 2734 | // No out-of-line constant pool support. |
| 2735 | DCHECK(!FLAG_enable_ool_constant_pool); |
| 2736 | return isolate->factory()->empty_constant_pool_array(); |
| 2737 | } |
| 2738 | |
| 2739 | |
| 2740 | void Assembler::PopulateConstantPool(ConstantPoolArray* constant_pool) { |
| 2741 | // No out-of-line constant pool support. |
| 2742 | DCHECK(!FLAG_enable_ool_constant_pool); |
| 2743 | return; |
| 2744 | } |
| 2745 | |
| 2746 | |
Andrei Popescu | 3100271 | 2010-02-23 13:46:05 +0000 | [diff] [blame] | 2747 | } } // namespace v8::internal |
| 2748 | |
Leon Clarke | f7060e2 | 2010-06-03 12:02:55 +0100 | [diff] [blame] | 2749 | #endif // V8_TARGET_ARCH_MIPS |