Ben Murdoch | b8a8cc1 | 2014-11-26 15:28:44 +0000 | [diff] [blame] | 1 | // Copyright 2014 the V8 project authors. All rights reserved. |
| 2 | // Use of this source code is governed by a BSD-style license that can be |
| 3 | // found in the LICENSE file. |
| 4 | |
| 5 | #ifndef V8_COMPILER_INSTRUCTION_CODES_H_ |
| 6 | #define V8_COMPILER_INSTRUCTION_CODES_H_ |
| 7 | |
Emily Bernier | d0a1eb7 | 2015-03-24 16:35:39 -0400 | [diff] [blame] | 8 | #include <iosfwd> |
| 9 | |
Ben Murdoch | b8a8cc1 | 2014-11-26 15:28:44 +0000 | [diff] [blame] | 10 | #if V8_TARGET_ARCH_ARM |
| 11 | #include "src/compiler/arm/instruction-codes-arm.h" |
| 12 | #elif V8_TARGET_ARCH_ARM64 |
| 13 | #include "src/compiler/arm64/instruction-codes-arm64.h" |
| 14 | #elif V8_TARGET_ARCH_IA32 |
| 15 | #include "src/compiler/ia32/instruction-codes-ia32.h" |
Emily Bernier | d0a1eb7 | 2015-03-24 16:35:39 -0400 | [diff] [blame] | 16 | #elif V8_TARGET_ARCH_MIPS |
| 17 | #include "src/compiler/mips/instruction-codes-mips.h" |
| 18 | #elif V8_TARGET_ARCH_MIPS64 |
| 19 | #include "src/compiler/mips64/instruction-codes-mips64.h" |
Ben Murdoch | b8a8cc1 | 2014-11-26 15:28:44 +0000 | [diff] [blame] | 20 | #elif V8_TARGET_ARCH_X64 |
| 21 | #include "src/compiler/x64/instruction-codes-x64.h" |
Ben Murdoch | 4a90d5f | 2016-03-22 12:00:34 +0000 | [diff] [blame] | 22 | #elif V8_TARGET_ARCH_PPC |
| 23 | #include "src/compiler/ppc/instruction-codes-ppc.h" |
Ben Murdoch | da12d29 | 2016-06-02 14:46:10 +0100 | [diff] [blame^] | 24 | #elif V8_TARGET_ARCH_S390 |
| 25 | #include "src/compiler/s390/instruction-codes-s390.h" |
Ben Murdoch | 4a90d5f | 2016-03-22 12:00:34 +0000 | [diff] [blame] | 26 | #elif V8_TARGET_ARCH_X87 |
| 27 | #include "src/compiler/x87/instruction-codes-x87.h" |
Ben Murdoch | b8a8cc1 | 2014-11-26 15:28:44 +0000 | [diff] [blame] | 28 | #else |
| 29 | #define TARGET_ARCH_OPCODE_LIST(V) |
| 30 | #define TARGET_ADDRESSING_MODE_LIST(V) |
| 31 | #endif |
| 32 | #include "src/utils.h" |
| 33 | |
| 34 | namespace v8 { |
| 35 | namespace internal { |
Ben Murdoch | b8a8cc1 | 2014-11-26 15:28:44 +0000 | [diff] [blame] | 36 | namespace compiler { |
| 37 | |
Ben Murdoch | 4a90d5f | 2016-03-22 12:00:34 +0000 | [diff] [blame] | 38 | // Modes for ArchStoreWithWriteBarrier below. |
| 39 | enum class RecordWriteMode { kValueIsMap, kValueIsPointer, kValueIsAny }; |
| 40 | |
| 41 | |
Ben Murdoch | b8a8cc1 | 2014-11-26 15:28:44 +0000 | [diff] [blame] | 42 | // Target-specific opcodes that specify which assembly sequence to emit. |
| 43 | // Most opcodes specify a single instruction. |
Ben Murdoch | da12d29 | 2016-06-02 14:46:10 +0100 | [diff] [blame^] | 44 | #define COMMON_ARCH_OPCODE_LIST(V) \ |
| 45 | V(ArchCallCodeObject) \ |
| 46 | V(ArchTailCallCodeObjectFromJSFunction) \ |
| 47 | V(ArchTailCallCodeObject) \ |
| 48 | V(ArchCallJSFunction) \ |
| 49 | V(ArchTailCallJSFunctionFromJSFunction) \ |
| 50 | V(ArchTailCallJSFunction) \ |
| 51 | V(ArchPrepareCallCFunction) \ |
| 52 | V(ArchCallCFunction) \ |
| 53 | V(ArchPrepareTailCall) \ |
| 54 | V(ArchJmp) \ |
| 55 | V(ArchLookupSwitch) \ |
| 56 | V(ArchTableSwitch) \ |
| 57 | V(ArchNop) \ |
| 58 | V(ArchThrowTerminator) \ |
| 59 | V(ArchDeoptimize) \ |
| 60 | V(ArchRet) \ |
| 61 | V(ArchStackPointer) \ |
| 62 | V(ArchFramePointer) \ |
| 63 | V(ArchParentFramePointer) \ |
| 64 | V(ArchTruncateDoubleToI) \ |
| 65 | V(ArchStoreWithWriteBarrier) \ |
| 66 | V(CheckedLoadInt8) \ |
| 67 | V(CheckedLoadUint8) \ |
| 68 | V(CheckedLoadInt16) \ |
| 69 | V(CheckedLoadUint16) \ |
| 70 | V(CheckedLoadWord32) \ |
| 71 | V(CheckedLoadWord64) \ |
| 72 | V(CheckedLoadFloat32) \ |
| 73 | V(CheckedLoadFloat64) \ |
| 74 | V(CheckedStoreWord8) \ |
| 75 | V(CheckedStoreWord16) \ |
| 76 | V(CheckedStoreWord32) \ |
| 77 | V(CheckedStoreWord64) \ |
| 78 | V(CheckedStoreFloat32) \ |
| 79 | V(CheckedStoreFloat64) \ |
Ben Murdoch | 097c5b2 | 2016-05-18 11:27:45 +0100 | [diff] [blame] | 80 | V(ArchStackSlot) |
Ben Murdoch | 4a90d5f | 2016-03-22 12:00:34 +0000 | [diff] [blame] | 81 | |
| 82 | #define ARCH_OPCODE_LIST(V) \ |
| 83 | COMMON_ARCH_OPCODE_LIST(V) \ |
Ben Murdoch | b8a8cc1 | 2014-11-26 15:28:44 +0000 | [diff] [blame] | 84 | TARGET_ARCH_OPCODE_LIST(V) |
| 85 | |
| 86 | enum ArchOpcode { |
| 87 | #define DECLARE_ARCH_OPCODE(Name) k##Name, |
| 88 | ARCH_OPCODE_LIST(DECLARE_ARCH_OPCODE) |
| 89 | #undef DECLARE_ARCH_OPCODE |
| 90 | #define COUNT_ARCH_OPCODE(Name) +1 |
| 91 | kLastArchOpcode = -1 ARCH_OPCODE_LIST(COUNT_ARCH_OPCODE) |
| 92 | #undef COUNT_ARCH_OPCODE |
| 93 | }; |
| 94 | |
Emily Bernier | d0a1eb7 | 2015-03-24 16:35:39 -0400 | [diff] [blame] | 95 | std::ostream& operator<<(std::ostream& os, const ArchOpcode& ao); |
Ben Murdoch | b8a8cc1 | 2014-11-26 15:28:44 +0000 | [diff] [blame] | 96 | |
| 97 | // Addressing modes represent the "shape" of inputs to an instruction. |
| 98 | // Many instructions support multiple addressing modes. Addressing modes |
| 99 | // are encoded into the InstructionCode of the instruction and tell the |
| 100 | // code generator after register allocation which assembler method to call. |
| 101 | #define ADDRESSING_MODE_LIST(V) \ |
| 102 | V(None) \ |
| 103 | TARGET_ADDRESSING_MODE_LIST(V) |
| 104 | |
| 105 | enum AddressingMode { |
| 106 | #define DECLARE_ADDRESSING_MODE(Name) kMode_##Name, |
| 107 | ADDRESSING_MODE_LIST(DECLARE_ADDRESSING_MODE) |
| 108 | #undef DECLARE_ADDRESSING_MODE |
| 109 | #define COUNT_ADDRESSING_MODE(Name) +1 |
| 110 | kLastAddressingMode = -1 ADDRESSING_MODE_LIST(COUNT_ADDRESSING_MODE) |
| 111 | #undef COUNT_ADDRESSING_MODE |
| 112 | }; |
| 113 | |
Emily Bernier | d0a1eb7 | 2015-03-24 16:35:39 -0400 | [diff] [blame] | 114 | std::ostream& operator<<(std::ostream& os, const AddressingMode& am); |
Ben Murdoch | b8a8cc1 | 2014-11-26 15:28:44 +0000 | [diff] [blame] | 115 | |
| 116 | // The mode of the flags continuation (see below). |
Ben Murdoch | da12d29 | 2016-06-02 14:46:10 +0100 | [diff] [blame^] | 117 | enum FlagsMode { |
| 118 | kFlags_none = 0, |
| 119 | kFlags_branch = 1, |
| 120 | kFlags_deoptimize = 2, |
| 121 | kFlags_set = 3 |
| 122 | }; |
Ben Murdoch | b8a8cc1 | 2014-11-26 15:28:44 +0000 | [diff] [blame] | 123 | |
Emily Bernier | d0a1eb7 | 2015-03-24 16:35:39 -0400 | [diff] [blame] | 124 | std::ostream& operator<<(std::ostream& os, const FlagsMode& fm); |
Ben Murdoch | b8a8cc1 | 2014-11-26 15:28:44 +0000 | [diff] [blame] | 125 | |
| 126 | // The condition of flags continuation (see below). |
| 127 | enum FlagsCondition { |
| 128 | kEqual, |
| 129 | kNotEqual, |
| 130 | kSignedLessThan, |
| 131 | kSignedGreaterThanOrEqual, |
| 132 | kSignedLessThanOrEqual, |
| 133 | kSignedGreaterThan, |
| 134 | kUnsignedLessThan, |
| 135 | kUnsignedGreaterThanOrEqual, |
| 136 | kUnsignedLessThanOrEqual, |
| 137 | kUnsignedGreaterThan, |
Ben Murdoch | 4a90d5f | 2016-03-22 12:00:34 +0000 | [diff] [blame] | 138 | kFloatLessThanOrUnordered, |
| 139 | kFloatGreaterThanOrEqual, |
| 140 | kFloatLessThanOrEqual, |
| 141 | kFloatGreaterThanOrUnordered, |
| 142 | kFloatLessThan, |
| 143 | kFloatGreaterThanOrEqualOrUnordered, |
| 144 | kFloatLessThanOrEqualOrUnordered, |
| 145 | kFloatGreaterThan, |
Ben Murdoch | b8a8cc1 | 2014-11-26 15:28:44 +0000 | [diff] [blame] | 146 | kUnorderedEqual, |
| 147 | kUnorderedNotEqual, |
Ben Murdoch | b8a8cc1 | 2014-11-26 15:28:44 +0000 | [diff] [blame] | 148 | kOverflow, |
| 149 | kNotOverflow |
| 150 | }; |
| 151 | |
Emily Bernier | d0a1eb7 | 2015-03-24 16:35:39 -0400 | [diff] [blame] | 152 | inline FlagsCondition NegateFlagsCondition(FlagsCondition condition) { |
| 153 | return static_cast<FlagsCondition>(condition ^ 1); |
| 154 | } |
| 155 | |
Ben Murdoch | 4a90d5f | 2016-03-22 12:00:34 +0000 | [diff] [blame] | 156 | FlagsCondition CommuteFlagsCondition(FlagsCondition condition); |
| 157 | |
Emily Bernier | d0a1eb7 | 2015-03-24 16:35:39 -0400 | [diff] [blame] | 158 | std::ostream& operator<<(std::ostream& os, const FlagsCondition& fc); |
Ben Murdoch | b8a8cc1 | 2014-11-26 15:28:44 +0000 | [diff] [blame] | 159 | |
| 160 | // The InstructionCode is an opaque, target-specific integer that encodes |
| 161 | // what code to emit for an instruction in the code generator. It is not |
| 162 | // interesting to the register allocator, as the inputs and flags on the |
| 163 | // instructions specify everything of interest. |
| 164 | typedef int32_t InstructionCode; |
| 165 | |
| 166 | // Helpers for encoding / decoding InstructionCode into the fields needed |
| 167 | // for code generation. We encode the instruction, addressing mode, and flags |
| 168 | // continuation into a single InstructionCode which is stored as part of |
| 169 | // the instruction. |
Ben Murdoch | 4a90d5f | 2016-03-22 12:00:34 +0000 | [diff] [blame] | 170 | typedef BitField<ArchOpcode, 0, 8> ArchOpcodeField; |
| 171 | typedef BitField<AddressingMode, 8, 5> AddressingModeField; |
| 172 | typedef BitField<FlagsMode, 13, 2> FlagsModeField; |
| 173 | typedef BitField<FlagsCondition, 15, 5> FlagsConditionField; |
| 174 | typedef BitField<int, 20, 12> MiscField; |
Ben Murdoch | b8a8cc1 | 2014-11-26 15:28:44 +0000 | [diff] [blame] | 175 | |
| 176 | } // namespace compiler |
| 177 | } // namespace internal |
| 178 | } // namespace v8 |
| 179 | |
| 180 | #endif // V8_COMPILER_INSTRUCTION_CODES_H_ |