s390: Valgrind-side changes to fixing bugzilla #274695:
Testcase, vbit tester update, memcheck support for the new IROps,
NEWS announcement and opcode list update.
Patch by Christian Borntraeger (borntraeger@de.ibm.com).
Vbit tester tweaks by myself.
Fixes bugzilla #274695.
See also companion patch VEX r2496.
git-svn-id: svn://svn.valgrind.org/valgrind/trunk@12921 a5019735-40e9-0310-863c-91ae7b9d1cf9
diff --git a/NEWS b/NEWS
index 93fd27f..dfc8e48 100644
--- a/NEWS
+++ b/NEWS
@@ -22,6 +22,7 @@
219156 [380] handle statically linked malloc and/or other malloc libs
254088 [380] Valgrind should know about UD2 instruction
+274695 [380] s390x: Support "compare to/from logical" instructions (new in z196)
275800 [380] s390x: Add support for the ecag instruction (part 1)
284004 [381] == 301281
289584 [381] Unhandled instruction: 0xF 0x29 0xE5 (MOVAPS)
diff --git a/docs/internals/s390-opcodes.csv b/docs/internals/s390-opcodes.csv
index 0c2e625..032ffb1 100644
--- a/docs/internals/s390-opcodes.csv
+++ b/docs/internals/s390-opcodes.csv
@@ -911,24 +911,24 @@
cegbra,"convert from 64 bit fixed to short bfp with rounding mode","not implemented","new to z196"
cdgbra,"convert from 64 bit fixed to long bfp with rounding mode","not implemented","new to z196"
cxgbra,"convert from 64 bit fixed to extended bfp with rounding mode","not implemented","new to z196"
-celfbr,"convert from 32 bit logical fixed to short bfp with rounding mode","not implemented","open bugzilla"
-cdlfbr,"convert from 32 bit logical fixed to long bfp with rounding mode","not implemented","open bugzilla"
-cxlfbr,"convert from 32 bit logical fixed to extended bfp with rounding mode","not implemented","open bugzilla"
-celgbr,"convert from 64 bit logical fixed to short bfp with rounding mode","not implemented","open bugzilla"
-cdlgbr,"convert from 64 bit logical fixed to long bfp with rounding mode","not implemented","open bugzilla"
-cxlgbr,"convert from 64 bit logical fixed to extended bfp with rounding mode","not implemented","open bugzilla"
+celfbr,"convert from 32 bit logical fixed to short bfp with rounding mode",implemented,
+cdlfbr,"convert from 32 bit logical fixed to long bfp with rounding mode",implemented,
+cxlfbr,"convert from 32 bit logical fixed to extended bfp with rounding mode",implemented,
+celgbr,"convert from 64 bit logical fixed to short bfp with rounding mode",implemented,
+cdlgbr,"convert from 64 bit logical fixed to long bfp with rounding mode",implemented,
+cxlgbr,"convert from 64 bit logical fixed to extended bfp with rounding mode",implemented,
cfebra,"convert to 32 bit fixed from short bfp with rounding mode","not implemented","new to z196"
cfdbra,"convert to 32 bit fixed from long bfp with rounding mode","not implemented","new to z196"
cfxbra,"convert to 32 bit fixed from extended bfp with rounding mode","not implemented","new to z196"
cgebra,"convert to 64 bit fixed from short bfp with rounding mode","not implemented","new to z196"
cgdbra,"convert to 64 bit fixed from long bfp with rounding mode","not implemented","new to z196"
cgxbra,"convert to 64 bit fixed from extended bfp with rounding mode","not implemented","new to z196"
-clfebr,"convert to 32 bit fixed logical from short bfp with rounding mode","not implemented","open bugzilla"
-clfdbr,"convert to 32 bit fixed logical from long bfp with rounding mode","not implemented","open bugzilla"
-clfxbr,"convert to 32 bit fixed logical from extended bfp with rounding mode","not implemented","open bugzilla"
-clgebr,"convert to 64 bit fixed logical from short bfp with rounding mode","not implemented","open bugzilla"
-clgdbr,"convert to 64 bit fixed logical from long bfp with rounding mode","not implemented","open bugzilla"
-clgxbr,"convert to 64 bit fixed logical from extended bfp with rounding mode","not implemented","open bugzilla"
+clfebr,"convert to 32 bit fixed logical from short bfp with rounding mode",implemented,
+clfdbr,"convert to 32 bit fixed logical from long bfp with rounding mode",implemented
+clfxbr,"convert to 32 bit fixed logical from extended bfp with rounding mode",implemented
+clgebr,"convert to 64 bit fixed logical from short bfp with rounding mode",implemented
+clgdbr,"convert to 64 bit fixed logical from long bfp with rounding mode",implemented
+clgxbr,"convert to 64 bit fixed logical from extended bfp with rounding mode",implemented
fiebra,"load fp integer short bfp with rounding mode","not implemented","new to z196"
fidbra,"load fp integer long bfp with rounding mode","not implemented","new to z196"
fixbra,"load fp integer extended bfp with rounding mode","not implemented","new to z196"
diff --git a/memcheck/mc_translate.c b/memcheck/mc_translate.c
index 64c375c..b06b3b1 100644
--- a/memcheck/mc_translate.c
+++ b/memcheck/mc_translate.c
@@ -3206,6 +3206,7 @@
/* Scalar floating point */
case Iop_F32toI64S:
+ case Iop_F32toI64U:
/* I32(rm) x F32 -> I64 */
return mkLazy2(mce, Ity_I64, vatom1, vatom2);
@@ -3254,15 +3255,19 @@
return mkLazy2(mce, Ity_I128, vatom1, vatom2);
case Iop_I32StoF32:
+ case Iop_I32UtoF32:
case Iop_F32toI32S:
+ case Iop_F32toI32U:
/* First arg is I32 (rounding mode), second is F32/I32 (data). */
return mkLazy2(mce, Ity_I32, vatom1, vatom2);
case Iop_F128toI32S: /* IRRoundingMode(I32) x F128 -> signed I32 */
+ case Iop_F128toI32U: /* IRRoundingMode(I32) x F128 -> unsigned I32 */
case Iop_F128toF32: /* IRRoundingMode(I32) x F128 -> F32 */
return mkLazy2(mce, Ity_I32, vatom1, vatom2);
case Iop_F128toI64S: /* IRRoundingMode(I32) x F128 -> signed I64 */
+ case Iop_F128toI64U: /* IRRoundingMode(I32) x F128 -> unsigned I64 */
case Iop_F128toF64: /* IRRoundingMode(I32) x F128 -> F64 */
case Iop_D128toD64: /* IRRoundingModeDFP(I64) x D128 -> D64 */
case Iop_D128toI64S: /* IRRoundingModeDFP(I64) x D128 -> signed I64 */
@@ -3611,6 +3616,8 @@
case Iop_I32StoF128: /* signed I32 -> F128 */
case Iop_I64StoF128: /* signed I64 -> F128 */
+ case Iop_I32UtoF128: /* unsigned I32 -> F128 */
+ case Iop_I64UtoF128: /* unsigned I64 -> F128 */
case Iop_F32toF128: /* F32 -> F128 */
case Iop_F64toF128: /* F64 -> F128 */
case Iop_I64StoD128: /* signed I64 -> D128 */
diff --git a/memcheck/tests/vbit-test/irops.c b/memcheck/tests/vbit-test/irops.c
index 10492be..2b627aa 100644
--- a/memcheck/tests/vbit-test/irops.c
+++ b/memcheck/tests/vbit-test/irops.c
@@ -179,15 +179,18 @@
{ DEFOP(Iop_F64toI16S, UNDEF_ALL), .s390x = 0, .amd64 = 0, .x86 = 1, .ppc64 = 0, .ppc32 = 0, .mips32 = 0 },
{ DEFOP(Iop_F64toI32S, UNDEF_ALL), .s390x = 1, .amd64 = 1, .x86 = 1, .ppc64 = 1, .ppc32 = 1, .mips32 = 0 }, // mips asserts
{ DEFOP(Iop_F64toI64S, UNDEF_ALL), .s390x = 1, .amd64 = 1, .x86 = 1, .ppc64 = 1, .ppc32 = 1, .mips32 = 0 },
- { DEFOP(Iop_F64toI64U, UNDEF_ALL), .s390x = 0, .amd64 = 0, .x86 = 0, .ppc64 = 1, .ppc32 = 1, .mips32 = 0 },
- { DEFOP(Iop_F64toI32U, UNDEF_ALL), .s390x = 0, .amd64 = 0, .x86 = 0, .ppc64 = 1, .ppc32 = 1, .mips32 = 0 },
+ { DEFOP(Iop_F64toI64U, UNDEF_ALL), .s390x = 1, .amd64 = 0, .x86 = 0, .ppc64 = 1, .ppc32 = 1, .mips32 = 0 },
+ { DEFOP(Iop_F64toI32U, UNDEF_ALL), .s390x = 1, .amd64 = 0, .x86 = 0, .ppc64 = 1, .ppc32 = 1, .mips32 = 0 },
{ DEFOP(Iop_I32StoF64, UNDEF_ALL), .s390x = 1, .amd64 = 1, .x86 = 1, .ppc64 = 0, .ppc32 = 0, .mips32 = 0 }, // mips asserts
{ DEFOP(Iop_I64StoF64, UNDEF_ALL), .s390x = 1, .amd64 = 1, .x86 = 1, .ppc64 = 1, .ppc32 = 1, .mips32 = 0 },
- { DEFOP(Iop_I64UtoF64, UNDEF_ALL), .s390x = 0, .amd64 = 0, .x86 = 0, .ppc64 = 1, .ppc32 = 1, .mips32 = 0 }, // mips asserts
- { DEFOP(Iop_I64UtoF32, UNDEF_ALL), .s390x = 0, .amd64 = 0, .x86 = 0, .ppc64 = 1, .ppc32 = 1, .mips32 = 0 },
- { DEFOP(Iop_I32UtoF64, UNDEF_ALL), .s390x = 0, .amd64 = 0, .x86 = 0, .ppc64 = 0, .ppc32 = 0, .mips32 = 0 },
+ { DEFOP(Iop_I64UtoF64, UNDEF_ALL), .s390x = 1, .amd64 = 0, .x86 = 0, .ppc64 = 1, .ppc32 = 1, .mips32 = 0 }, // mips asserts
+ { DEFOP(Iop_I64UtoF32, UNDEF_ALL), .s390x = 1, .amd64 = 0, .x86 = 0, .ppc64 = 1, .ppc32 = 1, .mips32 = 0 },
+ { DEFOP(Iop_I32UtoF32, UNDEF_ALL), .s390x = 1, .amd64 = 0, .x86 = 0, .ppc64 = 0, .ppc32 = 0, .mips32 = 0 },
+ { DEFOP(Iop_I32UtoF64, UNDEF_ALL), .s390x = 1, .amd64 = 0, .x86 = 0, .ppc64 = 0, .ppc32 = 0, .mips32 = 0 },
{ DEFOP(Iop_F32toI32S, UNDEF_ALL), .s390x = 1, .amd64 = 0, .x86 = 0, .ppc64 = 0, .ppc32 = 0, .mips32 = 0 },
{ DEFOP(Iop_F32toI64S, UNDEF_ALL), .s390x = 1, .amd64 = 0, .x86 = 0, .ppc64 = 0, .ppc32 = 0, .mips32 = 0 },
+ { DEFOP(Iop_F32toI32U, UNDEF_ALL), .s390x = 1, .amd64 = 0, .x86 = 0, .ppc64 = 0, .ppc32 = 0, .mips32 = 0 },
+ { DEFOP(Iop_F32toI64U, UNDEF_ALL), .s390x = 1, .amd64 = 0, .x86 = 0, .ppc64 = 0, .ppc32 = 0, .mips32 = 0 },
{ DEFOP(Iop_I32StoF32, UNDEF_ALL), .s390x = 1, .amd64 = 0, .x86 = 0, .ppc64 = 0, .ppc32 = 0, .mips32 = 1 },
{ DEFOP(Iop_I64StoF32, UNDEF_ALL), .s390x = 1, .amd64 = 0, .x86 = 0, .ppc64 = 0, .ppc32 = 0, .mips32 = 0 },
{ DEFOP(Iop_F32toF64, UNDEF_ALL), .s390x = 1, .amd64 = 1, .x86 = 1, .ppc64 = 1, .ppc32 = 1, .mips32 = 0 }, // mips asserts
@@ -210,10 +213,14 @@
{ DEFOP(Iop_SqrtF128, UNDEF_ALL), .s390x = 1, .amd64 = 0, .x86 = 0, .ppc64 = 0, .ppc32 = 0, .mips32 = 0 },
{ DEFOP(Iop_I32StoF128, UNDEF_ALL), .s390x = 1, .amd64 = 0, .x86 = 0, .ppc64 = 0, .ppc32 = 0, .mips32 = 0 },
{ DEFOP(Iop_I64StoF128, UNDEF_ALL), .s390x = 1, .amd64 = 0, .x86 = 0, .ppc64 = 0, .ppc32 = 0, .mips32 = 0 },
+ { DEFOP(Iop_I32UtoF128, UNDEF_ALL), .s390x = 1, .amd64 = 0, .x86 = 0, .ppc64 = 0, .ppc32 = 0, .mips32 = 0 },
+ { DEFOP(Iop_I64UtoF128, UNDEF_ALL), .s390x = 1, .amd64 = 0, .x86 = 0, .ppc64 = 0, .ppc32 = 0, .mips32 = 0 },
{ DEFOP(Iop_F32toF128, UNDEF_ALL), .s390x = 1, .amd64 = 0, .x86 = 0, .ppc64 = 0, .ppc32 = 0, .mips32 = 0 },
{ DEFOP(Iop_F64toF128, UNDEF_ALL), .s390x = 1, .amd64 = 0, .x86 = 0, .ppc64 = 0, .ppc32 = 0, .mips32 = 0 },
{ DEFOP(Iop_F128toI32S, UNDEF_ALL), .s390x = 1, .amd64 = 0, .x86 = 0, .ppc64 = 0, .ppc32 = 0, .mips32 = 0 },
{ DEFOP(Iop_F128toI64S, UNDEF_ALL), .s390x = 1, .amd64 = 0, .x86 = 0, .ppc64 = 0, .ppc32 = 0, .mips32 = 0 },
+ { DEFOP(Iop_F128toI32U, UNDEF_ALL), .s390x = 1, .amd64 = 0, .x86 = 0, .ppc64 = 0, .ppc32 = 0, .mips32 = 0 },
+ { DEFOP(Iop_F128toI64U, UNDEF_ALL), .s390x = 1, .amd64 = 0, .x86 = 0, .ppc64 = 0, .ppc32 = 0, .mips32 = 0 },
{ DEFOP(Iop_F128toF64, UNDEF_ALL), .s390x = 1, .amd64 = 0, .x86 = 0, .ppc64 = 0, .ppc32 = 0, .mips32 = 0 },
{ DEFOP(Iop_F128toF32, UNDEF_ALL), .s390x = 1, .amd64 = 0, .x86 = 0, .ppc64 = 0, .ppc32 = 0, .mips32 = 0 },
{ DEFOP(Iop_AtanF64, UNDEF_ALL), .s390x = 0, .amd64 = 1, .x86 = 1, .ppc64 = 0, .ppc32 = 0, .mips32 = 0 },
@@ -861,6 +868,28 @@
const irop_t *p = irops + i;
if (p->op == op) {
#ifdef __s390x__
+#define S390X_FEATURES "../../../tests/s390x_features"
+ switch (op) {
+ case Iop_I32UtoF32:
+ case Iop_I32UtoF64:
+ case Iop_I32UtoF128:
+ case Iop_I64UtoF32:
+ case Iop_I64UtoF64:
+ case Iop_I64UtoF128:
+ case Iop_F32toI32U:
+ case Iop_F32toI64U:
+ case Iop_F64toI32U:
+ case Iop_F64toI64U:
+ case Iop_F128toI32U:
+ case Iop_F128toI64U: {
+ int rc;
+ /* These IROps require the floating point extension facility */
+ rc = system(S390X_FEATURES " s390x-fpext");
+ // s390x_features returns 1 if features exists
+ rc /= 256;
+ if (rc != 0) return NULL;
+ }
+ }
return p->s390x ? p : NULL;
#endif
#ifdef __x86_64__
diff --git a/memcheck/tests/vbit-test/util.c b/memcheck/tests/vbit-test/util.c
index 4aa62b9..966a73b 100644
--- a/memcheck/tests/vbit-test/util.c
+++ b/memcheck/tests/vbit-test/util.c
@@ -518,7 +518,10 @@
case Iop_F32toI32S: BINARY(ity_RMode,Ity_F32, Ity_I32);
case Iop_F32toI64S: BINARY(ity_RMode,Ity_F32, Ity_I64);
-
+ case Iop_F32toI32U: BINARY(ity_RMode,Ity_F32, Ity_I32);
+ case Iop_F32toI64U: BINARY(ity_RMode,Ity_F32, Ity_I64);
+
+ case Iop_I32UtoF32: BINARY(ity_RMode,Ity_I32, Ity_F32);
case Iop_I32StoF32: BINARY(ity_RMode,Ity_I32, Ity_F32);
case Iop_I64StoF32: BINARY(ity_RMode,Ity_I64, Ity_F32);
@@ -805,9 +808,15 @@
case Iop_I32StoF128: UNARY(Ity_I32, Ity_F128);
case Iop_I64StoF128: UNARY(Ity_I64, Ity_F128);
+ case Iop_I32UtoF128: UNARY(Ity_I32, Ity_F128);
+ case Iop_I64UtoF128: UNARY(Ity_I64, Ity_F128);
+
case Iop_F128toI32S: BINARY(ity_RMode,Ity_F128, Ity_I32);
case Iop_F128toI64S: BINARY(ity_RMode,Ity_F128, Ity_I64);
+ case Iop_F128toI32U: BINARY(ity_RMode,Ity_F128, Ity_I32);
+ case Iop_F128toI64U: BINARY(ity_RMode,Ity_F128, Ity_I64);
+
case Iop_F32toF128: UNARY(Ity_F32, Ity_F128);
case Iop_F64toF128: UNARY(Ity_F64, Ity_F128);
diff --git a/none/tests/s390x/Makefile.am b/none/tests/s390x/Makefile.am
index 91b9963..203bd34 100644
--- a/none/tests/s390x/Makefile.am
+++ b/none/tests/s390x/Makefile.am
@@ -8,7 +8,7 @@
op_exception fgx stck stckf stcke stfle cksm mvcl clcl troo \
trto trot trtt tr tre cij cgij clij clgij crj cgrj clrj clgrj \
cs csg cds cdsg cu21 cu21_1 cu24 cu24_1 cu42 cu12 cu12_1 \
- ex_sig ex_clone cu14 cu14_1 cu41 fpconv ecag
+ ex_sig ex_clone cu14 cu14_1 cu41 fpconv ecag fpext
check_PROGRAMS = $(INSN_TESTS) \
allexec \
diff --git a/none/tests/s390x/fpext.c b/none/tests/s390x/fpext.c
new file mode 100644
index 0000000..64e7a47
--- /dev/null
+++ b/none/tests/s390x/fpext.c
@@ -0,0 +1,147 @@
+#include <float.h>
+#include <stdio.h>
+#include "opcodes.h"
+
+
+#define L2F(insn, initial, target,round) \
+({ \
+ register unsigned long source asm("2") = initial; \
+ register typeof(target) _t asm("f0"); \
+ asm volatile(insn(round,0,0,2) :"=f" (_t):"d"(source)); \
+ _t; \
+})
+
+#define F2L(insn, initial, type, round, cc) \
+({ \
+ register type source asm("f0") = initial; \
+ register unsigned long target asm ("2") = 0; \
+ asm volatile(insn(round,0,2,0) \
+ "ipm %1\n\t" \
+ "srl %1,28\n\t" \
+ :"=d" (target), "=d" (cc) :"f"(source):"cc"); \
+ target; \
+})
+
+
+#define DO_INSN_L2F32(insn, round) \
+({ \
+ float f32; \
+ printf(#insn " %f\n", L2F(insn, 0, f32, round)); \
+ printf(#insn " %f\n", L2F(insn, 1, f32, round)); \
+ printf(#insn " %f\n", L2F(insn, 0xffffffffUL, f32, round)); \
+ printf(#insn " %f\n", L2F(insn, 0x80000000UL, f32, round)); \
+ printf(#insn " %f\n", L2F(insn, 0x7fffffffUL, f32, round)); \
+ printf(#insn " %f\n", L2F(insn, 0x100000000UL, f32, round)); \
+ printf(#insn " %f\n", L2F(insn, 0xffffffffffffffffUL, f32, round)); \
+ printf(#insn " %f\n", L2F(insn, 0x8000000000000000UL, f32, round)); \
+ printf(#insn " %f\n", L2F(insn, 0x7fffffffffffffffUL, f32, round)); \
+})
+
+#define DO_INSN_L2F64(insn, round) \
+({ \
+ double f64; \
+ printf(#insn " %f\n", L2F(insn, 0, f64, round)); \
+ printf(#insn " %f\n", L2F(insn, 1, f64, round)); \
+ printf(#insn " %f\n", L2F(insn, 0xffffffffUL, f64, round)); \
+ printf(#insn " %f\n", L2F(insn, 0x80000000UL, f64, round)); \
+ printf(#insn " %f\n", L2F(insn, 0x7fffffffUL, f64, round)); \
+ printf(#insn " %f\n", L2F(insn, 0x100000000UL, f64, round)); \
+ printf(#insn " %f\n", L2F(insn, 0xffffffffffffffffUL, f64, round)); \
+ printf(#insn " %f\n", L2F(insn, 0x8000000000000000UL, f64, round)); \
+ printf(#insn " %f\n", L2F(insn, 0x7fffffffffffffffUL, f64, round)); \
+})
+
+#define DO_INSN_L2F128(insn, round) \
+({ \
+ long double f128; \
+ printf(#insn " %Lf\n", L2F(insn, 0, f128, round)); \
+ printf(#insn " %Lf\n", L2F(insn, 1, f128, round)); \
+ printf(#insn " %Lf\n", L2F(insn, 0xffffffffUL, f128, round)); \
+ printf(#insn " %Lf\n", L2F(insn, 0x80000000UL, f128, round)); \
+ printf(#insn " %Lf\n", L2F(insn, 0x7fffffffUL, f128, round)); \
+ printf(#insn " %Lf\n", L2F(insn, 0x100000000UL, f128, round)); \
+ printf(#insn " %Lf\n", L2F(insn, 0xffffffffffffffffUL, f128, round)); \
+ printf(#insn " %Lf\n", L2F(insn, 0x8000000000000000UL, f128, round)); \
+ printf(#insn " %Lf\n", L2F(insn, 0x7fffffffffffffffUL, f128, round)); \
+})
+
+#define DO_INSN_F2L(insn, round, type) \
+({ \
+ int cc; \
+ printf(#insn " %lu ", F2L(insn, -1.1, type, round, cc)); \
+ printf("cc=%d\n", cc); \
+ printf(#insn " %lu ", F2L(insn, 0, type, round, cc)); \
+ printf("cc=%d\n", cc); \
+ printf(#insn " %lu ", F2L(insn, 1, type, round, cc)); \
+ printf("cc=%d\n", cc); \
+ printf(#insn " %lu ", F2L(insn, 1.4, type, round, cc)); \
+ printf("cc=%d\n", cc); \
+ printf(#insn " %lu ", F2L(insn, 1.5, type, round, cc)); \
+ printf("cc=%d\n", cc); \
+ printf(#insn " %lu ", F2L(insn, 1.6, type, round, cc)); \
+ printf("cc=%d\n", cc); \
+ printf(#insn " %lu ", F2L(insn, 1.6E+4, type, round, cc)); \
+ printf("cc=%d\n", cc); \
+ printf(#insn " %lu ", F2L(insn, 1.6E+8, type, round, cc)); \
+ printf("cc=%d\n", cc); \
+ printf(#insn " %lu ", F2L(insn, 1.6E+12, type, round, cc)); \
+ printf("cc=%d\n", cc); \
+ printf(#insn " %lu ", F2L(insn, 1.6E+20, type, round, cc)); \
+ printf("cc=%d\n", cc); \
+ printf(#insn " %lu ", F2L(insn, 1.6E+200, type, round, cc)); \
+ printf("cc=%d\n", cc); \
+ printf(#insn " %lu ", F2L(insn, 1.6E+2000L, type, round, cc)); \
+ printf("cc=%d\n", cc); \
+ printf(#insn " %lu ", F2L(insn, 1.6E-4, type, round, cc)); \
+ printf("cc=%d\n", cc); \
+ printf(#insn " %lu ", F2L(insn, FLT_MIN, type, round, cc)); \
+ printf("cc=%d\n", cc); \
+ printf(#insn " %lu ", F2L(insn, FLT_MAX, type, round, cc)); \
+ printf("cc=%d\n", cc); \
+ printf(#insn " %lu ", F2L(insn, DBL_MIN, type, round, cc)); \
+ printf("cc=%d\n", cc); \
+ printf(#insn " %lu ", F2L(insn, DBL_MAX, type, round, cc)); \
+ printf("cc=%d\n", cc); \
+ printf(#insn " %lu ", F2L(insn, LDBL_MIN, type, round, cc)); \
+ printf("cc=%d\n", cc); \
+ printf(#insn " %lu ", F2L(insn, LDBL_MAX, type, round, cc)); \
+ printf("cc=%d\n", cc); \
+})
+
+#define DO_L2F(round) \
+({ \
+ DO_INSN_L2F32(CELFBR, round); \
+ DO_INSN_L2F32(CELGBR, round); \
+ DO_INSN_L2F64(CDLFBR, round); \
+ DO_INSN_L2F64(CDLGBR, round); \
+ DO_INSN_L2F128(CXLFBR, round); \
+ DO_INSN_L2F128(CXLGBR, round); \
+})
+
+#define DO_F2L(round) \
+({ \
+ DO_INSN_F2L(CLFEBR, round, float); \
+ DO_INSN_F2L(CLGEBR, round, float); \
+ DO_INSN_F2L(CLFDBR, round, double); \
+ DO_INSN_F2L(CLGDBR, round, double); \
+ DO_INSN_F2L(CLFXBR, round, long double); \
+ DO_INSN_F2L(CLGXBR, round, long double); \
+})
+
+
+int main()
+{
+ DO_L2F(4);
+ DO_F2L(4);
+
+ DO_L2F(5);
+ DO_F2L(5);
+
+ DO_L2F(6);
+ DO_F2L(6);
+
+ DO_L2F(7);
+ DO_F2L(7);
+
+ return 0;
+}
diff --git a/none/tests/s390x/fpext.stderr.exp b/none/tests/s390x/fpext.stderr.exp
new file mode 100644
index 0000000..139597f
--- /dev/null
+++ b/none/tests/s390x/fpext.stderr.exp
@@ -0,0 +1,2 @@
+
+
diff --git a/none/tests/s390x/fpext.stdout.exp b/none/tests/s390x/fpext.stdout.exp
new file mode 100644
index 0000000..48fbda0
--- /dev/null
+++ b/none/tests/s390x/fpext.stdout.exp
@@ -0,0 +1,672 @@
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+CLGDBR 18446744073709551615 cc=3
+CLFXBR 0 cc=3
+CLFXBR 0 cc=0
+CLFXBR 1 cc=2
+CLFXBR 1 cc=2
+CLFXBR 1 cc=2
+CLFXBR 1 cc=2
+CLFXBR 16000 cc=2
+CLFXBR 160000000 cc=2
+CLFXBR 4294967295 cc=3
+CLFXBR 4294967295 cc=3
+CLFXBR 4294967295 cc=3
+CLFXBR 4294967295 cc=3
+CLFXBR 0 cc=2
+CLFXBR 0 cc=2
+CLFXBR 4294967295 cc=3
+CLFXBR 0 cc=2
+CLFXBR 4294967295 cc=3
+CLFXBR 0 cc=2
+CLFXBR 4294967295 cc=3
+CLGXBR 0 cc=3
+CLGXBR 0 cc=0
+CLGXBR 1 cc=2
+CLGXBR 1 cc=2
+CLGXBR 1 cc=2
+CLGXBR 1 cc=2
+CLGXBR 16000 cc=2
+CLGXBR 160000000 cc=2
+CLGXBR 1600000000000 cc=2
+CLGXBR 18446744073709551615 cc=3
+CLGXBR 18446744073709551615 cc=3
+CLGXBR 18446744073709551615 cc=3
+CLGXBR 0 cc=2
+CLGXBR 0 cc=2
+CLGXBR 18446744073709551615 cc=3
+CLGXBR 0 cc=2
+CLGXBR 18446744073709551615 cc=3
+CLGXBR 0 cc=2
+CLGXBR 18446744073709551615 cc=3
diff --git a/none/tests/s390x/fpext.vgtest b/none/tests/s390x/fpext.vgtest
new file mode 100644
index 0000000..4740430
--- /dev/null
+++ b/none/tests/s390x/fpext.vgtest
@@ -0,0 +1,2 @@
+prog: fpext
+prereq: ../../../tests/s390x_features s390x-fpext
diff --git a/none/tests/s390x/opcodes.h b/none/tests/s390x/opcodes.h
index 149dbe8..afde5fb 100644
--- a/none/tests/s390x/opcodes.h
+++ b/none/tests/s390x/opcodes.h
@@ -68,6 +68,9 @@
".short 0x" #op1 #r1 #r3 "\n\t" \
".long 0x" #b2 #dl2 #dh2 #op2 "\n\t"
#define RRF_F0FF2(op,r3,u0,r1,r2) ".long 0x" #op #r3 #u0 #r1 #r2 "\n\t"
+#define RRF_UUFR(op,m3,m4,r1,r2) ".long 0x" #op #m3 #m4 #r1 #r2 "\n\t"
+#define RRF_UURF(op,m3,m4,r1,r2) ".long 0x" #op #m3 #m4 #r1 #r2 "\n\t"
+
#define RSY_RRRD(op1,r1,r3,b2,dl2,dh2,op2) \
".short 0x" #op1 #r1 #r3 "\n\t" \
".long 0x" #b2 #dl2 #dh2 #op2 "\n\t"
@@ -121,6 +124,10 @@
#define ARK(r3,r1,r2) RRF_R0RR2(b9f8,r3,0,r1,r2)
#define ASI(i2,b1,dl1,dh1) SIY_IRD(eb,i2,b1,dl1,dh1,6a)
#define AY(r1,x2,b2,dl2,dh2) RXY_RRRD(e3,r1,x2,b2,dl2,dh2,5a)
+#define CDLFBR(m3,m4,r1,r2) RRF_UUFR(b391,m3,m4,r1,r2)
+#define CDLGBR(m3,m4,r1,r2) RRF_UUFR(b3a1,m3,m4,r1,r2)
+#define CELFBR(m3,m4,r1,r2) RRF_UUFR(b390,m3,m4,r1,r2)
+#define CELGBR(m3,m4,r1,r2) RRF_UUFR(b3a0,m3,m4,r1,r2)
#define CFI(r1,i2) RIL_RI(c2,r1,d,i2)
#define CGFI(r1,i2) RIL_RI(c2,r1,c,i2)
#define CGFRL(r1,i2) RIL_RP(c6,r1,c,i2)
@@ -142,8 +149,13 @@
#define CIB(r1,m3,b4,d4,i2) RIS_RURDI(ec,r1,m3,b4,d4,i2,fe)
#define CIH(r1,i2) RIL_RI(cc,r1,d,i2)
#define CIJ(r1,m3,i4,i2) RIE_RUPI(ec,r1,m3,i4,i2,7e)
+#define CLFEBR(m3,m4,r1,r2) RRF_UURF(b39c,m3,m4,r1,r2)
+#define CLFDBR(m3,m4,r1,r2) RRF_UURF(b39d,m3,m4,r1,r2)
+#define CLFXBR(m3,m4,r1,r2) RRF_UURF(b39e,m3,m4,r1,r2)
#define CLFHSI(b1,d1,i2) SIL_RDU(e55d,b1,d1,i2)
#define CLFI(r1,i2) RIL_RU(c2,r1,f,i2)
+#define CLGDBR(m3,m4,r1,r2) RRF_UURF(b3ad,m3,m4,r1,r2)
+#define CLGEBR(m3,m4,r1,r2) RRF_UURF(b3ac,m3,m4,r1,r2)
#define CLGFI(r1,i2) RIL_RU(c2,r1,e,i2)
#define CLGFRL(r1,i2) RIL_RP(c6,r1,e,i2)
#define CLGHRL(r1,i2) RIL_RP(c6,r1,6,i2)
@@ -153,6 +165,7 @@
#define CLGRB(r1,r2,b4,d4,m3) RRS(ec,r1,r2,b4,d4,m3,0,e5)
#define CLGRJ(r1,r2,i4,m3) RIE_RRPU(ec,r1,r2,i4,m3,0,65)
#define CLGRL(r1,i2) RIL_RP(c6,r1,a,i2)
+#define CLGXBR(m3,m4,r1,r2) RRF_UURF(b3ae,m3,m4,r1,r2)
#define CLHF(r1,x2,b2,dl2,dh2) RXY_RRRD(e3,r1,x2,b2,dl2,dh2,cf)
#define CLHHR(r1,r2) RRE_RR(b9cf,00,r1,r2)
#define CLHHSI(b1,d1,i2) SIL_RDU(e555,b1,d1,i2)
@@ -180,6 +193,8 @@
#define CU42(r1,r2) RRE_RERE(b9b3,r1,r2)
#define CVBY(r1,x2,b2,dl2,dh2) RXY_RRRD(e3,r1,x2,b2,dl2,dh2,06)
#define CVDY(r1,x2,b2,dl2,dh2) RXY_RRRD(e3,r1,x2,b2,dl2,dh2,26)
+#define CXLFBR(m3,m4,r1,r2) RRF_UUFR(b392,m3,m4,r1,r2)
+#define CXLGBR(m3,m4,r1,r2) RRF_UUFR(b3a2,m3,m4,r1,r2)
#define CY(r1,x2,b2,dl2,dh2) RXY_RRRD(e3,r1,x2,b2,dl2,dh2,59)
#define EXRL(r1,i2) RIL_RP(c6,r1,0,i2)
#define FLOGR(r1,r2) RRE_RR(b983,00,r1,r2)