Add files I forgot to when I committed Tom Hughes' patch for bug 73907.
git-svn-id: svn://svn.valgrind.org/valgrind/trunk@2243 a5019735-40e9-0310-863c-91ae7b9d1cf9
diff --git a/none/tests/insn_basic.def b/none/tests/insn_basic.def
new file mode 100644
index 0000000..4d87903
--- /dev/null
+++ b/none/tests/insn_basic.def
@@ -0,0 +1,1083 @@
+aaa eflags[0x11,0x01] al.ub[0x1] ah.ub[0x0] : => al.ub[0x1] ah.ub[0x00] eflags[0x11,0x00]
+aaa eflags[0x11,0x01] al.ub[0x9] ah.ub[0x0] : => al.ub[0x9] ah.ub[0x00] eflags[0x11,0x00]
+aaa eflags[0x11,0x00] al.ub[0xa] ah.ub[0x0] : => al.ub[0x0] ah.ub[0x01] eflags[0x11,0x11]
+aaa eflags[0x11,0x00] al.ub[0xf] ah.ub[0x0] : => al.ub[0x5] ah.ub[0x01] eflags[0x11,0x11]
+aaa eflags[0x11,0x10] al.ub[0x1] ah.ub[0x0] : => al.ub[0x7] ah.ub[0x01] eflags[0x11,0x11]
+aaa eflags[0x11,0x10] al.ub[0x9] ah.ub[0x0] : => al.ub[0xf] ah.ub[0x01] eflags[0x11,0x11]
+aaa eflags[0x11,0x10] al.ub[0xa] ah.ub[0x0] : => al.ub[0x0] ah.ub[0x01] eflags[0x11,0x11]
+aaa eflags[0x11,0x10] al.ub[0xf] ah.ub[0x0] : => al.ub[0x5] ah.ub[0x01] eflags[0x11,0x11]
+aad al.ub[37] ah.ub[2] : => al.ub[57] ah.ub[0]
+aad al.ub[73] ah.ub[2] : => al.ub[93] ah.ub[0]
+aam al.ub[37] ah.ub[0] : => al.ub[7] ah.ub[3]
+aam al.ub[73] ah.ub[0] : => al.ub[3] ah.ub[7]
+aas eflags[0x11,0x01] al.ub[0x1] ah.ub[0x2] : => al.ub[0x1] ah.ub[0x02] eflags[0x11,0x00]
+aas eflags[0x11,0x01] al.ub[0x9] ah.ub[0x2] : => al.ub[0x9] ah.ub[0x02] eflags[0x11,0x00]
+aas eflags[0x11,0x00] al.ub[0xa] ah.ub[0x2] : => al.ub[0x4] ah.ub[0x01] eflags[0x11,0x11]
+aas eflags[0x11,0x00] al.ub[0xf] ah.ub[0x2] : => al.ub[0x9] ah.ub[0x01] eflags[0x11,0x11]
+aas eflags[0x11,0x10] al.ub[0x1] ah.ub[0x2] : => al.ub[0xb] ah.ub[0x00] eflags[0x11,0x11]
+aas eflags[0x11,0x10] al.ub[0x9] ah.ub[0x2] : => al.ub[0x3] ah.ub[0x01] eflags[0x11,0x11]
+aas eflags[0x11,0x10] al.ub[0xa] ah.ub[0x2] : => al.ub[0x4] ah.ub[0x01] eflags[0x11,0x11]
+aas eflags[0x11,0x10] al.ub[0xf] ah.ub[0x2] : => al.ub[0x9] ah.ub[0x01] eflags[0x11,0x11]
+adcb eflags[0x1,0x0] : imm8[12] al.ub[34] => 1.ub[46]
+adcb eflags[0x1,0x1] : imm8[12] al.ub[34] => 1.ub[47]
+adcb eflags[0x1,0x0] : imm8[12] bl.ub[34] => 1.ub[46]
+adcb eflags[0x1,0x1] : imm8[12] bl.ub[34] => 1.ub[47]
+adcb eflags[0x1,0x0] : imm8[12] m8.ub[34] => 1.ub[46]
+adcb eflags[0x1,0x1] : imm8[12] m8.ub[34] => 1.ub[47]
+adcb eflags[0x1,0x0] : r8.ub[12] r8.ub[34] => 1.ub[46]
+adcb eflags[0x1,0x1] : r8.ub[12] r8.ub[34] => 1.ub[47]
+adcb eflags[0x1,0x0] : r8.ub[12] m8.ub[34] => 1.ub[46]
+adcb eflags[0x1,0x1] : r8.ub[12] m8.ub[34] => 1.ub[47]
+adcb eflags[0x1,0x0] : m8.ub[12] r8.ub[34] => 1.ub[46]
+adcb eflags[0x1,0x1] : m8.ub[12] r8.ub[34] => 1.ub[47]
+adcw eflags[0x1,0x0] : imm8[12] r16.uw[3456] => 1.uw[3468]
+adcw eflags[0x1,0x1] : imm8[12] r16.uw[3456] => 1.uw[3469]
+adcw eflags[0x1,0x0] : imm16[1234] ax.uw[5678] => 1.uw[6912]
+adcw eflags[0x1,0x1] : imm16[1234] ax.uw[5678] => 1.uw[6913]
+adcw eflags[0x1,0x0] : imm16[1234] bx.uw[5678] => 1.uw[6912]
+adcw eflags[0x1,0x1] : imm16[1234] bx.uw[5678] => 1.uw[6913]
+adcw eflags[0x1,0x0] : imm16[1234] m16.uw[5678] => 1.uw[6912]
+adcw eflags[0x1,0x1] : imm16[1234] m16.uw[5678] => 1.uw[6913]
+adcw eflags[0x1,0x0] : r16.uw[1234] r16.uw[5678] => 1.uw[6912]
+adcw eflags[0x1,0x1] : r16.uw[1234] r16.uw[5678] => 1.uw[6913]
+adcw eflags[0x1,0x0] : r16.uw[1234] m16.uw[5678] => 1.uw[6912]
+adcw eflags[0x1,0x1] : r16.uw[1234] m16.uw[5678] => 1.uw[6913]
+adcw eflags[0x1,0x0] : m16.uw[1234] r16.uw[5678] => 1.uw[6912]
+adcw eflags[0x1,0x1] : m16.uw[1234] r16.uw[5678] => 1.uw[6913]
+adcl eflags[0x1,0x0] : imm8[12] r32.ud[87654321] => 1.ud[87654333]
+adcl eflags[0x1,0x1] : imm8[12] r32.ud[87654321] => 1.ud[87654334]
+adcl eflags[0x1,0x0] : imm32[12345678] eax.ud[87654321] => 1.ud[99999999]
+adcl eflags[0x1,0x1] : imm32[12345678] eax.ud[87654321] => 1.ud[100000000]
+adcl eflags[0x1,0x0] : imm32[12345678] ebx.ud[87654321] => 1.ud[99999999]
+adcl eflags[0x1,0x1] : imm32[12345678] ebx.ud[87654321] => 1.ud[100000000]
+adcl eflags[0x1,0x0] : imm32[12345678] m32.ud[87654321] => 1.ud[99999999]
+adcl eflags[0x1,0x1] : imm32[12345678] m32.ud[87654321] => 1.ud[100000000]
+adcl eflags[0x1,0x0] : r32.ud[12345678] r32.ud[87654321] => 1.ud[99999999]
+adcl eflags[0x1,0x1] : r32.ud[12345678] r32.ud[87654321] => 1.ud[100000000]
+adcl eflags[0x1,0x0] : r32.ud[12345678] m32.ud[87654321] => 1.ud[99999999]
+adcl eflags[0x1,0x1] : r32.ud[12345678] m32.ud[87654321] => 1.ud[100000000]
+adcl eflags[0x1,0x0] : m32.ud[12345678] r32.ud[87654321] => 1.ud[99999999]
+adcl eflags[0x1,0x1] : m32.ud[12345678] r32.ud[87654321] => 1.ud[100000000]
+addb imm8[12] al.ub[34] => 1.ub[46]
+addb imm8[12] bl.ub[34] => 1.ub[46]
+addb imm8[12] m8.ub[34] => 1.ub[46]
+addb r8.ub[12] r8.ub[34] => 1.ub[46]
+addb r8.ub[12] m8.ub[34] => 1.ub[46]
+addb m8.ub[12] r8.ub[34] => 1.ub[46]
+addw imm8[12] r16.uw[3456] => 1.uw[3468]
+addw imm16[1234] ax.uw[5678] => 1.uw[6912]
+addw imm16[1234] bx.uw[5678] => 1.uw[6912]
+addw imm16[1234] m16.uw[5678] => 1.uw[6912]
+addw r16.uw[1234] r16.uw[5678] => 1.uw[6912]
+addw r16.uw[1234] m16.uw[5678] => 1.uw[6912]
+addw m16.uw[1234] r16.uw[5678] => 1.uw[6912]
+addl imm8[12] r32.ud[87654321] => 1.ud[87654333]
+addl imm32[12345678] eax.ud[87654321] => 1.ud[99999999]
+addl imm32[12345678] ebx.ud[87654321] => 1.ud[99999999]
+addl imm32[12345678] m32.ud[87654321] => 1.ud[99999999]
+addl r32.ud[12345678] r32.ud[87654321] => 1.ud[99999999]
+addl r32.ud[12345678] m32.ud[87654321] => 1.ud[99999999]
+addl m32.ud[12345678] r32.ud[87654321] => 1.ud[99999999]
+andb imm8[0x34] al.ub[0x56] => 1.ub[0x14]
+andb imm8[0x34] bl.ub[0x56] => 1.ub[0x14]
+andb imm8[0x34] m8.ub[0x56] => 1.ub[0x14]
+andb r8.ub[0x34] r8.ub[0x56] => 1.ub[0x14]
+andb r8.ub[0x34] m8.ub[0x56] => 1.ub[0x14]
+andb m8.ub[0x34] r8.ub[0x56] => 1.ub[0x14]
+andw imm8[0x31] r16.uw[0x1234] => 1.uw[0x0030]
+andw imm16[0x4231] ax.uw[0x1234] => 1.uw[0x0230]
+andw imm16[0x4231] bx.uw[0x1234] => 1.uw[0x0230]
+andw imm16[0x4231] m16.uw[0x1234] => 1.uw[0x0230]
+andw r16.uw[0x4231] r16.uw[0x1234] => 1.uw[0x0230]
+andw r16.uw[0x4231] m16.uw[0x1234] => 1.uw[0x0230]
+andw m16.uw[0x4231] r16.uw[0x1234] => 1.uw[0x0230]
+andl imm8[0x31] r32.ud[0x12345678] => 1.ud[0x00000030]
+andl imm32[0x86427531] eax.ud[0x12345678] => 1.ud[0x02005430]
+andl imm32[0x86427531] ebx.ud[0x12345678] => 1.ud[0x02005430]
+andl imm32[0x86427531] m32.ud[0x12345678] => 1.ud[0x02005430]
+andl r32.ud[0x86427531] r32.ud[0x12345678] => 1.ud[0x02005430]
+andl r32.ud[0x86427531] m32.ud[0x12345678] => 1.ud[0x02005430]
+andl m32.ud[0x86427531] r32.ud[0x12345678] => 1.ud[0x02005430]
+bsfw r16.uw[0x2468] r16.uw[0] => 1.uw[3]
+bsfw m16.uw[0x8642] r16.uw[0] => 1.uw[1]
+bsfl r32.ud[0x13572468] r32.ud[0] => 1.ud[3]
+bsfl m32.ud[0x75318642] r32.ud[0] => 1.ud[1]
+bsrw r16.uw[0x2468] r16.uw[0] => 1.uw[13]
+bsrw m16.uw[0x8642] r16.uw[0] => 1.uw[15]
+bsrl r32.ud[0x13572468] r32.ud[0] => 1.ud[28]
+bsrl m32.ud[0x75318642] r32.ud[0] => 1.ud[30]
+bswapl r32.ud[0x12345678] => 0.ud[0x78563412]
+btw imm8[0] r16.uw[0x4231] => 1.uw[0x4231] eflags[0x001,0x001]
+btw imm8[12] r16.uw[0x4231] => 1.uw[0x4231] eflags[0x001,0x000]
+btw imm8[0] m16.uw[0x4231] => 1.uw[0x4231] eflags[0x001,0x001]
+btw imm8[12] m16.uw[0x4231] => 1.uw[0x4231] eflags[0x001,0x000]
+btw r16.uw[0] r16.uw[0x4231] => 1.uw[0x4231] eflags[0x001,0x001]
+btw r16.uw[12] r16.uw[0x4231] => 1.uw[0x4231] eflags[0x001,0x000]
+btw r16.uw[0] m16.uw[0x4231] => 1.uw[0x4231] eflags[0x001,0x001]
+btw r16.uw[12] m16.uw[0x4231] => 1.uw[0x4231] eflags[0x001,0x000]
+btl imm8[0] r32.ud[0x86427531] => 1.ud[0x86427531] eflags[0x001,0x001]
+btl imm8[24] r32.ud[0x86427531] => 1.ud[0x86427531] eflags[0x001,0x000]
+btl imm8[0] m32.ud[0x86427531] => 1.ud[0x86427531] eflags[0x001,0x001]
+btl imm8[24] m32.ud[0x86427531] => 1.ud[0x86427531] eflags[0x001,0x000]
+btl r32.ud[0] r32.ud[0x86427531] => 1.ud[0x86427531] eflags[0x001,0x001]
+btl r32.ud[24] r32.ud[0x86427531] => 1.ud[0x86427531] eflags[0x001,0x000]
+btl r32.ud[0] m32.ud[0x86427531] => 1.ud[0x86427531] eflags[0x001,0x001]
+btl r32.ud[24] m32.ud[0x86427531] => 1.ud[0x86427531] eflags[0x001,0x000]
+btcw imm8[0] r16.uw[0x4231] => 1.uw[0x4230] eflags[0x001,0x001]
+btcw imm8[12] r16.uw[0x4231] => 1.uw[0x5231] eflags[0x001,0x000]
+btcw imm8[0] m16.uw[0x4231] => 1.uw[0x4230] eflags[0x001,0x001]
+btcw imm8[12] m16.uw[0x4231] => 1.uw[0x5231] eflags[0x001,0x000]
+btcw r16.uw[0] r16.uw[0x4231] => 1.uw[0x4230] eflags[0x001,0x001]
+btcw r16.uw[12] r16.uw[0x4231] => 1.uw[0x5231] eflags[0x001,0x000]
+btcw r16.uw[0] m16.uw[0x4231] => 1.uw[0x4230] eflags[0x001,0x001]
+btcw r16.uw[12] m16.uw[0x4231] => 1.uw[0x5231] eflags[0x001,0x000]
+btcl imm8[0] r32.ud[0x86427531] => 1.ud[0x86427530] eflags[0x001,0x001]
+btcl imm8[24] r32.ud[0x86427531] => 1.ud[0x87427531] eflags[0x001,0x000]
+btcl imm8[0] m32.ud[0x86427531] => 1.ud[0x86427530] eflags[0x001,0x001]
+btcl imm8[24] m32.ud[0x86427531] => 1.ud[0x87427531] eflags[0x001,0x000]
+btcl r32.ud[0] r32.ud[0x86427531] => 1.ud[0x86427530] eflags[0x001,0x001]
+btcl r32.ud[24] r32.ud[0x86427531] => 1.ud[0x87427531] eflags[0x001,0x000]
+btcl r32.ud[0] m32.ud[0x86427531] => 1.ud[0x86427530] eflags[0x001,0x001]
+btcl r32.ud[24] m32.ud[0x86427531] => 1.ud[0x87427531] eflags[0x001,0x000]
+btrw imm8[0] r16.uw[0x4231] => 1.uw[0x4230] eflags[0x001,0x001]
+btrw imm8[12] r16.uw[0x4231] => 1.uw[0x4231] eflags[0x001,0x000]
+btrw imm8[0] m16.uw[0x4231] => 1.uw[0x4230] eflags[0x001,0x001]
+btrw imm8[12] m16.uw[0x4231] => 1.uw[0x4231] eflags[0x001,0x000]
+btrw r16.uw[0] r16.uw[0x4231] => 1.uw[0x4230] eflags[0x001,0x001]
+btrw r16.uw[12] r16.uw[0x4231] => 1.uw[0x4231] eflags[0x001,0x000]
+btrw r16.uw[0] m16.uw[0x4231] => 1.uw[0x4230] eflags[0x001,0x001]
+btrw r16.uw[12] m16.uw[0x4231] => 1.uw[0x4231] eflags[0x001,0x000]
+btrl imm8[0] r32.ud[0x86427531] => 1.ud[0x86427530] eflags[0x001,0x001]
+btrl imm8[24] r32.ud[0x86427531] => 1.ud[0x86427531] eflags[0x001,0x000]
+btrl imm8[0] m32.ud[0x86427531] => 1.ud[0x86427530] eflags[0x001,0x001]
+btrl imm8[24] m32.ud[0x86427531] => 1.ud[0x86427531] eflags[0x001,0x000]
+btrl r32.ud[0] r32.ud[0x86427531] => 1.ud[0x86427530] eflags[0x001,0x001]
+btrl r32.ud[24] r32.ud[0x86427531] => 1.ud[0x86427531] eflags[0x001,0x000]
+btrl r32.ud[0] m32.ud[0x86427531] => 1.ud[0x86427530] eflags[0x001,0x001]
+btrl r32.ud[24] m32.ud[0x86427531] => 1.ud[0x86427531] eflags[0x001,0x000]
+btsw imm8[0] r16.uw[0x4231] => 1.uw[0x4231] eflags[0x001,0x001]
+btsw imm8[12] r16.uw[0x4231] => 1.uw[0x5231] eflags[0x001,0x000]
+btsw imm8[0] m16.uw[0x4231] => 1.uw[0x4231] eflags[0x001,0x001]
+btsw imm8[12] m16.uw[0x4231] => 1.uw[0x5231] eflags[0x001,0x000]
+btsw r16.uw[0] r16.uw[0x4231] => 1.uw[0x4231] eflags[0x001,0x001]
+btsw r16.uw[12] r16.uw[0x4231] => 1.uw[0x5231] eflags[0x001,0x000]
+btsw r16.uw[0] m16.uw[0x4231] => 1.uw[0x4231] eflags[0x001,0x001]
+btsw r16.uw[12] m16.uw[0x4231] => 1.uw[0x5231] eflags[0x001,0x000]
+btsl imm8[0] r32.ud[0x86427531] => 1.ud[0x86427531] eflags[0x001,0x001]
+btsl imm8[24] r32.ud[0x86427531] => 1.ud[0x87427531] eflags[0x001,0x000]
+btsl imm8[0] m32.ud[0x86427531] => 1.ud[0x86427531] eflags[0x001,0x001]
+btsl imm8[24] m32.ud[0x86427531] => 1.ud[0x87427531] eflags[0x001,0x000]
+btsl r32.ud[0] r32.ud[0x86427531] => 1.ud[0x86427531] eflags[0x001,0x001]
+btsl r32.ud[24] r32.ud[0x86427531] => 1.ud[0x87427531] eflags[0x001,0x000]
+btsl r32.ud[0] m32.ud[0x86427531] => 1.ud[0x86427531] eflags[0x001,0x001]
+btsl r32.ud[24] m32.ud[0x86427531] => 1.ud[0x87427531] eflags[0x001,0x000]
+cbw al.sb[123] : => ax.sw[123]
+cbw al.sb[-123] : => ax.sw[-123]
+cdq eax.ud[0x12345678] : => edx.ud[0x00000000] eax.ud[0x12345678]
+cdq eax.ud[0xfedcba98] : => edx.ud[0xffffffff] eax.ud[0xfedcba98]
+clc eflags[0x001,0x000] : => eflags[0x001,0x000]
+clc eflags[0x001,0x001] : => eflags[0x001,0x000]
+cld eflags[0x400,0x000] : => eflags[0x400,0x000]
+cld eflags[0x400,0x400] : => eflags[0x400,0x000]
+cmc eflags[0x001,0x000] : => eflags[0x001,0x001]
+cmc eflags[0x001,0x001] : => eflags[0x001,0x000]
+cmpb imm8[3] al.ub[2] => eflags[0x010,0x010]
+cmpb imm8[2] al.ub[3] => eflags[0x010,0x000]
+cmpb imm8[12] al.ub[12] => eflags[0x044,0x044]
+cmpb imm8[12] al.ub[34] => eflags[0x044,0x000]
+cmpb imm8[34] al.ub[12] => eflags[0x081,0x081]
+cmpb imm8[12] al.ub[34] => eflags[0x081,0x000]
+cmpb imm8[100] al.sb[-100] => eflags[0x800,0x800]
+cmpb imm8[50] al.sb[-50] => eflags[0x800,0x000]
+cmpb imm8[-50] al.sb[50] => eflags[0x800,0x000]
+cmpb imm8[-100] al.sb[100] => eflags[0x800,0x800]
+cmpb imm8[3] r8.ub[2] => eflags[0x010,0x010]
+cmpb imm8[2] r8.ub[3] => eflags[0x010,0x000]
+cmpb imm8[12] r8.ub[12] => eflags[0x044,0x044]
+cmpb imm8[12] r8.ub[34] => eflags[0x044,0x000]
+cmpb imm8[34] r8.ub[12] => eflags[0x081,0x081]
+cmpb imm8[12] r8.ub[34] => eflags[0x081,0x000]
+cmpb imm8[100] r8.sb[-100] => eflags[0x800,0x800]
+cmpb imm8[50] r8.sb[-50] => eflags[0x800,0x000]
+cmpb imm8[-50] r8.sb[50] => eflags[0x800,0x000]
+cmpb imm8[-100] r8.sb[100] => eflags[0x800,0x800]
+cmpb imm8[3] m8.ub[2] => eflags[0x010,0x010]
+cmpb imm8[2] m8.ub[3] => eflags[0x010,0x000]
+cmpb imm8[12] m8.ub[12] => eflags[0x044,0x044]
+cmpb imm8[12] m8.ub[34] => eflags[0x044,0x000]
+cmpb imm8[34] m8.ub[12] => eflags[0x081,0x081]
+cmpb imm8[12] m8.ub[34] => eflags[0x081,0x000]
+cmpb imm8[100] m8.sb[-100] => eflags[0x800,0x800]
+cmpb imm8[50] m8.sb[-50] => eflags[0x800,0x000]
+cmpb imm8[-50] m8.sb[50] => eflags[0x800,0x000]
+cmpb imm8[-100] m8.sb[100] => eflags[0x800,0x800]
+cmpb r8.ub[3] r8.ub[2] => eflags[0x010,0x010]
+cmpb r8.ub[2] r8.ub[3] => eflags[0x010,0x000]
+cmpb r8.ub[12] r8.ub[12] => eflags[0x044,0x044]
+cmpb r8.ub[12] r8.ub[34] => eflags[0x044,0x000]
+cmpb r8.ub[34] r8.ub[12] => eflags[0x081,0x081]
+cmpb r8.ub[12] r8.ub[34] => eflags[0x081,0x000]
+cmpb r8.ub[100] r8.sb[-100] => eflags[0x800,0x800]
+cmpb r8.ub[50] r8.sb[-50] => eflags[0x800,0x000]
+cmpb r8.sb[-50] r8.sb[50] => eflags[0x800,0x000]
+cmpb r8.sb[-100] r8.sb[100] => eflags[0x800,0x800]
+cmpb r8.ub[3] m8.ub[2] => eflags[0x010,0x010]
+cmpb r8.ub[2] m8.ub[3] => eflags[0x010,0x000]
+cmpb r8.ub[12] m8.ub[12] => eflags[0x044,0x044]
+cmpb r8.ub[12] m8.ub[34] => eflags[0x044,0x000]
+cmpb r8.ub[34] m8.ub[12] => eflags[0x081,0x081]
+cmpb r8.ub[12] m8.ub[34] => eflags[0x081,0x000]
+cmpb r8.ub[100] m8.sb[-100] => eflags[0x800,0x800]
+cmpb r8.ub[50] m8.sb[-50] => eflags[0x800,0x000]
+cmpb r8.sb[-50] m8.sb[50] => eflags[0x800,0x000]
+cmpb r8.sb[-100] m8.sb[100] => eflags[0x800,0x800]
+cmpb m8.ub[3] r8.ub[2] => eflags[0x010,0x010]
+cmpb m8.ub[2] r8.ub[3] => eflags[0x010,0x000]
+cmpb m8.ub[12] r8.ub[12] => eflags[0x044,0x044]
+cmpb m8.ub[12] r8.ub[34] => eflags[0x044,0x000]
+cmpb m8.ub[34] r8.ub[12] => eflags[0x081,0x081]
+cmpb m8.ub[12] r8.ub[34] => eflags[0x081,0x000]
+cmpb m8.ub[100] r8.sb[-100] => eflags[0x800,0x800]
+cmpb m8.ub[50] r8.sb[-50] => eflags[0x800,0x000]
+cmpb m8.sb[-50] r8.sb[50] => eflags[0x800,0x000]
+cmpb m8.sb[-100] r8.sb[100] => eflags[0x800,0x800]
+cmpw imm8[3] r16.uw[2] => eflags[0x010,0x010]
+cmpw imm8[2] r16.uw[3] => eflags[0x010,0x000]
+cmpw imm8[12] r16.uw[12] => eflags[0x044,0x044]
+cmpw imm8[12] r16.uw[34] => eflags[0x044,0x000]
+cmpw imm8[34] r16.uw[12] => eflags[0x081,0x081]
+cmpw imm8[12] r16.uw[34] => eflags[0x081,0x000]
+cmpw imm8[100] r16.sw[-32700] => eflags[0x800,0x800]
+cmpw imm8[50] r16.sw[-50] => eflags[0x800,0x000]
+cmpw imm8[-50] r16.sw[50] => eflags[0x800,0x000]
+cmpw imm8[-100] r16.sw[32700] => eflags[0x800,0x800]
+cmpw imm8[3] m16.uw[2] => eflags[0x010,0x010]
+cmpw imm8[2] m16.uw[3] => eflags[0x010,0x000]
+cmpw imm8[12] m16.uw[12] => eflags[0x044,0x044]
+cmpw imm8[12] m16.uw[34] => eflags[0x044,0x000]
+cmpw imm8[34] m16.uw[12] => eflags[0x081,0x081]
+cmpw imm8[12] m16.uw[34] => eflags[0x081,0x000]
+cmpw imm8[100] m16.sw[-32700] => eflags[0x800,0x800]
+cmpw imm8[50] m16.sw[-50] => eflags[0x800,0x000]
+cmpw imm8[-50] m16.sw[50] => eflags[0x800,0x000]
+cmpw imm8[-100] m16.sw[32700] => eflags[0x800,0x800]
+cmpw imm16[3] ax.uw[2] => eflags[0x010,0x010]
+cmpw imm16[2] ax.uw[3] => eflags[0x010,0x000]
+cmpw imm16[12] ax.uw[12] => eflags[0x044,0x044]
+cmpw imm16[12] ax.uw[34] => eflags[0x044,0x000]
+cmpw imm16[34] ax.uw[12] => eflags[0x081,0x081]
+cmpw imm16[12] ax.uw[34] => eflags[0x081,0x000]
+cmpw imm16[100] ax.sw[-32700] => eflags[0x800,0x800]
+cmpw imm16[50] ax.sw[-50] => eflags[0x800,0x000]
+cmpw imm16[-50] ax.sw[50] => eflags[0x800,0x000]
+cmpw imm16[-100] ax.sw[32700] => eflags[0x800,0x800]
+cmpw imm16[3] r16.uw[2] => eflags[0x010,0x010]
+cmpw imm16[2] r16.uw[3] => eflags[0x010,0x000]
+cmpw imm16[12] r16.uw[12] => eflags[0x044,0x044]
+cmpw imm16[12] r16.uw[34] => eflags[0x044,0x000]
+cmpw imm16[34] r16.uw[12] => eflags[0x081,0x081]
+cmpw imm16[12] r16.uw[34] => eflags[0x081,0x000]
+cmpw imm16[100] r16.sw[-32700] => eflags[0x800,0x800]
+cmpw imm16[50] r16.sw[-50] => eflags[0x800,0x000]
+cmpw imm16[-50] r16.sw[50] => eflags[0x800,0x000]
+cmpw imm16[-100] r16.sw[32700] => eflags[0x800,0x800]
+cmpw imm16[3] m16.uw[2] => eflags[0x010,0x010]
+cmpw imm16[2] m16.uw[3] => eflags[0x010,0x000]
+cmpw imm16[12] m16.uw[12] => eflags[0x044,0x044]
+cmpw imm16[12] m16.uw[34] => eflags[0x044,0x000]
+cmpw imm16[34] m16.uw[12] => eflags[0x081,0x081]
+cmpw imm16[12] m16.uw[34] => eflags[0x081,0x000]
+cmpw imm16[100] m16.sw[-32700] => eflags[0x800,0x800]
+cmpw imm16[50] m16.sw[-50] => eflags[0x800,0x000]
+cmpw imm16[-50] m16.sw[50] => eflags[0x800,0x000]
+cmpw imm16[-100] m16.sw[32700] => eflags[0x800,0x800]
+cmpw r16.uw[3] r16.uw[2] => eflags[0x010,0x010]
+cmpw r16.uw[2] r16.uw[3] => eflags[0x010,0x000]
+cmpw r16.uw[12] r16.uw[12] => eflags[0x044,0x044]
+cmpw r16.uw[12] r16.uw[34] => eflags[0x044,0x000]
+cmpw r16.uw[34] r16.uw[12] => eflags[0x081,0x081]
+cmpw r16.uw[12] r16.uw[34] => eflags[0x081,0x000]
+cmpw r16.uw[100] r16.sw[-32700] => eflags[0x800,0x800]
+cmpw r16.uw[50] r16.sw[-50] => eflags[0x800,0x000]
+cmpw r16.sw[-50] r16.sw[50] => eflags[0x800,0x000]
+cmpw r16.sw[-100] r16.sw[32700] => eflags[0x800,0x800]
+cmpw r16.uw[3] m16.uw[2] => eflags[0x010,0x010]
+cmpw r16.uw[2] m16.uw[3] => eflags[0x010,0x000]
+cmpw r16.uw[12] m16.uw[12] => eflags[0x044,0x044]
+cmpw r16.uw[12] m16.uw[34] => eflags[0x044,0x000]
+cmpw r16.uw[34] m16.uw[12] => eflags[0x081,0x081]
+cmpw r16.uw[12] m16.uw[34] => eflags[0x081,0x000]
+cmpw r16.uw[100] m16.sw[-32700] => eflags[0x800,0x800]
+cmpw r16.uw[50] m16.sw[-50] => eflags[0x800,0x000]
+cmpw r16.sw[-50] m16.sw[50] => eflags[0x800,0x000]
+cmpw r16.sw[-100] m16.sw[32700] => eflags[0x800,0x800]
+cmpw m16.uw[3] r16.uw[2] => eflags[0x010,0x010]
+cmpw m16.uw[2] r16.uw[3] => eflags[0x010,0x000]
+cmpw m16.uw[12] r16.uw[12] => eflags[0x044,0x044]
+cmpw m16.uw[12] r16.uw[34] => eflags[0x044,0x000]
+cmpw m16.uw[34] r16.uw[12] => eflags[0x081,0x081]
+cmpw m16.uw[12] r16.uw[34] => eflags[0x081,0x000]
+cmpw m16.uw[100] r16.sw[-32700] => eflags[0x800,0x800]
+cmpw m16.uw[50] r16.sw[-50] => eflags[0x800,0x000]
+cmpw m16.sw[-50] r16.sw[50] => eflags[0x800,0x000]
+cmpw m16.sw[-100] r16.sw[32700] => eflags[0x800,0x800]
+cmpl imm8[3] r32.ud[2] => eflags[0x010,0x010]
+cmpl imm8[2] r32.ud[3] => eflags[0x010,0x000]
+cmpl imm8[12] r32.ud[12] => eflags[0x044,0x044]
+cmpl imm8[12] r32.ud[34] => eflags[0x044,0x000]
+cmpl imm8[34] r32.ud[12] => eflags[0x081,0x081]
+cmpl imm8[12] r32.ud[34] => eflags[0x081,0x000]
+cmpl imm8[100] r32.sd[-2147483600] => eflags[0x800,0x800]
+cmpl imm8[50] r32.sd[-50] => eflags[0x800,0x000]
+cmpl imm8[-50] r32.sd[50] => eflags[0x800,0x000]
+cmpl imm8[-100] r32.sd[2147483600] => eflags[0x800,0x800]
+cmpl imm8[3] m32.ud[2] => eflags[0x010,0x010]
+cmpl imm8[2] m32.ud[3] => eflags[0x010,0x000]
+cmpl imm8[12] m32.ud[12] => eflags[0x044,0x044]
+cmpl imm8[12] m32.ud[34] => eflags[0x044,0x000]
+cmpl imm8[34] m32.ud[12] => eflags[0x081,0x081]
+cmpl imm8[12] m32.ud[34] => eflags[0x081,0x000]
+cmpl imm8[100] m32.sd[-2147483600] => eflags[0x800,0x800]
+cmpl imm8[50] m32.sd[-50] => eflags[0x800,0x000]
+cmpl imm8[-50] m32.sd[50] => eflags[0x800,0x000]
+cmpl imm8[-100] m32.sd[2147483600] => eflags[0x800,0x800]
+cmpl imm32[3] eax.ud[2] => eflags[0x010,0x010]
+cmpl imm32[2] eax.ud[3] => eflags[0x010,0x000]
+cmpl imm32[12] eax.ud[12] => eflags[0x044,0x044]
+cmpl imm32[12] eax.ud[34] => eflags[0x044,0x000]
+cmpl imm32[34] eax.ud[12] => eflags[0x081,0x081]
+cmpl imm32[12] eax.ud[34] => eflags[0x081,0x000]
+cmpl imm32[100] eax.sd[-2147483600] => eflags[0x800,0x800]
+cmpl imm32[50] eax.sd[-50] => eflags[0x800,0x000]
+cmpl imm32[-50] eax.sd[50] => eflags[0x800,0x000]
+cmpl imm32[-100] eax.sd[2147483600] => eflags[0x800,0x800]
+cmpl imm32[3] r32.ud[2] => eflags[0x010,0x010]
+cmpl imm32[2] r32.ud[3] => eflags[0x010,0x000]
+cmpl imm32[12] r32.ud[12] => eflags[0x044,0x044]
+cmpl imm32[12] r32.ud[34] => eflags[0x044,0x000]
+cmpl imm32[34] r32.ud[12] => eflags[0x081,0x081]
+cmpl imm32[12] r32.ud[34] => eflags[0x081,0x000]
+cmpl imm32[100] r32.sd[-2147483600] => eflags[0x800,0x800]
+cmpl imm32[50] r32.sd[-50] => eflags[0x800,0x000]
+cmpl imm32[-50] r32.sd[50] => eflags[0x800,0x000]
+cmpl imm32[-100] r32.sd[2147483600] => eflags[0x800,0x800]
+cmpl imm32[3] m32.ud[2] => eflags[0x010,0x010]
+cmpl imm32[2] m32.ud[3] => eflags[0x010,0x000]
+cmpl imm32[12] m32.ud[12] => eflags[0x044,0x044]
+cmpl imm32[12] m32.ud[34] => eflags[0x044,0x000]
+cmpl imm32[34] m32.ud[12] => eflags[0x081,0x081]
+cmpl imm32[12] m32.ud[34] => eflags[0x081,0x000]
+cmpl imm32[100] m32.sd[-2147483600] => eflags[0x800,0x800]
+cmpl imm32[50] m32.sd[-50] => eflags[0x800,0x000]
+cmpl imm32[-50] m32.sd[50] => eflags[0x800,0x000]
+cmpl imm32[-100] m32.sd[2147483600] => eflags[0x800,0x800]
+cmpl r32.ud[3] r32.ud[2] => eflags[0x010,0x010]
+cmpl r32.ud[2] r32.ud[3] => eflags[0x010,0x000]
+cmpl r32.ud[12] r32.ud[12] => eflags[0x044,0x044]
+cmpl r32.ud[12] r32.ud[34] => eflags[0x044,0x000]
+cmpl r32.ud[34] r32.ud[12] => eflags[0x081,0x081]
+cmpl r32.ud[12] r32.ud[34] => eflags[0x081,0x000]
+cmpl r32.ud[100] r32.sd[-2147483600] => eflags[0x800,0x800]
+cmpl r32.ud[50] r32.sd[-50] => eflags[0x800,0x000]
+cmpl r32.sd[-50] r32.sd[50] => eflags[0x800,0x000]
+cmpl r32.sd[-100] r32.sd[2147483600] => eflags[0x800,0x800]
+cmpl r32.ud[3] m32.ud[2] => eflags[0x010,0x010]
+cmpl r32.ud[2] m32.ud[3] => eflags[0x010,0x000]
+cmpl r32.ud[12] m32.ud[12] => eflags[0x044,0x044]
+cmpl r32.ud[12] m32.ud[34] => eflags[0x044,0x000]
+cmpl r32.ud[34] m32.ud[12] => eflags[0x081,0x081]
+cmpl r32.ud[12] m32.ud[34] => eflags[0x081,0x000]
+cmpl r32.ud[100] m32.sd[-2147483600] => eflags[0x800,0x800]
+cmpl r32.ud[50] m32.sd[-50] => eflags[0x800,0x000]
+cmpl r32.sd[-50] m32.sd[50] => eflags[0x800,0x000]
+cmpl r32.sd[-100] m32.sd[2147483600] => eflags[0x800,0x800]
+cmpl m32.ud[3] r32.ud[2] => eflags[0x010,0x010]
+cmpl m32.ud[2] r32.ud[3] => eflags[0x010,0x000]
+cmpl m32.ud[12] r32.ud[12] => eflags[0x044,0x044]
+cmpl m32.ud[12] r32.ud[34] => eflags[0x044,0x000]
+cmpl m32.ud[34] r32.ud[12] => eflags[0x081,0x081]
+cmpl m32.ud[12] r32.ud[34] => eflags[0x081,0x000]
+cmpl m32.ud[100] r32.sd[-2147483600] => eflags[0x800,0x800]
+cmpl m32.ud[50] r32.sd[-50] => eflags[0x800,0x000]
+cmpl m32.sd[-50] r32.sd[50] => eflags[0x800,0x000]
+cmpl m32.sd[-100] r32.sd[2147483600] => eflags[0x800,0x800]
+cmpxchgb eflags[0x40,0x00] ax.uw[12] : r8.ub[56] r8.ub[12] => eflags[0x40,0x40] al.ub[12] 0.ub[56] 1.ub[56]
+cmpxchgb eflags[0x40,0x40] al.ub[12] : r8.ub[56] r8.ub[34] => eflags[0x40,0x00] al.ub[34] 0.ub[56] 1.ub[34]
+cmpxchgb eflags[0x40,0x00] al.ub[12] : r8.ub[56] m8.ub[12] => eflags[0x40,0x40] al.ub[12] 0.ub[56] 1.ub[56]
+cmpxchgb eflags[0x40,0x40] al.ub[12] : r8.ub[56] m8.ub[34] => eflags[0x40,0x00] al.ub[34] 0.ub[56] 1.ub[34]
+cmpxchgw eflags[0x40,0x00] ax.uw[123] : r16.uw[567] r16.uw[123] => eflags[0x40,0x40] ax.uw[123] 0.uw[567] 1.uw[567]
+cmpxchgw eflags[0x40,0x40] ax.uw[123] : r16.uw[567] r16.uw[345] => eflags[0x40,0x00] ax.uw[345] 0.uw[567] 1.uw[345]
+cmpxchgw eflags[0x40,0x00] ax.uw[123] : r16.uw[567] m16.uw[123] => eflags[0x40,0x40] ax.uw[123] 0.uw[567] 1.uw[567]
+cmpxchgw eflags[0x40,0x40] ax.uw[123] : r16.uw[567] m16.uw[345] => eflags[0x40,0x00] ax.uw[345] 0.uw[567] 1.uw[345]
+cmpxchgl eflags[0x40,0x00] eax.ud[1234] : r32.ud[5678] r32.ud[1234] => eflags[0x40,0x40] eax.ud[1234] 0.ud[5678] 1.ud[5678]
+cmpxchgl eflags[0x40,0x40] eax.ud[1234] : r32.ud[5678] r32.ud[3456] => eflags[0x40,0x00] eax.ud[3456] 0.ud[5678] 1.ud[3456]
+cmpxchgl eflags[0x40,0x00] eax.ud[1234] : r32.ud[5678] m32.ud[1234] => eflags[0x40,0x40] eax.ud[1234] 0.ud[5678] 1.ud[5678]
+cmpxchgl eflags[0x40,0x40] eax.ud[1234] : r32.ud[5678] m32.ud[3456] => eflags[0x40,0x00] eax.ud[3456] 0.ud[5678] 1.ud[3456]
+cwd ax.uw[0x1234] : => dx.uw[0x0000] ax.uw[0x1234]
+cwd ax.uw[0xfedc] : => dx.uw[0xffff] ax.uw[0xfedc]
+cwde ax.sw[12345] : => eax.sd[12345]
+cwde ax.sw[-12345] : => eax.sd[-12345]
+daa eflags[0x8d5,0x880] al.ub[0xae] : => al.ub[0x14] eflags[0xd5,0x15]
+daa eflags[0x8d5,0x880] al.ub[0x2e] : => al.ub[0x34] eflags[0xd5,0x10]
+das eflags[0x8d5,0x895] al.ub[0xee] : => al.ub[0x88] eflags[0xd5,0x95]
+decb r8.ub[123] => 0.ub[122]
+decb m8.ub[123] => 0.ub[122]
+decw r16.uw[12345] => 0.uw[12344]
+decw m16.uw[12345] => 0.uw[12344]
+decl r32.ud[12345678] => 0.ud[12345677]
+decl m32.ud[12345678] => 0.ud[12345677]
+divb ax.uw[30276] : r8.ub[123] => al.ub[246] ah.ub[18]
+divb ax.uw[30276] : m8.ub[123] => al.ub[246] ah.ub[18]
+divw dx.uw[464] ax.uw[58794] : r16.uw[12345] => ax.uw[2468] dx.uw[38]
+divw dx.uw[464] ax.uw[58794] : m16.uw[12345] => ax.uw[2468] dx.uw[38]
+divl edx.ud[251958] eax.ud[673192206] : r32.ud[87654321] => eax.ud[12345678] edx.ud[20783136]
+divl edx.ud[251958] eax.ud[673192206] : m32.ud[87654321] => eax.ud[12345678] edx.ud[20783136]
+idivb ax.sw[-15157] : r8.sb[123] => al.sb[-123] ah.sb[-28]
+idivb ax.sw[15157] : m8.sb[-123] => al.sb[-123] ah.sb[28]
+idivw dx.sw[-464] ax.sw[-23456] : r16.sw[12345] => ax.sw[-2459] dx.sw[-10269]
+idivw dx.sw[464] ax.sw[23456] : m16.sw[-12345] => ax.sw[-2465] dx.sw[1735]
+idivl edx.sd[-251959] eax.sd[-673192206] : r32.sd[87654321] => eax.sd[-12345678] edx.sd[-20783136]
+idivl edx.sd[251958] eax.sd[673192206] : m32.sd[-87654321] => eax.sd[-12345678] edx.sd[20783136]
+imulb al.sb[123] : r8.sb[-123] => ax.sw[-15129]
+imulb al.sb[-123] : m8.sb[123] => ax.sw[-15129]
+imulw ax.sw[-12345] : r16.sw[12345] => dx.sw[-2326] ax.sw[-27825]
+imulw ax.sw[12345] : m16.sw[-12345] => dx.sw[-2326] ax.sw[-27825]
+imull eax.sd[-12345678] : r32.sd[12345678] => edx.sd[-35488] eax.sd[-260846532]
+imull eax.sd[12345678] : m32.sd[-12345678] => edx.sd[-35488] eax.sd[-260846532]
+imulw imm8[123] r16.uw[456] => 1.uw[56088]
+imulw imm8[123] r16.uw[456] r16.uw[0] => 2.uw[56088]
+imulw imm8[123] m16.uw[456] r16.uw[0] => 2.uw[56088]
+imulw imm16[123] r16.uw[456] => 1.uw[56088]
+imulw imm16[123] r16.uw[456] r16.uw[0] => 2.uw[56088]
+imulw imm16[123] m16.uw[456] r16.uw[0] => 2.uw[56088]
+imulw r16.uw[123] r16.uw[456] => 1.uw[56088]
+imulw m16.uw[123] r16.uw[456] => 1.uw[56088]
+imull imm8[123] r32.ud[67890] => 1.ud[8350470]
+imull imm8[123] r32.ud[67890] r32.ud[0] => 2.ud[8350470]
+imull imm8[123] m32.ud[67890] r32.ud[0] => 2.ud[8350470]
+imull imm32[12345] r32.ud[67890] => 1.ud[838102050]
+imull imm32[12345] r32.ud[67890] r32.ud[0] => 2.ud[838102050]
+imull imm32[12345] m32.ud[67890] r32.ud[0] => 2.ud[838102050]
+imull r32.ud[12345] r32.ud[67890] => 1.ud[838102050]
+imull m32.ud[12345] r32.ud[67890] => 1.ud[838102050]
+incb r8.ub[123] => 0.ub[124]
+incb m8.ub[123] => 0.ub[124]
+incw r16.uw[12345] => 0.uw[12346]
+incw m16.uw[12345] => 0.uw[12346]
+incl r32.ud[12345678] => 0.ud[12345679]
+incl m32.ud[12345678] => 0.ud[12345679]
+lahf eflags[0xff,0xfd] ah.ub[0x28] : => ah.ub[0xd7]
+lahf eflags[0xff,0x28] ah.ub[0xfd] : => ah.ub[0x02]
+movb imm8[123] r8.ub[0] => 1.ub[123]
+movb imm8[123] m8.ub[0] => 1.ub[123]
+movb r8.ub[123] r8.ub[0] => 1.ub[123]
+movb r8.ub[123] m8.ub[0] => 1.ub[123]
+movb m8.ub[123] r8.ub[0] => 1.ub[123]
+movw imm16[12345] r16.uw[0] => 1.uw[12345]
+movw imm16[12345] m16.uw[0] => 1.uw[12345]
+movw r16.uw[12345] r16.uw[0] => 1.uw[12345]
+movw r16.uw[12345] m16.uw[0] => 1.uw[12345]
+movw m16.uw[12345] r16.uw[0] => 1.uw[12345]
+movl imm32[12345678] r32.ud[0] => 1.ud[12345678]
+movl imm32[12345678] m32.ud[0] => 1.ud[12345678]
+movl r32.ud[12345678] r32.ud[0] => 1.ud[12345678]
+movl r32.ud[12345678] m32.ud[0] => 1.ud[12345678]
+movl m32.ud[12345678] r32.ud[0] => 1.ud[12345678]
+movsbw r8.sb[123] r16.sw[0] => 1.sw[123]
+movsbw m8.sb[-123] r16.sw[0] => 1.sw[-123]
+movsbl r8.sb[123] r32.sd[0] => 1.sd[123]
+movsbl m8.sb[-123] r32.sd[0] => 1.sd[-123]
+movswl r16.sw[12345] r32.sd[0] => 1.sd[12345]
+movswl m16.sw[-12345] r32.sd[0] => 1.sd[-12345]
+movzbw r8.ub[123] r16.uw[0] => 1.uw[123]
+movzbw m8.ub[246] r16.uw[0] => 1.uw[246]
+movzbl r8.ub[123] r32.ud[0] => 1.ud[123]
+movzbl m8.ub[246] r32.ud[0] => 1.ud[246]
+movzwl r16.uw[12345] r32.ud[0] => 1.ud[12345]
+movzwl m16.uw[49380] r32.ud[0] => 1.ud[49380]
+mulb al.ub[123] : r8.ub[123] => ax.uw[15129]
+mulb al.ub[123] : m8.ub[123] => ax.uw[15129]
+mulw ax.uw[12345] : r16.uw[12345] => dx.uw[2325] ax.uw[27825]
+mulw ax.uw[12345] : m16.uw[12345] => dx.uw[2325] ax.uw[27825]
+mull eax.ud[12345678] : r32.ud[12345678] => edx.ud[35487] eax.ud[260846532]
+mull eax.ud[12345678] : m32.ud[12345678] => edx.ud[35487] eax.ud[260846532]
+negb r8.sb[123] => 0.sb[-123]
+negb m8.sb[-123] => 0.sb[123]
+negw r16.sw[12345] => 0.sw[-12345]
+negw m16.sw[-12345] => 0.sw[12345]
+negl r32.sd[12345678] => 0.sd[-12345678]
+negl m32.sd[-12345678] => 0.sd[12345678]
+notb r8.ub[0xca] => 0.ub[0x35]
+notb m8.ub[0xca] => 0.ub[0x35]
+notw r16.uw[0xf0ca] => 0.uw[0x0f35]
+notw m16.uw[0xf0ca] => 0.uw[0x0f35]
+notl r32.ud[0xff00f0ca] => 0.ud[0x00ff0f35]
+notl m32.ud[0xff00f0ca] => 0.ud[0x00ff0f35]
+orb imm8[0x34] al.ub[0x56] => 1.ub[0x76]
+orb imm8[0x34] bl.ub[0x56] => 1.ub[0x76]
+orb imm8[0x34] m8.ub[0x56] => 1.ub[0x76]
+orb r8.ub[0x34] r8.ub[0x56] => 1.ub[0x76]
+orb r8.ub[0x34] m8.ub[0x56] => 1.ub[0x76]
+orb m8.ub[0x34] r8.ub[0x56] => 1.ub[0x76]
+orw imm8[0x31] r16.uw[0x1234] => 1.uw[0x1235]
+orw imm16[0x4231] ax.uw[0x1234] => 1.uw[0x5235]
+orw imm16[0x4231] bx.uw[0x1234] => 1.uw[0x5235]
+orw imm16[0x4231] m16.uw[0x1234] => 1.uw[0x5235]
+orw r16.uw[0x4231] r16.uw[0x1234] => 1.uw[0x5235]
+orw r16.uw[0x4231] m16.uw[0x1234] => 1.uw[0x5235]
+orw m16.uw[0x4231] r16.uw[0x1234] => 1.uw[0x5235]
+orl imm8[0x31] r32.ud[0x12345678] => 1.ud[0x12345679]
+orl imm32[0x86427531] eax.ud[0x12345678] => 1.ud[0x96767779]
+orl imm32[0x86427531] ebx.ud[0x12345678] => 1.ud[0x96767779]
+orl imm32[0x86427531] m32.ud[0x12345678] => 1.ud[0x96767779]
+orl r32.ud[0x86427531] r32.ud[0x12345678] => 1.ud[0x96767779]
+orl r32.ud[0x86427531] m32.ud[0x12345678] => 1.ud[0x96767779]
+orl m32.ud[0x86427531] r32.ud[0x12345678] => 1.ud[0x96767779]
+rclb eflags[0x1,0x0] : r8.ub[0xca] => 0.ub[0x94] eflags[0x1,0x1]
+rclb eflags[0x1,0x0] : m8.ub[0xca] => 0.ub[0x94] eflags[0x1,0x1]
+rclb eflags[0x1,0x0] : imm8[2] r8.ub[0xca] => 1.ub[0x29] eflags[0x1,0x1]
+rclb eflags[0x1,0x0] : imm8[2] m8.ub[0xca] => 1.ub[0x29] eflags[0x1,0x1]
+rclb eflags[0x1,0x0] : cl.ub[2] r8.ub[0xca] => 1.ub[0x29] eflags[0x1,0x1]
+rclb eflags[0x1,0x0] : cl.ub[2] m8.ub[0xca] => 1.ub[0x29] eflags[0x1,0x1]
+rclw eflags[0x1,0x0] : r16.uw[0xf0ca] => 0.uw[0xe194] eflags[0x1,0x1]
+rclw eflags[0x1,0x0] : m16.uw[0xf0ca] => 0.uw[0xe194] eflags[0x1,0x1]
+rclw eflags[0x1,0x0] : imm8[4] r16.uw[0xf0ca] => 1.uw[0x0ca7] eflags[0x1,0x1]
+rclw eflags[0x1,0x0] : imm8[4] m16.uw[0xf0ca] => 1.uw[0x0ca7] eflags[0x1,0x1]
+rclw eflags[0x1,0x0] : cl.ub[4] r16.uw[0xf0ca] => 1.uw[0x0ca7] eflags[0x1,0x1]
+rclw eflags[0x1,0x0] : cl.ub[4] m16.uw[0xf0ca] => 1.uw[0x0ca7] eflags[0x1,0x1]
+rcll eflags[0x1,0x0] : r32.ud[0xff00f0ca] => 0.ud[0xfe01e194] eflags[0x1,0x1]
+rcll eflags[0x1,0x0] : m32.ud[0xff00f0ca] => 0.ud[0xfe01e194] eflags[0x1,0x1]
+rcll eflags[0x1,0x0] : imm8[8] r32.ud[0xff00f0ca] => 1.ud[0x00f0ca7f] eflags[0x1,0x1]
+rcll eflags[0x1,0x0] : imm8[8] m32.ud[0xff00f0ca] => 1.ud[0x00f0ca7f] eflags[0x1,0x1]
+rcll eflags[0x1,0x0] : cl.ub[8] r32.ud[0xff00f0ca] => 1.ud[0x00f0ca7f] eflags[0x1,0x1]
+rcll eflags[0x1,0x0] : cl.ub[8] m32.ud[0xff00f0ca] => 1.ud[0x00f0ca7f] eflags[0x1,0x1]
+rcrb eflags[0x1,0x1] : r8.ub[0xca] => 0.ub[0xe5] eflags[0x1,0x0]
+rcrb eflags[0x1,0x1] : m8.ub[0xca] => 0.ub[0xe5] eflags[0x1,0x0]
+rcrb eflags[0x1,0x0] : imm8[2] r8.ub[0xca] => 1.ub[0x32] eflags[0x1,0x1]
+rcrb eflags[0x1,0x0] : imm8[2] m8.ub[0xca] => 1.ub[0x32] eflags[0x1,0x1]
+rcrb eflags[0x1,0x0] : cl.ub[2] r8.ub[0xca] => 1.ub[0x32] eflags[0x1,0x1]
+rcrb eflags[0x1,0x0] : cl.ub[2] m8.ub[0xca] => 1.ub[0x32] eflags[0x1,0x1]
+rcrw eflags[0x1,0x1] : r16.uw[0xf0ca] => 0.uw[0xf865] eflags[0x1,0x0]
+rcrw eflags[0x1,0x1] : m16.uw[0xf0ca] => 0.uw[0xf865] eflags[0x1,0x0]
+rcrw eflags[0x1,0x0] : imm8[4] r16.uw[0xf0ca] => 1.uw[0x4f0c] eflags[0x1,0x1]
+rcrw eflags[0x1,0x0] : imm8[4] m16.uw[0xf0ca] => 1.uw[0x4f0c] eflags[0x1,0x1]
+rcrw eflags[0x1,0x0] : cl.ub[4] r16.uw[0xf0ca] => 1.uw[0x4f0c] eflags[0x1,0x1]
+rcrw eflags[0x1,0x0] : cl.ub[4] m16.uw[0xf0ca] => 1.uw[0x4f0c] eflags[0x1,0x1]
+rcrl eflags[0x1,0x1] : r32.ud[0xff00f0ca] => 0.ud[0xff807865] eflags[0x1,0x0]
+rcrl eflags[0x1,0x1] : m32.ud[0xff00f0ca] => 0.ud[0xff807865] eflags[0x1,0x0]
+rcrl eflags[0x1,0x0] : imm8[8] r32.ud[0xff00f0ca] => 1.ud[0x94ff00f0] eflags[0x1,0x1]
+rcrl eflags[0x1,0x0] : imm8[8] m32.ud[0xff00f0ca] => 1.ud[0x94ff00f0] eflags[0x1,0x1]
+rcrl eflags[0x1,0x0] : cl.ub[8] r32.ud[0xff00f0ca] => 1.ud[0x94ff00f0] eflags[0x1,0x1]
+rcrl eflags[0x1,0x0] : cl.ub[8] m32.ud[0xff00f0ca] => 1.ud[0x94ff00f0] eflags[0x1,0x1]
+rolb r8.ub[0xca] => 0.ub[0x95]
+rolb m8.ub[0xca] => 0.ub[0x95]
+rolb imm8[2] r8.ub[0xca] => 1.ub[0x2b]
+rolb imm8[2] m8.ub[0xca] => 1.ub[0x2b]
+rolb cl.ub[2] r8.ub[0xca] => 1.ub[0x2b]
+rolb cl.ub[2] m8.ub[0xca] => 1.ub[0x2b]
+rolw r16.uw[0xf0ca] => 0.uw[0xe195]
+rolw m16.uw[0xf0ca] => 0.uw[0xe195]
+rolw imm8[4] r16.uw[0xf0ca] => 1.uw[0x0caf]
+rolw imm8[4] m16.uw[0xf0ca] => 1.uw[0x0caf]
+rolw cl.ub[4] r16.uw[0xf0ca] => 1.uw[0x0caf]
+rolw cl.ub[4] m16.uw[0xf0ca] => 1.uw[0x0caf]
+roll r32.ud[0xff00f0ca] => 0.ud[0xfe01e195]
+roll m32.ud[0xff00f0ca] => 0.ud[0xfe01e195]
+roll imm8[8] r32.ud[0xff00f0ca] => 1.ud[0x00f0caff]
+roll imm8[8] m32.ud[0xff00f0ca] => 1.ud[0x00f0caff]
+roll cl.ub[8] r32.ud[0xff00f0ca] => 1.ud[0x00f0caff]
+roll cl.ub[8] m32.ud[0xff00f0ca] => 1.ud[0x00f0caff]
+rorb r8.ub[0xca] => 0.ub[0x65]
+rorb m8.ub[0xca] => 0.ub[0x65]
+rorb imm8[2] r8.ub[0xca] => 1.ub[0xb2]
+rorb imm8[2] m8.ub[0xca] => 1.ub[0xb2]
+rorb cl.ub[2] r8.ub[0xca] => 1.ub[0xb2]
+rorb cl.ub[2] m8.ub[0xca] => 1.ub[0xb2]
+rorw r16.uw[0xf0ca] => 0.uw[0x7865]
+rorw m16.uw[0xf0ca] => 0.uw[0x7865]
+rorw imm8[4] r16.uw[0xf0ca] => 1.uw[0xaf0c]
+rorw imm8[4] m16.uw[0xf0ca] => 1.uw[0xaf0c]
+rorw cl.ub[4] r16.uw[0xf0ca] => 1.uw[0xaf0c]
+rorw cl.ub[4] m16.uw[0xf0ca] => 1.uw[0xaf0c]
+rorl r32.ud[0xff00f0ca] => 0.ud[0x7f807865]
+rorl m32.ud[0xff00f0ca] => 0.ud[0x7f807865]
+rorl imm8[8] r32.ud[0xff00f0ca] => 1.ud[0xcaff00f0]
+rorl imm8[8] m32.ud[0xff00f0ca] => 1.ud[0xcaff00f0]
+rorl cl.ub[8] r32.ud[0xff00f0ca] => 1.ud[0xcaff00f0]
+rorl cl.ub[8] m32.ud[0xff00f0ca] => 1.ud[0xcaff00f0]
+sahf eflags[0xff,0x28] ah.ub[0xfd] : => eflags[0xff,0xd7]
+sahf eflags[0xff,0xfd] ah.ub[0x28] : => eflags[0xff,0x02]
+salb r8.ub[0xca] => 0.ub[0x94]
+salb m8.ub[0xca] => 0.ub[0x94]
+salb imm8[2] r8.ub[0xca] => 1.ub[0x28]
+salb imm8[2] m8.ub[0xca] => 1.ub[0x28]
+salb cl.ub[2] r8.ub[0xca] => 1.ub[0x28]
+salb cl.ub[2] m8.ub[0xca] => 1.ub[0x28]
+salw r16.uw[0xf0ca] => 0.uw[0xe194]
+salw m16.uw[0xf0ca] => 0.uw[0xe194]
+salw imm8[4] r16.uw[0xf0ca] => 1.uw[0x0ca0]
+salw imm8[4] m16.uw[0xf0ca] => 1.uw[0x0ca0]
+salw cl.ub[4] r16.uw[0xf0ca] => 1.uw[0x0ca0]
+salw cl.ub[4] m16.uw[0xf0ca] => 1.uw[0x0ca0]
+sall r32.ud[0xff00f0ca] => 0.ud[0xfe01e194]
+sall m32.ud[0xff00f0ca] => 0.ud[0xfe01e194]
+sall imm8[8] r32.ud[0xff00f0ca] => 1.ud[0x00f0ca00]
+sall imm8[8] m32.ud[0xff00f0ca] => 1.ud[0x00f0ca00]
+sall cl.ub[8] r32.ud[0xff00f0ca] => 1.ud[0x00f0ca00]
+sall cl.ub[8] m32.ud[0xff00f0ca] => 1.ud[0x00f0ca00]
+sarb r8.ub[0xca] => 0.ub[0xe5]
+sarb m8.ub[0xca] => 0.ub[0xe5]
+sarb imm8[2] r8.ub[0xca] => 1.ub[0xf2]
+sarb imm8[2] m8.ub[0xca] => 1.ub[0xf2]
+sarb cl.ub[2] r8.ub[0xca] => 1.ub[0xf2]
+sarb cl.ub[2] m8.ub[0xca] => 1.ub[0xf2]
+sarw r16.uw[0xf0ca] => 0.uw[0xf865]
+sarw m16.uw[0xf0ca] => 0.uw[0xf865]
+sarw imm8[4] r16.uw[0xf0ca] => 1.uw[0xff0c]
+sarw imm8[4] m16.uw[0xf0ca] => 1.uw[0xff0c]
+sarw cl.ub[4] r16.uw[0xf0ca] => 1.uw[0xff0c]
+sarw cl.ub[4] m16.uw[0xf0ca] => 1.uw[0xff0c]
+sarl r32.ud[0xff00f0ca] => 0.ud[0xff807865]
+sarl m32.ud[0xff00f0ca] => 0.ud[0xff807865]
+sarl imm8[8] r32.ud[0xff00f0ca] => 1.ud[0xffff00f0]
+sarl imm8[8] m32.ud[0xff00f0ca] => 1.ud[0xffff00f0]
+sarl cl.ub[8] r32.ud[0xff00f0ca] => 1.ud[0xffff00f0]
+sarl cl.ub[8] m32.ud[0xff00f0ca] => 1.ud[0xffff00f0]
+sbbb eflags[0x1,0x0] : imm8[12] al.ub[34] => 1.ub[22]
+sbbb eflags[0x1,0x1] : imm8[12] al.ub[34] => 1.ub[21]
+sbbb eflags[0x1,0x0] : imm8[12] bl.ub[34] => 1.ub[22]
+sbbb eflags[0x1,0x1] : imm8[12] bl.ub[34] => 1.ub[21]
+sbbb eflags[0x1,0x0] : imm8[12] m8.ub[34] => 1.ub[22]
+sbbb eflags[0x1,0x1] : imm8[12] m8.ub[34] => 1.ub[21]
+sbbb eflags[0x1,0x0] : r8.ub[12] r8.ub[34] => 1.ub[22]
+sbbb eflags[0x1,0x1] : r8.ub[12] r8.ub[34] => 1.ub[21]
+sbbb eflags[0x1,0x0] : r8.ub[12] m8.ub[34] => 1.ub[22]
+sbbb eflags[0x1,0x1] : r8.ub[12] m8.ub[34] => 1.ub[21]
+sbbb eflags[0x1,0x0] : m8.ub[12] r8.ub[34] => 1.ub[22]
+sbbb eflags[0x1,0x1] : m8.ub[12] r8.ub[34] => 1.ub[21]
+sbbw eflags[0x1,0x0] : imm8[12] r16.uw[3456] => 1.uw[3444]
+sbbw eflags[0x1,0x1] : imm8[12] r16.uw[3456] => 1.uw[3443]
+sbbw eflags[0x1,0x0] : imm16[1234] ax.uw[5678] => 1.uw[4444]
+sbbw eflags[0x1,0x1] : imm16[1234] ax.uw[5678] => 1.uw[4443]
+sbbw eflags[0x1,0x0] : imm16[1234] bx.uw[5678] => 1.uw[4444]
+sbbw eflags[0x1,0x1] : imm16[1234] bx.uw[5678] => 1.uw[4443]
+sbbw eflags[0x1,0x0] : imm16[1234] m16.uw[5678] => 1.uw[4444]
+sbbw eflags[0x1,0x1] : imm16[1234] m16.uw[5678] => 1.uw[4443]
+sbbw eflags[0x1,0x0] : r16.uw[1234] r16.uw[5678] => 1.uw[4444]
+sbbw eflags[0x1,0x1] : r16.uw[1234] r16.uw[5678] => 1.uw[4443]
+sbbw eflags[0x1,0x0] : r16.uw[1234] m16.uw[5678] => 1.uw[4444]
+sbbw eflags[0x1,0x1] : r16.uw[1234] m16.uw[5678] => 1.uw[4443]
+sbbw eflags[0x1,0x0] : m16.uw[1234] r16.uw[5678] => 1.uw[4444]
+sbbw eflags[0x1,0x1] : m16.uw[1234] r16.uw[5678] => 1.uw[4443]
+sbbl eflags[0x1,0x0] : imm8[12] r32.ud[87654321] => 1.ud[87654309]
+sbbl eflags[0x1,0x1] : imm8[12] r32.ud[87654321] => 1.ud[87654308]
+sbbl eflags[0x1,0x0] : imm32[12345678] eax.ud[87654321] => 1.ud[75308643]
+sbbl eflags[0x1,0x1] : imm32[12345678] eax.ud[87654321] => 1.ud[75308642]
+sbbl eflags[0x1,0x0] : imm32[12345678] ebx.ud[87654321] => 1.ud[75308643]
+sbbl eflags[0x1,0x1] : imm32[12345678] ebx.ud[87654321] => 1.ud[75308642]
+sbbl eflags[0x1,0x0] : imm32[12345678] m32.ud[87654321] => 1.ud[75308643]
+sbbl eflags[0x1,0x1] : imm32[12345678] m32.ud[87654321] => 1.ud[75308642]
+sbbl eflags[0x1,0x0] : r32.ud[12345678] r32.ud[87654321] => 1.ud[75308643]
+sbbl eflags[0x1,0x1] : r32.ud[12345678] r32.ud[87654321] => 1.ud[75308642]
+sbbl eflags[0x1,0x0] : r32.ud[12345678] m32.ud[87654321] => 1.ud[75308643]
+sbbl eflags[0x1,0x1] : r32.ud[12345678] m32.ud[87654321] => 1.ud[75308642]
+sbbl eflags[0x1,0x0] : m32.ud[12345678] r32.ud[87654321] => 1.ud[75308643]
+sbbl eflags[0x1,0x1] : m32.ud[12345678] r32.ud[87654321] => 1.ud[75308642]
+seta eflags[0x041,0x000] : r8.ub[123] => 0.ub[1]
+seta eflags[0x041,0x001] : r8.ub[123] => 0.ub[0]
+seta eflags[0x041,0x040] : r8.ub[123] => 0.ub[0]
+seta eflags[0x041,0x041] : r8.ub[123] => 0.ub[0]
+seta eflags[0x041,0x000] : m8.ub[123] => 0.ub[1]
+seta eflags[0x041,0x001] : m8.ub[123] => 0.ub[0]
+seta eflags[0x041,0x040] : m8.ub[123] => 0.ub[0]
+seta eflags[0x041,0x041] : m8.ub[123] => 0.ub[0]
+setae eflags[0x001,0x000] : r8.ub[123] => 0.ub[1]
+setae eflags[0x001,0x001] : r8.ub[123] => 0.ub[0]
+setae eflags[0x001,0x000] : m8.ub[123] => 0.ub[1]
+setae eflags[0x001,0x001] : m8.ub[123] => 0.ub[0]
+setb eflags[0x001,0x000] : r8.ub[123] => 0.ub[0]
+setb eflags[0x001,0x001] : r8.ub[123] => 0.ub[1]
+setb eflags[0x001,0x000] : m8.ub[123] => 0.ub[0]
+setb eflags[0x001,0x001] : m8.ub[123] => 0.ub[1]
+setbe eflags[0x041,0x000] : r8.ub[123] => 0.ub[0]
+setbe eflags[0x041,0x001] : r8.ub[123] => 0.ub[1]
+setbe eflags[0x041,0x040] : r8.ub[123] => 0.ub[1]
+setbe eflags[0x041,0x041] : r8.ub[123] => 0.ub[1]
+setbe eflags[0x041,0x000] : m8.ub[123] => 0.ub[0]
+setbe eflags[0x041,0x001] : m8.ub[123] => 0.ub[1]
+setbe eflags[0x041,0x040] : m8.ub[123] => 0.ub[1]
+setbe eflags[0x041,0x041] : m8.ub[123] => 0.ub[1]
+setc eflags[0x001,0x000] : r8.ub[123] => 0.ub[0]
+setc eflags[0x001,0x001] : r8.ub[123] => 0.ub[1]
+setc eflags[0x001,0x000] : m8.ub[123] => 0.ub[0]
+setc eflags[0x001,0x001] : m8.ub[123] => 0.ub[1]
+sete eflags[0x040,0x000] : r8.ub[123] => 0.ub[0]
+sete eflags[0x040,0x040] : r8.ub[123] => 0.ub[1]
+sete eflags[0x040,0x000] : m8.ub[123] => 0.ub[0]
+sete eflags[0x040,0x040] : m8.ub[123] => 0.ub[1]
+setg eflags[0x8c0,0x000] : r8.ub[123] => 0.ub[1]
+setg eflags[0x8c0,0x040] : r8.ub[123] => 0.ub[0]
+setg eflags[0x8c0,0x080] : r8.ub[123] => 0.ub[0]
+setg eflags[0x8c0,0x0c0] : r8.ub[123] => 0.ub[0]
+setg eflags[0x8c0,0x800] : r8.ub[123] => 0.ub[0]
+setg eflags[0x8c0,0x840] : r8.ub[123] => 0.ub[0]
+setg eflags[0x8c0,0x880] : r8.ub[123] => 0.ub[1]
+setg eflags[0x8c0,0x8c0] : r8.ub[123] => 0.ub[0]
+setg eflags[0x8c0,0x000] : m8.ub[123] => 0.ub[1]
+setg eflags[0x8c0,0x040] : m8.ub[123] => 0.ub[0]
+setg eflags[0x8c0,0x080] : m8.ub[123] => 0.ub[0]
+setg eflags[0x8c0,0x0c0] : m8.ub[123] => 0.ub[0]
+setg eflags[0x8c0,0x800] : m8.ub[123] => 0.ub[0]
+setg eflags[0x8c0,0x840] : m8.ub[123] => 0.ub[0]
+setg eflags[0x8c0,0x880] : m8.ub[123] => 0.ub[1]
+setg eflags[0x8c0,0x8c0] : m8.ub[123] => 0.ub[0]
+setge eflags[0x8c0,0x000] : r8.ub[123] => 0.ub[1]
+setge eflags[0x8c0,0x080] : r8.ub[123] => 0.ub[0]
+setge eflags[0x8c0,0x800] : r8.ub[123] => 0.ub[0]
+setge eflags[0x8c0,0x880] : r8.ub[123] => 0.ub[1]
+setge eflags[0x8c0,0x000] : m8.ub[123] => 0.ub[1]
+setge eflags[0x8c0,0x080] : m8.ub[123] => 0.ub[0]
+setge eflags[0x8c0,0x800] : m8.ub[123] => 0.ub[0]
+setge eflags[0x8c0,0x880] : m8.ub[123] => 0.ub[1]
+setl eflags[0x8c0,0x000] : r8.ub[123] => 0.ub[0]
+setl eflags[0x8c0,0x080] : r8.ub[123] => 0.ub[1]
+setl eflags[0x8c0,0x800] : r8.ub[123] => 0.ub[1]
+setl eflags[0x8c0,0x880] : r8.ub[123] => 0.ub[0]
+setl eflags[0x8c0,0x000] : m8.ub[123] => 0.ub[0]
+setl eflags[0x8c0,0x080] : m8.ub[123] => 0.ub[1]
+setl eflags[0x8c0,0x800] : m8.ub[123] => 0.ub[1]
+setl eflags[0x8c0,0x880] : m8.ub[123] => 0.ub[0]
+setle eflags[0x8c0,0x000] : r8.ub[123] => 0.ub[0]
+setle eflags[0x8c0,0x040] : r8.ub[123] => 0.ub[1]
+setle eflags[0x8c0,0x080] : r8.ub[123] => 0.ub[1]
+setle eflags[0x8c0,0x0c0] : r8.ub[123] => 0.ub[1]
+setle eflags[0x8c0,0x800] : r8.ub[123] => 0.ub[1]
+setle eflags[0x8c0,0x840] : r8.ub[123] => 0.ub[1]
+setle eflags[0x8c0,0x880] : r8.ub[123] => 0.ub[0]
+setle eflags[0x8c0,0x8c0] : r8.ub[123] => 0.ub[1]
+setle eflags[0x8c0,0x000] : m8.ub[123] => 0.ub[0]
+setle eflags[0x8c0,0x040] : m8.ub[123] => 0.ub[1]
+setle eflags[0x8c0,0x080] : m8.ub[123] => 0.ub[1]
+setle eflags[0x8c0,0x0c0] : m8.ub[123] => 0.ub[1]
+setle eflags[0x8c0,0x800] : m8.ub[123] => 0.ub[1]
+setle eflags[0x8c0,0x840] : m8.ub[123] => 0.ub[1]
+setle eflags[0x8c0,0x880] : m8.ub[123] => 0.ub[0]
+setle eflags[0x8c0,0x8c0] : m8.ub[123] => 0.ub[1]
+setna eflags[0x041,0x000] : r8.ub[123] => 0.ub[0]
+setna eflags[0x041,0x001] : r8.ub[123] => 0.ub[1]
+setna eflags[0x041,0x040] : r8.ub[123] => 0.ub[1]
+setna eflags[0x041,0x041] : r8.ub[123] => 0.ub[1]
+setna eflags[0x041,0x000] : m8.ub[123] => 0.ub[0]
+setna eflags[0x041,0x001] : m8.ub[123] => 0.ub[1]
+setna eflags[0x041,0x040] : m8.ub[123] => 0.ub[1]
+setna eflags[0x041,0x041] : m8.ub[123] => 0.ub[1]
+setnae eflags[0x001,0x000] : r8.ub[123] => 0.ub[0]
+setnae eflags[0x001,0x001] : r8.ub[123] => 0.ub[1]
+setnae eflags[0x001,0x000] : m8.ub[123] => 0.ub[0]
+setnae eflags[0x001,0x001] : m8.ub[123] => 0.ub[1]
+setnb eflags[0x001,0x000] : r8.ub[123] => 0.ub[1]
+setnb eflags[0x001,0x001] : r8.ub[123] => 0.ub[0]
+setnb eflags[0x001,0x000] : m8.ub[123] => 0.ub[1]
+setnb eflags[0x001,0x001] : m8.ub[123] => 0.ub[0]
+setnbe eflags[0x041,0x000] : r8.ub[123] => 0.ub[1]
+setnbe eflags[0x041,0x001] : r8.ub[123] => 0.ub[0]
+setnbe eflags[0x041,0x040] : r8.ub[123] => 0.ub[0]
+setnbe eflags[0x041,0x041] : r8.ub[123] => 0.ub[0]
+setnbe eflags[0x041,0x000] : m8.ub[123] => 0.ub[1]
+setnbe eflags[0x041,0x001] : m8.ub[123] => 0.ub[0]
+setnbe eflags[0x041,0x040] : m8.ub[123] => 0.ub[0]
+setnbe eflags[0x041,0x041] : m8.ub[123] => 0.ub[0]
+setnc eflags[0x001,0x000] : r8.ub[123] => 0.ub[1]
+setnc eflags[0x001,0x001] : r8.ub[123] => 0.ub[0]
+setnc eflags[0x001,0x000] : m8.ub[123] => 0.ub[1]
+setnc eflags[0x001,0x001] : m8.ub[123] => 0.ub[0]
+setne eflags[0x040,0x000] : r8.ub[123] => 0.ub[1]
+setne eflags[0x040,0x040] : r8.ub[123] => 0.ub[0]
+setne eflags[0x040,0x000] : m8.ub[123] => 0.ub[1]
+setne eflags[0x040,0x040] : m8.ub[123] => 0.ub[0]
+setng eflags[0x8c0,0x000] : r8.ub[123] => 0.ub[0]
+setng eflags[0x8c0,0x040] : r8.ub[123] => 0.ub[1]
+setng eflags[0x8c0,0x080] : r8.ub[123] => 0.ub[1]
+setng eflags[0x8c0,0x0c0] : r8.ub[123] => 0.ub[1]
+setng eflags[0x8c0,0x800] : r8.ub[123] => 0.ub[1]
+setng eflags[0x8c0,0x840] : r8.ub[123] => 0.ub[1]
+setng eflags[0x8c0,0x880] : r8.ub[123] => 0.ub[0]
+setng eflags[0x8c0,0x8c0] : r8.ub[123] => 0.ub[1]
+setng eflags[0x8c0,0x000] : m8.ub[123] => 0.ub[0]
+setng eflags[0x8c0,0x040] : m8.ub[123] => 0.ub[1]
+setng eflags[0x8c0,0x080] : m8.ub[123] => 0.ub[1]
+setng eflags[0x8c0,0x0c0] : m8.ub[123] => 0.ub[1]
+setng eflags[0x8c0,0x800] : m8.ub[123] => 0.ub[1]
+setng eflags[0x8c0,0x840] : m8.ub[123] => 0.ub[1]
+setng eflags[0x8c0,0x880] : m8.ub[123] => 0.ub[0]
+setng eflags[0x8c0,0x8c0] : m8.ub[123] => 0.ub[1]
+setnge eflags[0x8c0,0x000] : r8.ub[123] => 0.ub[0]
+setnge eflags[0x8c0,0x080] : r8.ub[123] => 0.ub[1]
+setnge eflags[0x8c0,0x800] : r8.ub[123] => 0.ub[1]
+setnge eflags[0x8c0,0x880] : r8.ub[123] => 0.ub[0]
+setnge eflags[0x8c0,0x000] : m8.ub[123] => 0.ub[0]
+setnge eflags[0x8c0,0x080] : m8.ub[123] => 0.ub[1]
+setnge eflags[0x8c0,0x800] : m8.ub[123] => 0.ub[1]
+setnge eflags[0x8c0,0x880] : m8.ub[123] => 0.ub[0]
+setnl eflags[0x8c0,0x000] : r8.ub[123] => 0.ub[1]
+setnl eflags[0x8c0,0x080] : r8.ub[123] => 0.ub[0]
+setnl eflags[0x8c0,0x800] : r8.ub[123] => 0.ub[0]
+setnl eflags[0x8c0,0x880] : r8.ub[123] => 0.ub[1]
+setnl eflags[0x8c0,0x000] : m8.ub[123] => 0.ub[1]
+setnl eflags[0x8c0,0x080] : m8.ub[123] => 0.ub[0]
+setnl eflags[0x8c0,0x800] : m8.ub[123] => 0.ub[0]
+setnl eflags[0x8c0,0x880] : m8.ub[123] => 0.ub[1]
+setnle eflags[0x8c0,0x000] : r8.ub[123] => 0.ub[1]
+setnle eflags[0x8c0,0x040] : r8.ub[123] => 0.ub[0]
+setnle eflags[0x8c0,0x080] : r8.ub[123] => 0.ub[0]
+setnle eflags[0x8c0,0x0c0] : r8.ub[123] => 0.ub[0]
+setnle eflags[0x8c0,0x800] : r8.ub[123] => 0.ub[0]
+setnle eflags[0x8c0,0x840] : r8.ub[123] => 0.ub[0]
+setnle eflags[0x8c0,0x880] : r8.ub[123] => 0.ub[1]
+setnle eflags[0x8c0,0x8c0] : r8.ub[123] => 0.ub[0]
+setnle eflags[0x8c0,0x000] : m8.ub[123] => 0.ub[1]
+setnle eflags[0x8c0,0x040] : m8.ub[123] => 0.ub[0]
+setnle eflags[0x8c0,0x080] : m8.ub[123] => 0.ub[0]
+setnle eflags[0x8c0,0x0c0] : m8.ub[123] => 0.ub[0]
+setnle eflags[0x8c0,0x800] : m8.ub[123] => 0.ub[0]
+setnle eflags[0x8c0,0x840] : m8.ub[123] => 0.ub[0]
+setnle eflags[0x8c0,0x880] : m8.ub[123] => 0.ub[1]
+setnle eflags[0x8c0,0x8c0] : m8.ub[123] => 0.ub[0]
+setno eflags[0x800,0x000] : r8.ub[123] => 0.ub[1]
+setno eflags[0x800,0x800] : r8.ub[123] => 0.ub[0]
+setno eflags[0x800,0x000] : m8.ub[123] => 0.ub[1]
+setno eflags[0x800,0x800] : m8.ub[123] => 0.ub[0]
+setnp eflags[0x004,0x000] : r8.ub[123] => 0.ub[1]
+setnp eflags[0x004,0x004] : r8.ub[123] => 0.ub[0]
+setnp eflags[0x004,0x000] : m8.ub[123] => 0.ub[1]
+setnp eflags[0x004,0x004] : m8.ub[123] => 0.ub[0]
+setns eflags[0x080,0x000] : r8.ub[123] => 0.ub[1]
+setns eflags[0x080,0x080] : r8.ub[123] => 0.ub[0]
+setns eflags[0x080,0x000] : m8.ub[123] => 0.ub[1]
+setns eflags[0x080,0x080] : m8.ub[123] => 0.ub[0]
+setnz eflags[0x040,0x000] : r8.ub[123] => 0.ub[1]
+setnz eflags[0x040,0x040] : r8.ub[123] => 0.ub[0]
+setnz eflags[0x040,0x000] : m8.ub[123] => 0.ub[1]
+setnz eflags[0x040,0x040] : m8.ub[123] => 0.ub[0]
+seto eflags[0x800,0x000] : r8.ub[123] => 0.ub[0]
+seto eflags[0x800,0x800] : r8.ub[123] => 0.ub[1]
+seto eflags[0x800,0x000] : m8.ub[123] => 0.ub[0]
+seto eflags[0x800,0x800] : m8.ub[123] => 0.ub[1]
+setp eflags[0x004,0x000] : r8.ub[123] => 0.ub[0]
+setp eflags[0x004,0x004] : r8.ub[123] => 0.ub[1]
+setp eflags[0x004,0x000] : m8.ub[123] => 0.ub[0]
+setp eflags[0x004,0x004] : m8.ub[123] => 0.ub[1]
+sets eflags[0x080,0x000] : r8.ub[123] => 0.ub[0]
+sets eflags[0x080,0x080] : r8.ub[123] => 0.ub[1]
+sets eflags[0x080,0x000] : m8.ub[123] => 0.ub[0]
+sets eflags[0x080,0x080] : m8.ub[123] => 0.ub[1]
+setz eflags[0x040,0x000] : r8.ub[123] => 0.ub[0]
+setz eflags[0x040,0x040] : r8.ub[123] => 0.ub[1]
+setz eflags[0x040,0x000] : m8.ub[123] => 0.ub[0]
+setz eflags[0x040,0x040] : m8.ub[123] => 0.ub[1]
+shlb r8.ub[0xca] => 0.ub[0x94]
+shlb m8.ub[0xca] => 0.ub[0x94]
+shlb imm8[2] r8.ub[0xca] => 1.ub[0x28]
+shlb imm8[2] m8.ub[0xca] => 1.ub[0x28]
+shlb cl.ub[2] r8.ub[0xca] => 1.ub[0x28]
+shlb cl.ub[2] m8.ub[0xca] => 1.ub[0x28]
+shlw r16.uw[0xf0ca] => 0.uw[0xe194]
+shlw m16.uw[0xf0ca] => 0.uw[0xe194]
+shlw imm8[4] r16.uw[0xf0ca] => 1.uw[0x0ca0]
+shlw imm8[4] m16.uw[0xf0ca] => 1.uw[0x0ca0]
+shlw cl.ub[4] r16.uw[0xf0ca] => 1.uw[0x0ca0]
+shlw cl.ub[4] m16.uw[0xf0ca] => 1.uw[0x0ca0]
+shll r32.ud[0xff00f0ca] => 0.ud[0xfe01e194]
+shll m32.ud[0xff00f0ca] => 0.ud[0xfe01e194]
+shll imm8[8] r32.ud[0xff00f0ca] => 1.ud[0x00f0ca00]
+shll imm8[8] m32.ud[0xff00f0ca] => 1.ud[0x00f0ca00]
+shll cl.ub[8] r32.ud[0xff00f0ca] => 1.ud[0x00f0ca00]
+shll cl.ub[8] m32.ud[0xff00f0ca] => 1.ud[0x00f0ca00]
+shrb r8.ub[0xca] => 0.ub[0x65]
+shrb m8.ub[0xca] => 0.ub[0x65]
+shrb imm8[2] r8.ub[0xca] => 1.ub[0x32]
+shrb imm8[2] m8.ub[0xca] => 1.ub[0x32]
+shrb cl.ub[2] r8.ub[0xca] => 1.ub[0x32]
+shrb cl.ub[2] m8.ub[0xca] => 1.ub[0x32]
+shrw r16.uw[0xf0ca] => 0.uw[0x7865]
+shrw m16.uw[0xf0ca] => 0.uw[0x7865]
+shrw imm8[4] r16.uw[0xf0ca] => 1.uw[0x0f0c]
+shrw imm8[4] m16.uw[0xf0ca] => 1.uw[0x0f0c]
+shrw cl.ub[4] r16.uw[0xf0ca] => 1.uw[0x0f0c]
+shrw cl.ub[4] m16.uw[0xf0ca] => 1.uw[0x0f0c]
+shrl r32.ud[0xff00f0ca] => 0.ud[0x7f807865]
+shrl m32.ud[0xff00f0ca] => 0.ud[0x7f807865]
+shrl imm8[8] r32.ud[0xff00f0ca] => 1.ud[0x00ff00f0]
+shrl imm8[8] m32.ud[0xff00f0ca] => 1.ud[0x00ff00f0]
+shrl cl.ub[8] r32.ud[0xff00f0ca] => 1.ud[0x00ff00f0]
+shrl cl.ub[8] m32.ud[0xff00f0ca] => 1.ud[0x00ff00f0]
+shldw imm8[1] r16.uw[0xf0ca] r16.uw[0xf0ca] => 2.uw[0xe195]
+shldw imm8[1] r16.uw[0xf0ca] m16.uw[0xf0ca] => 2.uw[0xe195]
+shldw imm8[4] r16.uw[0xf0ca] r16.uw[0xf0ca] => 2.uw[0x0caf]
+shldw imm8[4] r16.uw[0xf0ca] m16.uw[0xf0ca] => 2.uw[0x0caf]
+shldw cl.ub[1] r16.uw[0xf0ca] r16.uw[0xf0ca] => 2.uw[0xe195]
+shldw cl.ub[1] r16.uw[0xf0ca] m16.uw[0xf0ca] => 2.uw[0xe195]
+shldw cl.ub[4] r16.uw[0xf0ca] r16.uw[0xf0ca] => 2.uw[0x0caf]
+shldw cl.ub[4] r16.uw[0xf0ca] m16.uw[0xf0ca] => 2.uw[0x0caf]
+shldl imm8[1] r32.ud[0xff00f0ca] r32.ud[0xff00f0ca] => 2.ud[0xfe01e195]
+shldl imm8[1] r32.ud[0xff00f0ca] m32.ud[0xff00f0ca] => 2.ud[0xfe01e195]
+shldl imm8[8] r32.ud[0xff00f0ca] r32.ud[0xff00f0ca] => 2.ud[0x00f0caff]
+shldl imm8[8] r32.ud[0xff00f0ca] m32.ud[0xff00f0ca] => 2.ud[0x00f0caff]
+shldl cl.ub[1] r32.ud[0xff00f0ca] r32.ud[0xff00f0ca] => 2.ud[0xfe01e195]
+shldl cl.ub[1] r32.ud[0xff00f0ca] m32.ud[0xff00f0ca] => 2.ud[0xfe01e195]
+shldl cl.ub[8] r32.ud[0xff00f0ca] r32.ud[0xff00f0ca] => 2.ud[0x00f0caff]
+shldl cl.ub[8] r32.ud[0xff00f0ca] m32.ud[0xff00f0ca] => 2.ud[0x00f0caff]
+shrdw imm8[1] r16.uw[0xf0ca] r16.uw[0xf0ca] => 2.uw[0x7865]
+shrdw imm8[1] r16.uw[0xf0ca] m16.uw[0xf0ca] => 2.uw[0x7865]
+shrdw imm8[4] r16.uw[0xf0ca] r16.uw[0xf0ca] => 2.uw[0xaf0c]
+shrdw imm8[4] r16.uw[0xf0ca] m16.uw[0xf0ca] => 2.uw[0xaf0c]
+shrdw cl.ub[1] r16.uw[0xf0ca] r16.uw[0xf0ca] => 2.uw[0x7865]
+shrdw cl.ub[1] r16.uw[0xf0ca] m16.uw[0xf0ca] => 2.uw[0x7865]
+shrdw cl.ub[4] r16.uw[0xf0ca] r16.uw[0xf0ca] => 2.uw[0xaf0c]
+shrdw cl.ub[4] r16.uw[0xf0ca] m16.uw[0xf0ca] => 2.uw[0xaf0c]
+shrdl imm8[1] r32.ud[0xff00f0ca] r32.ud[0xff00f0ca] => 2.ud[0x7f807865]
+shrdl imm8[1] r32.ud[0xff00f0ca] m32.ud[0xff00f0ca] => 2.ud[0x7f807865]
+shrdl imm8[8] r32.ud[0xff00f0ca] r32.ud[0xff00f0ca] => 2.ud[0xcaff00f0]
+shrdl imm8[8] r32.ud[0xff00f0ca] m32.ud[0xff00f0ca] => 2.ud[0xcaff00f0]
+shrdl cl.ub[1] r32.ud[0xff00f0ca] r32.ud[0xff00f0ca] => 2.ud[0x7f807865]
+shrdl cl.ub[1] r32.ud[0xff00f0ca] m32.ud[0xff00f0ca] => 2.ud[0x7f807865]
+shrdl cl.ub[8] r32.ud[0xff00f0ca] r32.ud[0xff00f0ca] => 2.ud[0xcaff00f0]
+shrdl cl.ub[8] r32.ud[0xff00f0ca] m32.ud[0xff00f0ca] => 2.ud[0xcaff00f0]
+stc eflags[0x001,0x000] : => eflags[0x001,0x001]
+stc eflags[0x001,0x001] : => eflags[0x001,0x001]
+std eflags[0x400,0x000] : => eflags[0x400,0x400]
+std eflags[0x400,0x400] : => eflags[0x400,0x400]
+subb imm8[12] al.ub[34] => 1.ub[22]
+subb imm8[12] bl.ub[34] => 1.ub[22]
+subb imm8[12] m8.ub[34] => 1.ub[22]
+subb r8.ub[12] r8.ub[34] => 1.ub[22]
+subb r8.ub[12] m8.ub[34] => 1.ub[22]
+subb m8.ub[12] r8.ub[34] => 1.ub[22]
+subw imm8[12] r16.uw[3456] => 1.uw[3444]
+subw imm16[1234] ax.uw[5678] => 1.uw[4444]
+subw imm16[1234] bx.uw[5678] => 1.uw[4444]
+subw imm16[1234] m16.uw[5678] => 1.uw[4444]
+subw r16.uw[1234] r16.uw[5678] => 1.uw[4444]
+subw r16.uw[1234] m16.uw[5678] => 1.uw[4444]
+subw m16.uw[1234] r16.uw[5678] => 1.uw[4444]
+subl imm8[12] r32.ud[87654321] => 1.ud[87654309]
+subl imm32[12345678] r32.ud[87654321] => 1.ud[75308643]
+subl imm32[12345678] eax.ud[87654321] => 1.ud[75308643]
+subl imm32[12345678] ebx.ud[87654321] => 1.ud[75308643]
+subl r32.ud[12345678] r32.ud[87654321] => 1.ud[75308643]
+subl r32.ud[12345678] m32.ud[87654321] => 1.ud[75308643]
+subl m32.ud[12345678] r32.ud[87654321] => 1.ud[75308643]
+testb imm8[0x1a] al.ub[0x1a] => eflags[0x8c5,0x000]
+testb imm8[0x5a] al.ub[0x5a] => eflags[0x8c5,0x004]
+testb imm8[0x1a] al.ub[0xa1] => eflags[0x8c5,0x044]
+testb imm8[0xa1] al.ub[0xa1] => eflags[0x8c5,0x080]
+testb imm8[0xa5] al.ub[0xa5] => eflags[0x8c5,0x084]
+testb imm8[0x1a] bl.ub[0x1a] => eflags[0x8c5,0x000]
+testb imm8[0x5a] bl.ub[0x5a] => eflags[0x8c5,0x004]
+testb imm8[0x1a] bl.ub[0xa1] => eflags[0x8c5,0x044]
+testb imm8[0xa1] bl.ub[0xa1] => eflags[0x8c5,0x080]
+testb imm8[0xa5] bl.ub[0xa5] => eflags[0x8c5,0x084]
+testb imm8[0x1a] m8.ub[0x1a] => eflags[0x8c5,0x000]
+testb imm8[0x5a] m8.ub[0x5a] => eflags[0x8c5,0x004]
+testb imm8[0x1a] m8.ub[0xa1] => eflags[0x8c5,0x044]
+testb imm8[0xa1] m8.ub[0xa1] => eflags[0x8c5,0x080]
+testb imm8[0xa5] m8.ub[0xa5] => eflags[0x8c5,0x084]
+testb r8.ub[0x1a] r8.ub[0x1a] => eflags[0x8c5,0x000]
+testb r8.ub[0x5a] r8.ub[0x5a] => eflags[0x8c5,0x004]
+testb r8.ub[0x1a] r8.ub[0xa1] => eflags[0x8c5,0x044]
+testb r8.ub[0xa1] r8.ub[0xa1] => eflags[0x8c5,0x080]
+testb r8.ub[0xa5] r8.ub[0xa5] => eflags[0x8c5,0x084]
+testb r8.ub[0x1a] m8.ub[0x1a] => eflags[0x8c5,0x000]
+testb r8.ub[0x5a] m8.ub[0x5a] => eflags[0x8c5,0x004]
+testb r8.ub[0x1a] m8.ub[0xa1] => eflags[0x8c5,0x044]
+testb r8.ub[0xa1] m8.ub[0xa1] => eflags[0x8c5,0x080]
+testb r8.ub[0xa5] m8.ub[0xa5] => eflags[0x8c5,0x084]
+testw imm16[0x1a1a] ax.uw[0x1a1a] => eflags[0x8c5,0x000]
+testw imm16[0x5a5a] ax.uw[0x5a5a] => eflags[0x8c5,0x004]
+testw imm16[0x1a1a] ax.uw[0xa1a1] => eflags[0x8c5,0x044]
+testw imm16[0xa1a1] ax.uw[0xa1a1] => eflags[0x8c5,0x080]
+testw imm16[0xa5a5] ax.uw[0xa5a5] => eflags[0x8c5,0x084]
+testw imm16[0x1a1a] bx.uw[0x1a1a] => eflags[0x8c5,0x000]
+testw imm16[0x5a5a] bx.uw[0x5a5a] => eflags[0x8c5,0x004]
+testw imm16[0x1a1a] bx.uw[0xa1a1] => eflags[0x8c5,0x044]
+testw imm16[0xa1a1] bx.uw[0xa1a1] => eflags[0x8c5,0x080]
+testw imm16[0xa5a5] bx.uw[0xa5a5] => eflags[0x8c5,0x084]
+testw imm16[0x1a1a] m16.uw[0x1a1a] => eflags[0x8c5,0x000]
+testw imm16[0x5a5a] m16.uw[0x5a5a] => eflags[0x8c5,0x004]
+testw imm16[0x1a1a] m16.uw[0xa1a1] => eflags[0x8c5,0x044]
+testw imm16[0xa1a1] m16.uw[0xa1a1] => eflags[0x8c5,0x080]
+testw imm16[0xa5a5] m16.uw[0xa5a5] => eflags[0x8c5,0x084]
+testw r16.uw[0x1a1a] r16.uw[0x1a1a] => eflags[0x8c5,0x000]
+testw r16.uw[0x5a5a] r16.uw[0x5a5a] => eflags[0x8c5,0x004]
+testw r16.uw[0x1a1a] r16.uw[0xa1a1] => eflags[0x8c5,0x044]
+testw r16.uw[0xa1a1] r16.uw[0xa1a1] => eflags[0x8c5,0x080]
+testw r16.uw[0xa5a5] r16.uw[0xa5a5] => eflags[0x8c5,0x084]
+testw r16.uw[0x1a1a] m16.uw[0x1a1a] => eflags[0x8c5,0x000]
+testw r16.uw[0x5a5a] m16.uw[0x5a5a] => eflags[0x8c5,0x004]
+testw r16.uw[0x1a1a] m16.uw[0xa1a1] => eflags[0x8c5,0x044]
+testw r16.uw[0xa1a1] m16.uw[0xa1a1] => eflags[0x8c5,0x080]
+testw r16.uw[0xa5a5] m16.uw[0xa5a5] => eflags[0x8c5,0x084]
+testl imm32[0x1a1a1a1a] eax.ud[0x1a1a1a1a] => eflags[0x8c5,0x000]
+testl imm32[0x5a5a5a5a] eax.ud[0x5a5a5a5a] => eflags[0x8c5,0x004]
+testl imm32[0x1a1a1a1a] eax.ud[0xa1a1a1a1] => eflags[0x8c5,0x044]
+testl imm32[0xa1a1a1a1] eax.ud[0xa1a1a1a1] => eflags[0x8c5,0x080]
+testl imm32[0xa5a5a5a5] eax.ud[0xa5a5a5a5] => eflags[0x8c5,0x084]
+testl imm32[0x1a1a1a1a] ebx.ud[0x1a1a1a1a] => eflags[0x8c5,0x000]
+testl imm32[0x5a5a5a5a] ebx.ud[0x5a5a5a5a] => eflags[0x8c5,0x004]
+testl imm32[0x1a1a1a1a] ebx.ud[0xa1a1a1a1] => eflags[0x8c5,0x044]
+testl imm32[0xa1a1a1a1] ebx.ud[0xa1a1a1a1] => eflags[0x8c5,0x080]
+testl imm32[0xa5a5a5a5] ebx.ud[0xa5a5a5a5] => eflags[0x8c5,0x084]
+testl imm32[0x1a1a1a1a] m32.ud[0x1a1a1a1a] => eflags[0x8c5,0x000]
+testl imm32[0x5a5a5a5a] m32.ud[0x5a5a5a5a] => eflags[0x8c5,0x004]
+testl imm32[0x1a1a1a1a] m32.ud[0xa1a1a1a1] => eflags[0x8c5,0x044]
+testl imm32[0xa1a1a1a1] m32.ud[0xa1a1a1a1] => eflags[0x8c5,0x080]
+testl imm32[0xa5a5a5a5] m32.ud[0xa5a5a5a5] => eflags[0x8c5,0x084]
+testl r32.ud[0x1a1a1a1a] r32.ud[0x1a1a1a1a] => eflags[0x8c5,0x000]
+testl r32.ud[0x5a5a5a5a] r32.ud[0x5a5a5a5a] => eflags[0x8c5,0x004]
+testl r32.ud[0x1a1a1a1a] r32.ud[0xa1a1a1a1] => eflags[0x8c5,0x044]
+testl r32.ud[0xa1a1a1a1] r32.ud[0xa1a1a1a1] => eflags[0x8c5,0x080]
+testl r32.ud[0xa5a5a5a5] r32.ud[0xa5a5a5a5] => eflags[0x8c5,0x084]
+testl r32.ud[0x1a1a1a1a] m32.ud[0x1a1a1a1a] => eflags[0x8c5,0x000]
+testl r32.ud[0x5a5a5a5a] m32.ud[0x5a5a5a5a] => eflags[0x8c5,0x004]
+testl r32.ud[0x1a1a1a1a] m32.ud[0xa1a1a1a1] => eflags[0x8c5,0x044]
+testl r32.ud[0xa1a1a1a1] m32.ud[0xa1a1a1a1] => eflags[0x8c5,0x080]
+testl r32.ud[0xa5a5a5a5] m32.ud[0xa5a5a5a5] => eflags[0x8c5,0x084]
+xaddb r8.ub[12] r8.ub[34] => 0.ub[34] 1.ub[46]
+xaddb r8.ub[12] m8.ub[34] => 0.ub[34] 1.ub[46]
+xaddw r16.uw[1234] r16.uw[5678] => 0.uw[5678] 1.uw[6912]
+xaddw r16.uw[1234] m16.uw[5678] => 0.uw[5678] 1.uw[6912]
+xaddl r32.ud[12345678] r32.ud[87654321] => 0.ud[87654321] 1.ud[99999999]
+xaddl r32.ud[12345678] m32.ud[87654321] => 0.ud[87654321] 1.ud[99999999]
+xchgb r8.ub[12] r8.ub[34] => 0.ub[34] 1.ub[12]
+xchgb r8.ub[12] m8.ub[34] => 0.ub[34] 1.ub[12]
+xchgb m8.ub[12] r8.ub[34] => 0.ub[34] 1.ub[12]
+xchgw ax.uw[1234] bx.uw[5678] => 0.uw[5678] 1.uw[1234]
+xchgw bx.uw[1234] ax.uw[5678] => 0.uw[5678] 1.uw[1234]
+xchgw ax.uw[1234] cx.uw[5678] => 0.uw[5678] 1.uw[1234]
+xchgw r16.uw[1234] m16.uw[5678] => 0.uw[5678] 1.uw[1234]
+xchgw m16.uw[1234] r16.uw[5678] => 0.uw[5678] 1.uw[1234]
+xchgl eax.ud[12345678] ebx.ud[87654321] => 0.ud[87654321] 1.ud[12345678]
+xchgl ebx.ud[12345678] eax.ud[87654321] => 0.ud[87654321] 1.ud[12345678]
+xchgl ebx.ud[12345678] ecx.ud[87654321] => 0.ud[87654321] 1.ud[12345678]
+xchgl r32.ud[12345678] m32.ud[87654321] => 0.ud[87654321] 1.ud[12345678]
+xchgl m32.ud[12345678] r32.ud[87654321] => 0.ud[87654321] 1.ud[12345678]
+xorb imm8[0x34] al.ub[0x56] => 1.ub[0x62]
+xorb imm8[0x34] bl.ub[0x56] => 1.ub[0x62]
+xorb imm8[0x34] m8.ub[0x56] => 1.ub[0x62]
+xorb r8.ub[0x34] r8.ub[0x56] => 1.ub[0x62]
+xorb r8.ub[0x34] m8.ub[0x56] => 1.ub[0x62]
+xorb m8.ub[0x34] r8.ub[0x56] => 1.ub[0x62]
+xorw imm8[0x31] r16.uw[0x1234] => 1.uw[0x1205]
+xorw imm16[0x4231] ax.uw[0x1234] => 1.uw[0x5005]
+xorw imm16[0x4231] bx.uw[0x1234] => 1.uw[0x5005]
+xorw imm16[0x4231] m16.uw[0x1234] => 1.uw[0x5005]
+xorw r16.uw[0x4231] r16.uw[0x1234] => 1.uw[0x5005]
+xorw r16.uw[0x4231] m16.uw[0x1234] => 1.uw[0x5005]
+xorw m16.uw[0x4231] r16.uw[0x1234] => 1.uw[0x5005]
+xorl imm8[0x31] r32.ud[0x12345678] => 1.ud[0x12345649]
+xorl imm32[0x86427531] eax.ud[0x12345678] => 1.ud[0x94762349]
+xorl imm32[0x86427531] ebx.ud[0x12345678] => 1.ud[0x94762349]
+xorl imm32[0x86427531] m32.ud[0x12345678] => 1.ud[0x94762349]
+xorl r32.ud[0x86427531] r32.ud[0x12345678] => 1.ud[0x94762349]
+xorl r32.ud[0x86427531] m32.ud[0x12345678] => 1.ud[0x94762349]
+xorl m32.ud[0x86427531] r32.ud[0x12345678] => 1.ud[0x94762349]
diff --git a/none/tests/insn_basic.stderr.exp b/none/tests/insn_basic.stderr.exp
new file mode 100644
index 0000000..139597f
--- /dev/null
+++ b/none/tests/insn_basic.stderr.exp
@@ -0,0 +1,2 @@
+
+
diff --git a/none/tests/insn_basic.stdout.exp b/none/tests/insn_basic.stdout.exp
new file mode 100644
index 0000000..40cabbc
--- /dev/null
+++ b/none/tests/insn_basic.stdout.exp
@@ -0,0 +1,1083 @@
+aaa_1 ... ok
+aaa_2 ... ok
+aaa_3 ... ok
+aaa_4 ... ok
+aaa_5 ... ok
+aaa_6 ... ok
+aaa_7 ... ok
+aaa_8 ... ok
+aad_1 ... ok
+aad_2 ... ok
+aam_1 ... ok
+aam_2 ... ok
+aas_1 ... ok
+aas_2 ... ok
+aas_3 ... ok
+aas_4 ... ok
+aas_5 ... ok
+aas_6 ... ok
+aas_7 ... ok
+aas_8 ... ok
+adcb_1 ... ok
+adcb_2 ... ok
+adcb_3 ... ok
+adcb_4 ... ok
+adcb_5 ... ok
+adcb_6 ... ok
+adcb_7 ... ok
+adcb_8 ... ok
+adcb_9 ... ok
+adcb_10 ... ok
+adcb_11 ... ok
+adcb_12 ... ok
+adcw_1 ... ok
+adcw_2 ... ok
+adcw_3 ... ok
+adcw_4 ... ok
+adcw_5 ... ok
+adcw_6 ... ok
+adcw_7 ... ok
+adcw_8 ... ok
+adcw_9 ... ok
+adcw_10 ... ok
+adcw_11 ... ok
+adcw_12 ... ok
+adcw_13 ... ok
+adcw_14 ... ok
+adcl_1 ... ok
+adcl_2 ... ok
+adcl_3 ... ok
+adcl_4 ... ok
+adcl_5 ... ok
+adcl_6 ... ok
+adcl_7 ... ok
+adcl_8 ... ok
+adcl_9 ... ok
+adcl_10 ... ok
+adcl_11 ... ok
+adcl_12 ... ok
+adcl_13 ... ok
+adcl_14 ... ok
+addb_1 ... ok
+addb_2 ... ok
+addb_3 ... ok
+addb_4 ... ok
+addb_5 ... ok
+addb_6 ... ok
+addw_1 ... ok
+addw_2 ... ok
+addw_3 ... ok
+addw_4 ... ok
+addw_5 ... ok
+addw_6 ... ok
+addw_7 ... ok
+addl_1 ... ok
+addl_2 ... ok
+addl_3 ... ok
+addl_4 ... ok
+addl_5 ... ok
+addl_6 ... ok
+addl_7 ... ok
+andb_1 ... ok
+andb_2 ... ok
+andb_3 ... ok
+andb_4 ... ok
+andb_5 ... ok
+andb_6 ... ok
+andw_1 ... ok
+andw_2 ... ok
+andw_3 ... ok
+andw_4 ... ok
+andw_5 ... ok
+andw_6 ... ok
+andw_7 ... ok
+andl_1 ... ok
+andl_2 ... ok
+andl_3 ... ok
+andl_4 ... ok
+andl_5 ... ok
+andl_6 ... ok
+andl_7 ... ok
+bsfw_1 ... ok
+bsfw_2 ... ok
+bsfl_1 ... ok
+bsfl_2 ... ok
+bsrw_1 ... ok
+bsrw_2 ... ok
+bsrl_1 ... ok
+bsrl_2 ... ok
+bswapl_1 ... ok
+btw_1 ... ok
+btw_2 ... ok
+btw_3 ... ok
+btw_4 ... ok
+btw_5 ... ok
+btw_6 ... ok
+btw_7 ... ok
+btw_8 ... ok
+btl_1 ... ok
+btl_2 ... ok
+btl_3 ... ok
+btl_4 ... ok
+btl_5 ... ok
+btl_6 ... ok
+btl_7 ... ok
+btl_8 ... ok
+btcw_1 ... ok
+btcw_2 ... ok
+btcw_3 ... ok
+btcw_4 ... ok
+btcw_5 ... ok
+btcw_6 ... ok
+btcw_7 ... ok
+btcw_8 ... ok
+btcl_1 ... ok
+btcl_2 ... ok
+btcl_3 ... ok
+btcl_4 ... ok
+btcl_5 ... ok
+btcl_6 ... ok
+btcl_7 ... ok
+btcl_8 ... ok
+btrw_1 ... ok
+btrw_2 ... ok
+btrw_3 ... ok
+btrw_4 ... ok
+btrw_5 ... ok
+btrw_6 ... ok
+btrw_7 ... ok
+btrw_8 ... ok
+btrl_1 ... ok
+btrl_2 ... ok
+btrl_3 ... ok
+btrl_4 ... ok
+btrl_5 ... ok
+btrl_6 ... ok
+btrl_7 ... ok
+btrl_8 ... ok
+btsw_1 ... ok
+btsw_2 ... ok
+btsw_3 ... ok
+btsw_4 ... ok
+btsw_5 ... ok
+btsw_6 ... ok
+btsw_7 ... ok
+btsw_8 ... ok
+btsl_1 ... ok
+btsl_2 ... ok
+btsl_3 ... ok
+btsl_4 ... ok
+btsl_5 ... ok
+btsl_6 ... ok
+btsl_7 ... ok
+btsl_8 ... ok
+cbw_1 ... ok
+cbw_2 ... ok
+cdq_1 ... ok
+cdq_2 ... ok
+clc_1 ... ok
+clc_2 ... ok
+cld_1 ... ok
+cld_2 ... ok
+cmc_1 ... ok
+cmc_2 ... ok
+cmpb_1 ... ok
+cmpb_2 ... ok
+cmpb_3 ... ok
+cmpb_4 ... ok
+cmpb_5 ... ok
+cmpb_6 ... ok
+cmpb_7 ... ok
+cmpb_8 ... ok
+cmpb_9 ... ok
+cmpb_10 ... ok
+cmpb_11 ... ok
+cmpb_12 ... ok
+cmpb_13 ... ok
+cmpb_14 ... ok
+cmpb_15 ... ok
+cmpb_16 ... ok
+cmpb_17 ... ok
+cmpb_18 ... ok
+cmpb_19 ... ok
+cmpb_20 ... ok
+cmpb_21 ... ok
+cmpb_22 ... ok
+cmpb_23 ... ok
+cmpb_24 ... ok
+cmpb_25 ... ok
+cmpb_26 ... ok
+cmpb_27 ... ok
+cmpb_28 ... ok
+cmpb_29 ... ok
+cmpb_30 ... ok
+cmpb_31 ... ok
+cmpb_32 ... ok
+cmpb_33 ... ok
+cmpb_34 ... ok
+cmpb_35 ... ok
+cmpb_36 ... ok
+cmpb_37 ... ok
+cmpb_38 ... ok
+cmpb_39 ... ok
+cmpb_40 ... ok
+cmpb_41 ... ok
+cmpb_42 ... ok
+cmpb_43 ... ok
+cmpb_44 ... ok
+cmpb_45 ... ok
+cmpb_46 ... ok
+cmpb_47 ... ok
+cmpb_48 ... ok
+cmpb_49 ... ok
+cmpb_50 ... ok
+cmpb_51 ... ok
+cmpb_52 ... ok
+cmpb_53 ... ok
+cmpb_54 ... ok
+cmpb_55 ... ok
+cmpb_56 ... ok
+cmpb_57 ... ok
+cmpb_58 ... ok
+cmpb_59 ... ok
+cmpb_60 ... ok
+cmpw_1 ... ok
+cmpw_2 ... ok
+cmpw_3 ... ok
+cmpw_4 ... ok
+cmpw_5 ... ok
+cmpw_6 ... ok
+cmpw_7 ... ok
+cmpw_8 ... ok
+cmpw_9 ... ok
+cmpw_10 ... ok
+cmpw_11 ... ok
+cmpw_12 ... ok
+cmpw_13 ... ok
+cmpw_14 ... ok
+cmpw_15 ... ok
+cmpw_16 ... ok
+cmpw_17 ... ok
+cmpw_18 ... ok
+cmpw_19 ... ok
+cmpw_20 ... ok
+cmpw_21 ... ok
+cmpw_22 ... ok
+cmpw_23 ... ok
+cmpw_24 ... ok
+cmpw_25 ... ok
+cmpw_26 ... ok
+cmpw_27 ... ok
+cmpw_28 ... ok
+cmpw_29 ... ok
+cmpw_30 ... ok
+cmpw_31 ... ok
+cmpw_32 ... ok
+cmpw_33 ... ok
+cmpw_34 ... ok
+cmpw_35 ... ok
+cmpw_36 ... ok
+cmpw_37 ... ok
+cmpw_38 ... ok
+cmpw_39 ... ok
+cmpw_40 ... ok
+cmpw_41 ... ok
+cmpw_42 ... ok
+cmpw_43 ... ok
+cmpw_44 ... ok
+cmpw_45 ... ok
+cmpw_46 ... ok
+cmpw_47 ... ok
+cmpw_48 ... ok
+cmpw_49 ... ok
+cmpw_50 ... ok
+cmpw_51 ... ok
+cmpw_52 ... ok
+cmpw_53 ... ok
+cmpw_54 ... ok
+cmpw_55 ... ok
+cmpw_56 ... ok
+cmpw_57 ... ok
+cmpw_58 ... ok
+cmpw_59 ... ok
+cmpw_60 ... ok
+cmpw_61 ... ok
+cmpw_62 ... ok
+cmpw_63 ... ok
+cmpw_64 ... ok
+cmpw_65 ... ok
+cmpw_66 ... ok
+cmpw_67 ... ok
+cmpw_68 ... ok
+cmpw_69 ... ok
+cmpw_70 ... ok
+cmpw_71 ... ok
+cmpw_72 ... ok
+cmpw_73 ... ok
+cmpw_74 ... ok
+cmpw_75 ... ok
+cmpw_76 ... ok
+cmpw_77 ... ok
+cmpw_78 ... ok
+cmpw_79 ... ok
+cmpw_80 ... ok
+cmpl_1 ... ok
+cmpl_2 ... ok
+cmpl_3 ... ok
+cmpl_4 ... ok
+cmpl_5 ... ok
+cmpl_6 ... ok
+cmpl_7 ... ok
+cmpl_8 ... ok
+cmpl_9 ... ok
+cmpl_10 ... ok
+cmpl_11 ... ok
+cmpl_12 ... ok
+cmpl_13 ... ok
+cmpl_14 ... ok
+cmpl_15 ... ok
+cmpl_16 ... ok
+cmpl_17 ... ok
+cmpl_18 ... ok
+cmpl_19 ... ok
+cmpl_20 ... ok
+cmpl_21 ... ok
+cmpl_22 ... ok
+cmpl_23 ... ok
+cmpl_24 ... ok
+cmpl_25 ... ok
+cmpl_26 ... ok
+cmpl_27 ... ok
+cmpl_28 ... ok
+cmpl_29 ... ok
+cmpl_30 ... ok
+cmpl_31 ... ok
+cmpl_32 ... ok
+cmpl_33 ... ok
+cmpl_34 ... ok
+cmpl_35 ... ok
+cmpl_36 ... ok
+cmpl_37 ... ok
+cmpl_38 ... ok
+cmpl_39 ... ok
+cmpl_40 ... ok
+cmpl_41 ... ok
+cmpl_42 ... ok
+cmpl_43 ... ok
+cmpl_44 ... ok
+cmpl_45 ... ok
+cmpl_46 ... ok
+cmpl_47 ... ok
+cmpl_48 ... ok
+cmpl_49 ... ok
+cmpl_50 ... ok
+cmpl_51 ... ok
+cmpl_52 ... ok
+cmpl_53 ... ok
+cmpl_54 ... ok
+cmpl_55 ... ok
+cmpl_56 ... ok
+cmpl_57 ... ok
+cmpl_58 ... ok
+cmpl_59 ... ok
+cmpl_60 ... ok
+cmpl_61 ... ok
+cmpl_62 ... ok
+cmpl_63 ... ok
+cmpl_64 ... ok
+cmpl_65 ... ok
+cmpl_66 ... ok
+cmpl_67 ... ok
+cmpl_68 ... ok
+cmpl_69 ... ok
+cmpl_70 ... ok
+cmpl_71 ... ok
+cmpl_72 ... ok
+cmpl_73 ... ok
+cmpl_74 ... ok
+cmpl_75 ... ok
+cmpl_76 ... ok
+cmpl_77 ... ok
+cmpl_78 ... ok
+cmpl_79 ... ok
+cmpl_80 ... ok
+cmpxchgb_1 ... ok
+cmpxchgb_2 ... ok
+cmpxchgb_3 ... ok
+cmpxchgb_4 ... ok
+cmpxchgw_1 ... ok
+cmpxchgw_2 ... ok
+cmpxchgw_3 ... ok
+cmpxchgw_4 ... ok
+cmpxchgl_1 ... ok
+cmpxchgl_2 ... ok
+cmpxchgl_3 ... ok
+cmpxchgl_4 ... ok
+cwd_1 ... ok
+cwd_2 ... ok
+cwde_1 ... ok
+cwde_2 ... ok
+daa_1 ... ok
+daa_2 ... ok
+das_1 ... ok
+decb_1 ... ok
+decb_2 ... ok
+decw_1 ... ok
+decw_2 ... ok
+decl_1 ... ok
+decl_2 ... ok
+divb_1 ... ok
+divb_2 ... ok
+divw_1 ... ok
+divw_2 ... ok
+divl_1 ... ok
+divl_2 ... ok
+idivb_1 ... ok
+idivb_2 ... ok
+idivw_1 ... ok
+idivw_2 ... ok
+idivl_1 ... ok
+idivl_2 ... ok
+imulb_1 ... ok
+imulb_2 ... ok
+imulw_1 ... ok
+imulw_2 ... ok
+imull_1 ... ok
+imull_2 ... ok
+imulw_3 ... ok
+imulw_4 ... ok
+imulw_5 ... ok
+imulw_6 ... ok
+imulw_7 ... ok
+imulw_8 ... ok
+imulw_9 ... ok
+imulw_10 ... ok
+imull_3 ... ok
+imull_4 ... ok
+imull_5 ... ok
+imull_6 ... ok
+imull_7 ... ok
+imull_8 ... ok
+imull_9 ... ok
+imull_10 ... ok
+incb_1 ... ok
+incb_2 ... ok
+incw_1 ... ok
+incw_2 ... ok
+incl_1 ... ok
+incl_2 ... ok
+lahf_1 ... ok
+lahf_2 ... ok
+movb_1 ... ok
+movb_2 ... ok
+movb_3 ... ok
+movb_4 ... ok
+movb_5 ... ok
+movw_1 ... ok
+movw_2 ... ok
+movw_3 ... ok
+movw_4 ... ok
+movw_5 ... ok
+movl_1 ... ok
+movl_2 ... ok
+movl_3 ... ok
+movl_4 ... ok
+movl_5 ... ok
+movsbw_1 ... ok
+movsbw_2 ... ok
+movsbl_1 ... ok
+movsbl_2 ... ok
+movswl_1 ... ok
+movswl_2 ... ok
+movzbw_1 ... ok
+movzbw_2 ... ok
+movzbl_1 ... ok
+movzbl_2 ... ok
+movzwl_1 ... ok
+movzwl_2 ... ok
+mulb_1 ... ok
+mulb_2 ... ok
+mulw_1 ... ok
+mulw_2 ... ok
+mull_1 ... ok
+mull_2 ... ok
+negb_1 ... ok
+negb_2 ... ok
+negw_1 ... ok
+negw_2 ... ok
+negl_1 ... ok
+negl_2 ... ok
+notb_1 ... ok
+notb_2 ... ok
+notw_1 ... ok
+notw_2 ... ok
+notl_1 ... ok
+notl_2 ... ok
+orb_1 ... ok
+orb_2 ... ok
+orb_3 ... ok
+orb_4 ... ok
+orb_5 ... ok
+orb_6 ... ok
+orw_1 ... ok
+orw_2 ... ok
+orw_3 ... ok
+orw_4 ... ok
+orw_5 ... ok
+orw_6 ... ok
+orw_7 ... ok
+orl_1 ... ok
+orl_2 ... ok
+orl_3 ... ok
+orl_4 ... ok
+orl_5 ... ok
+orl_6 ... ok
+orl_7 ... ok
+rclb_1 ... ok
+rclb_2 ... ok
+rclb_3 ... ok
+rclb_4 ... ok
+rclb_5 ... ok
+rclb_6 ... ok
+rclw_1 ... ok
+rclw_2 ... ok
+rclw_3 ... ok
+rclw_4 ... ok
+rclw_5 ... ok
+rclw_6 ... ok
+rcll_1 ... ok
+rcll_2 ... ok
+rcll_3 ... ok
+rcll_4 ... ok
+rcll_5 ... ok
+rcll_6 ... ok
+rcrb_1 ... ok
+rcrb_2 ... ok
+rcrb_3 ... ok
+rcrb_4 ... ok
+rcrb_5 ... ok
+rcrb_6 ... ok
+rcrw_1 ... ok
+rcrw_2 ... ok
+rcrw_3 ... ok
+rcrw_4 ... ok
+rcrw_5 ... ok
+rcrw_6 ... ok
+rcrl_1 ... ok
+rcrl_2 ... ok
+rcrl_3 ... ok
+rcrl_4 ... ok
+rcrl_5 ... ok
+rcrl_6 ... ok
+rolb_1 ... ok
+rolb_2 ... ok
+rolb_3 ... ok
+rolb_4 ... ok
+rolb_5 ... ok
+rolb_6 ... ok
+rolw_1 ... ok
+rolw_2 ... ok
+rolw_3 ... ok
+rolw_4 ... ok
+rolw_5 ... ok
+rolw_6 ... ok
+roll_1 ... ok
+roll_2 ... ok
+roll_3 ... ok
+roll_4 ... ok
+roll_5 ... ok
+roll_6 ... ok
+rorb_1 ... ok
+rorb_2 ... ok
+rorb_3 ... ok
+rorb_4 ... ok
+rorb_5 ... ok
+rorb_6 ... ok
+rorw_1 ... ok
+rorw_2 ... ok
+rorw_3 ... ok
+rorw_4 ... ok
+rorw_5 ... ok
+rorw_6 ... ok
+rorl_1 ... ok
+rorl_2 ... ok
+rorl_3 ... ok
+rorl_4 ... ok
+rorl_5 ... ok
+rorl_6 ... ok
+sahf_1 ... ok
+sahf_2 ... ok
+salb_1 ... ok
+salb_2 ... ok
+salb_3 ... ok
+salb_4 ... ok
+salb_5 ... ok
+salb_6 ... ok
+salw_1 ... ok
+salw_2 ... ok
+salw_3 ... ok
+salw_4 ... ok
+salw_5 ... ok
+salw_6 ... ok
+sall_1 ... ok
+sall_2 ... ok
+sall_3 ... ok
+sall_4 ... ok
+sall_5 ... ok
+sall_6 ... ok
+sarb_1 ... ok
+sarb_2 ... ok
+sarb_3 ... ok
+sarb_4 ... ok
+sarb_5 ... ok
+sarb_6 ... ok
+sarw_1 ... ok
+sarw_2 ... ok
+sarw_3 ... ok
+sarw_4 ... ok
+sarw_5 ... ok
+sarw_6 ... ok
+sarl_1 ... ok
+sarl_2 ... ok
+sarl_3 ... ok
+sarl_4 ... ok
+sarl_5 ... ok
+sarl_6 ... ok
+sbbb_1 ... ok
+sbbb_2 ... ok
+sbbb_3 ... ok
+sbbb_4 ... ok
+sbbb_5 ... ok
+sbbb_6 ... ok
+sbbb_7 ... ok
+sbbb_8 ... ok
+sbbb_9 ... ok
+sbbb_10 ... ok
+sbbb_11 ... ok
+sbbb_12 ... ok
+sbbw_1 ... ok
+sbbw_2 ... ok
+sbbw_3 ... ok
+sbbw_4 ... ok
+sbbw_5 ... ok
+sbbw_6 ... ok
+sbbw_7 ... ok
+sbbw_8 ... ok
+sbbw_9 ... ok
+sbbw_10 ... ok
+sbbw_11 ... ok
+sbbw_12 ... ok
+sbbw_13 ... ok
+sbbw_14 ... ok
+sbbl_1 ... ok
+sbbl_2 ... ok
+sbbl_3 ... ok
+sbbl_4 ... ok
+sbbl_5 ... ok
+sbbl_6 ... ok
+sbbl_7 ... ok
+sbbl_8 ... ok
+sbbl_9 ... ok
+sbbl_10 ... ok
+sbbl_11 ... ok
+sbbl_12 ... ok
+sbbl_13 ... ok
+sbbl_14 ... ok
+seta_1 ... ok
+seta_2 ... ok
+seta_3 ... ok
+seta_4 ... ok
+seta_5 ... ok
+seta_6 ... ok
+seta_7 ... ok
+seta_8 ... ok
+setae_1 ... ok
+setae_2 ... ok
+setae_3 ... ok
+setae_4 ... ok
+setb_1 ... ok
+setb_2 ... ok
+setb_3 ... ok
+setb_4 ... ok
+setbe_1 ... ok
+setbe_2 ... ok
+setbe_3 ... ok
+setbe_4 ... ok
+setbe_5 ... ok
+setbe_6 ... ok
+setbe_7 ... ok
+setbe_8 ... ok
+setc_1 ... ok
+setc_2 ... ok
+setc_3 ... ok
+setc_4 ... ok
+sete_1 ... ok
+sete_2 ... ok
+sete_3 ... ok
+sete_4 ... ok
+setg_1 ... ok
+setg_2 ... ok
+setg_3 ... ok
+setg_4 ... ok
+setg_5 ... ok
+setg_6 ... ok
+setg_7 ... ok
+setg_8 ... ok
+setg_9 ... ok
+setg_10 ... ok
+setg_11 ... ok
+setg_12 ... ok
+setg_13 ... ok
+setg_14 ... ok
+setg_15 ... ok
+setg_16 ... ok
+setge_1 ... ok
+setge_2 ... ok
+setge_3 ... ok
+setge_4 ... ok
+setge_5 ... ok
+setge_6 ... ok
+setge_7 ... ok
+setge_8 ... ok
+setl_1 ... ok
+setl_2 ... ok
+setl_3 ... ok
+setl_4 ... ok
+setl_5 ... ok
+setl_6 ... ok
+setl_7 ... ok
+setl_8 ... ok
+setle_1 ... ok
+setle_2 ... ok
+setle_3 ... ok
+setle_4 ... ok
+setle_5 ... ok
+setle_6 ... ok
+setle_7 ... ok
+setle_8 ... ok
+setle_9 ... ok
+setle_10 ... ok
+setle_11 ... ok
+setle_12 ... ok
+setle_13 ... ok
+setle_14 ... ok
+setle_15 ... ok
+setle_16 ... ok
+setna_1 ... ok
+setna_2 ... ok
+setna_3 ... ok
+setna_4 ... ok
+setna_5 ... ok
+setna_6 ... ok
+setna_7 ... ok
+setna_8 ... ok
+setnae_1 ... ok
+setnae_2 ... ok
+setnae_3 ... ok
+setnae_4 ... ok
+setnb_1 ... ok
+setnb_2 ... ok
+setnb_3 ... ok
+setnb_4 ... ok
+setnbe_1 ... ok
+setnbe_2 ... ok
+setnbe_3 ... ok
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+setnbe_5 ... ok
+setnbe_6 ... ok
+setnbe_7 ... ok
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+setnc_1 ... ok
+setnc_2 ... ok
+setnc_3 ... ok
+setnc_4 ... ok
+setne_1 ... ok
+setne_2 ... ok
+setne_3 ... ok
+setne_4 ... ok
+setng_1 ... ok
+setng_2 ... ok
+setng_3 ... ok
+setng_4 ... ok
+setng_5 ... ok
+setng_6 ... ok
+setng_7 ... ok
+setng_8 ... ok
+setng_9 ... ok
+setng_10 ... ok
+setng_11 ... ok
+setng_12 ... ok
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+setng_14 ... ok
+setng_15 ... ok
+setng_16 ... ok
+setnge_1 ... ok
+setnge_2 ... ok
+setnge_3 ... ok
+setnge_4 ... ok
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+setnge_6 ... ok
+setnge_7 ... ok
+setnge_8 ... ok
+setnl_1 ... ok
+setnl_2 ... ok
+setnl_3 ... ok
+setnl_4 ... ok
+setnl_5 ... ok
+setnl_6 ... ok
+setnl_7 ... ok
+setnl_8 ... ok
+setnle_1 ... ok
+setnle_2 ... ok
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+setnle_4 ... ok
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+setnle_6 ... ok
+setnle_7 ... ok
+setnle_8 ... ok
+setnle_9 ... ok
+setnle_10 ... ok
+setnle_11 ... ok
+setnle_12 ... ok
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+setnle_14 ... ok
+setnle_15 ... ok
+setnle_16 ... ok
+setno_1 ... ok
+setno_2 ... ok
+setno_3 ... ok
+setno_4 ... ok
+setnp_1 ... ok
+setnp_2 ... ok
+setnp_3 ... ok
+setnp_4 ... ok
+setns_1 ... ok
+setns_2 ... ok
+setns_3 ... ok
+setns_4 ... ok
+setnz_1 ... ok
+setnz_2 ... ok
+setnz_3 ... ok
+setnz_4 ... ok
+seto_1 ... ok
+seto_2 ... ok
+seto_3 ... ok
+seto_4 ... ok
+setp_1 ... ok
+setp_2 ... ok
+setp_3 ... ok
+setp_4 ... ok
+sets_1 ... ok
+sets_2 ... ok
+sets_3 ... ok
+sets_4 ... ok
+setz_1 ... ok
+setz_2 ... ok
+setz_3 ... ok
+setz_4 ... ok
+shlb_1 ... ok
+shlb_2 ... ok
+shlb_3 ... ok
+shlb_4 ... ok
+shlb_5 ... ok
+shlb_6 ... ok
+shlw_1 ... ok
+shlw_2 ... ok
+shlw_3 ... ok
+shlw_4 ... ok
+shlw_5 ... ok
+shlw_6 ... ok
+shll_1 ... ok
+shll_2 ... ok
+shll_3 ... ok
+shll_4 ... ok
+shll_5 ... ok
+shll_6 ... ok
+shrb_1 ... ok
+shrb_2 ... ok
+shrb_3 ... ok
+shrb_4 ... ok
+shrb_5 ... ok
+shrb_6 ... ok
+shrw_1 ... ok
+shrw_2 ... ok
+shrw_3 ... ok
+shrw_4 ... ok
+shrw_5 ... ok
+shrw_6 ... ok
+shrl_1 ... ok
+shrl_2 ... ok
+shrl_3 ... ok
+shrl_4 ... ok
+shrl_5 ... ok
+shrl_6 ... ok
+shldw_1 ... ok
+shldw_2 ... ok
+shldw_3 ... ok
+shldw_4 ... ok
+shldw_5 ... ok
+shldw_6 ... ok
+shldw_7 ... ok
+shldw_8 ... ok
+shldl_1 ... ok
+shldl_2 ... ok
+shldl_3 ... ok
+shldl_4 ... ok
+shldl_5 ... ok
+shldl_6 ... ok
+shldl_7 ... ok
+shldl_8 ... ok
+shrdw_1 ... ok
+shrdw_2 ... ok
+shrdw_3 ... ok
+shrdw_4 ... ok
+shrdw_5 ... ok
+shrdw_6 ... ok
+shrdw_7 ... ok
+shrdw_8 ... ok
+shrdl_1 ... ok
+shrdl_2 ... ok
+shrdl_3 ... ok
+shrdl_4 ... ok
+shrdl_5 ... ok
+shrdl_6 ... ok
+shrdl_7 ... ok
+shrdl_8 ... ok
+stc_1 ... ok
+stc_2 ... ok
+std_1 ... ok
+std_2 ... ok
+subb_1 ... ok
+subb_2 ... ok
+subb_3 ... ok
+subb_4 ... ok
+subb_5 ... ok
+subb_6 ... ok
+subw_1 ... ok
+subw_2 ... ok
+subw_3 ... ok
+subw_4 ... ok
+subw_5 ... ok
+subw_6 ... ok
+subw_7 ... ok
+subl_1 ... ok
+subl_2 ... ok
+subl_3 ... ok
+subl_4 ... ok
+subl_5 ... ok
+subl_6 ... ok
+subl_7 ... ok
+testb_1 ... ok
+testb_2 ... ok
+testb_3 ... ok
+testb_4 ... ok
+testb_5 ... ok
+testb_6 ... ok
+testb_7 ... ok
+testb_8 ... ok
+testb_9 ... ok
+testb_10 ... ok
+testb_11 ... ok
+testb_12 ... ok
+testb_13 ... ok
+testb_14 ... ok
+testb_15 ... ok
+testb_16 ... ok
+testb_17 ... ok
+testb_18 ... ok
+testb_19 ... ok
+testb_20 ... ok
+testb_21 ... ok
+testb_22 ... ok
+testb_23 ... ok
+testb_24 ... ok
+testb_25 ... ok
+testw_1 ... ok
+testw_2 ... ok
+testw_3 ... ok
+testw_4 ... ok
+testw_5 ... ok
+testw_6 ... ok
+testw_7 ... ok
+testw_8 ... ok
+testw_9 ... ok
+testw_10 ... ok
+testw_11 ... ok
+testw_12 ... ok
+testw_13 ... ok
+testw_14 ... ok
+testw_15 ... ok
+testw_16 ... ok
+testw_17 ... ok
+testw_18 ... ok
+testw_19 ... ok
+testw_20 ... ok
+testw_21 ... ok
+testw_22 ... ok
+testw_23 ... ok
+testw_24 ... ok
+testw_25 ... ok
+testl_1 ... ok
+testl_2 ... ok
+testl_3 ... ok
+testl_4 ... ok
+testl_5 ... ok
+testl_6 ... ok
+testl_7 ... ok
+testl_8 ... ok
+testl_9 ... ok
+testl_10 ... ok
+testl_11 ... ok
+testl_12 ... ok
+testl_13 ... ok
+testl_14 ... ok
+testl_15 ... ok
+testl_16 ... ok
+testl_17 ... ok
+testl_18 ... ok
+testl_19 ... ok
+testl_20 ... ok
+testl_21 ... ok
+testl_22 ... ok
+testl_23 ... ok
+testl_24 ... ok
+testl_25 ... ok
+xaddb_1 ... ok
+xaddb_2 ... ok
+xaddw_1 ... ok
+xaddw_2 ... ok
+xaddl_1 ... ok
+xaddl_2 ... ok
+xchgb_1 ... ok
+xchgb_2 ... ok
+xchgb_3 ... ok
+xchgw_1 ... ok
+xchgw_2 ... ok
+xchgw_3 ... ok
+xchgw_4 ... ok
+xchgw_5 ... ok
+xchgl_1 ... ok
+xchgl_2 ... ok
+xchgl_3 ... ok
+xchgl_4 ... ok
+xchgl_5 ... ok
+xorb_1 ... ok
+xorb_2 ... ok
+xorb_3 ... ok
+xorb_4 ... ok
+xorb_5 ... ok
+xorb_6 ... ok
+xorw_1 ... ok
+xorw_2 ... ok
+xorw_3 ... ok
+xorw_4 ... ok
+xorw_5 ... ok
+xorw_6 ... ok
+xorw_7 ... ok
+xorl_1 ... ok
+xorl_2 ... ok
+xorl_3 ... ok
+xorl_4 ... ok
+xorl_5 ... ok
+xorl_6 ... ok
+xorl_7 ... ok
diff --git a/none/tests/insn_basic.vgtest b/none/tests/insn_basic.vgtest
new file mode 100644
index 0000000..4210146
--- /dev/null
+++ b/none/tests/insn_basic.vgtest
@@ -0,0 +1 @@
+prog: insn_basic
diff --git a/none/tests/insn_cmov.def b/none/tests/insn_cmov.def
new file mode 100644
index 0000000..40e6b2e
--- /dev/null
+++ b/none/tests/insn_cmov.def
@@ -0,0 +1,384 @@
+cmova eflags[0x041,0x000] : r16.uw[12345] r16.uw[0] => 1.uw[12345]
+cmova eflags[0x041,0x001] : r16.uw[12345] r16.uw[0] => 1.uw[0]
+cmova eflags[0x041,0x040] : r16.uw[12345] r16.uw[0] => 1.uw[0]
+cmova eflags[0x041,0x041] : r16.uw[12345] r16.uw[0] => 1.uw[0]
+cmova eflags[0x041,0x000] : m16.uw[12345] r16.uw[0] => 1.uw[12345]
+cmova eflags[0x041,0x001] : m16.uw[12345] r16.uw[0] => 1.uw[0]
+cmova eflags[0x041,0x040] : m16.uw[12345] r16.uw[0] => 1.uw[0]
+cmova eflags[0x041,0x041] : m16.uw[12345] r16.uw[0] => 1.uw[0]
+cmovae eflags[0x001,0x000] : r16.uw[12345] r16.uw[0] => 1.uw[12345]
+cmovae eflags[0x001,0x001] : r16.uw[12345] r16.uw[0] => 1.uw[0]
+cmovae eflags[0x001,0x000] : m16.uw[12345] r16.uw[0] => 1.uw[12345]
+cmovae eflags[0x001,0x001] : m16.uw[12345] r16.uw[0] => 1.uw[0]
+cmovb eflags[0x001,0x000] : r16.uw[12345] r16.uw[0] => 1.uw[0]
+cmovb eflags[0x001,0x001] : r16.uw[12345] r16.uw[0] => 1.uw[12345]
+cmovb eflags[0x001,0x000] : m16.uw[12345] r16.uw[0] => 1.uw[0]
+cmovb eflags[0x001,0x001] : m16.uw[12345] r16.uw[0] => 1.uw[12345]
+cmovbe eflags[0x041,0x000] : r16.uw[12345] r16.uw[0] => 1.uw[0]
+cmovbe eflags[0x041,0x001] : r16.uw[12345] r16.uw[0] => 1.uw[12345]
+cmovbe eflags[0x041,0x040] : r16.uw[12345] r16.uw[0] => 1.uw[12345]
+cmovbe eflags[0x041,0x041] : r16.uw[12345] r16.uw[0] => 1.uw[12345]
+cmovbe eflags[0x041,0x000] : m16.uw[12345] r16.uw[0] => 1.uw[0]
+cmovbe eflags[0x041,0x001] : m16.uw[12345] r16.uw[0] => 1.uw[12345]
+cmovbe eflags[0x041,0x040] : m16.uw[12345] r16.uw[0] => 1.uw[12345]
+cmovbe eflags[0x041,0x041] : m16.uw[12345] r16.uw[0] => 1.uw[12345]
+cmovc eflags[0x001,0x000] : r16.uw[12345] r16.uw[0] => 1.uw[0]
+cmovc eflags[0x001,0x001] : r16.uw[12345] r16.uw[0] => 1.uw[12345]
+cmovc eflags[0x001,0x000] : m16.uw[12345] r16.uw[0] => 1.uw[0]
+cmovc eflags[0x001,0x001] : m16.uw[12345] r16.uw[0] => 1.uw[12345]
+cmove eflags[0x040,0x000] : r16.uw[12345] r16.uw[0] => 1.uw[0]
+cmove eflags[0x040,0x040] : r16.uw[12345] r16.uw[0] => 1.uw[12345]
+cmove eflags[0x040,0x000] : m16.uw[12345] r16.uw[0] => 1.uw[0]
+cmove eflags[0x040,0x040] : m16.uw[12345] r16.uw[0] => 1.uw[12345]
+cmovg eflags[0x8c0,0x000] : r16.uw[12345] r16.uw[0] => 1.uw[12345]
+cmovg eflags[0x8c0,0x040] : r16.uw[12345] r16.uw[0] => 1.uw[0]
+cmovg eflags[0x8c0,0x080] : r16.uw[12345] r16.uw[0] => 1.uw[0]
+cmovg eflags[0x8c0,0x0c0] : r16.uw[12345] r16.uw[0] => 1.uw[0]
+cmovg eflags[0x8c0,0x800] : r16.uw[12345] r16.uw[0] => 1.uw[0]
+cmovg eflags[0x8c0,0x840] : r16.uw[12345] r16.uw[0] => 1.uw[0]
+cmovg eflags[0x8c0,0x880] : r16.uw[12345] r16.uw[0] => 1.uw[12345]
+cmovg eflags[0x8c0,0x8c0] : r16.uw[12345] r16.uw[0] => 1.uw[0]
+cmovg eflags[0x8c0,0x000] : m16.uw[12345] r16.uw[0] => 1.uw[12345]
+cmovg eflags[0x8c0,0x040] : m16.uw[12345] r16.uw[0] => 1.uw[0]
+cmovg eflags[0x8c0,0x080] : m16.uw[12345] r16.uw[0] => 1.uw[0]
+cmovg eflags[0x8c0,0x0c0] : m16.uw[12345] r16.uw[0] => 1.uw[0]
+cmovg eflags[0x8c0,0x800] : m16.uw[12345] r16.uw[0] => 1.uw[0]
+cmovg eflags[0x8c0,0x840] : m16.uw[12345] r16.uw[0] => 1.uw[0]
+cmovg eflags[0x8c0,0x880] : m16.uw[12345] r16.uw[0] => 1.uw[12345]
+cmovg eflags[0x8c0,0x8c0] : m16.uw[12345] r16.uw[0] => 1.uw[0]
+cmovge eflags[0x8c0,0x000] : r16.uw[12345] r16.uw[0] => 1.uw[12345]
+cmovge eflags[0x8c0,0x080] : r16.uw[12345] r16.uw[0] => 1.uw[0]
+cmovge eflags[0x8c0,0x800] : r16.uw[12345] r16.uw[0] => 1.uw[0]
+cmovge eflags[0x8c0,0x880] : r16.uw[12345] r16.uw[0] => 1.uw[12345]
+cmovge eflags[0x8c0,0x000] : m16.uw[12345] r16.uw[0] => 1.uw[12345]
+cmovge eflags[0x8c0,0x080] : m16.uw[12345] r16.uw[0] => 1.uw[0]
+cmovge eflags[0x8c0,0x800] : m16.uw[12345] r16.uw[0] => 1.uw[0]
+cmovge eflags[0x8c0,0x880] : m16.uw[12345] r16.uw[0] => 1.uw[12345]
+cmovl eflags[0x8c0,0x000] : r16.uw[12345] r16.uw[0] => 1.uw[0]
+cmovl eflags[0x8c0,0x080] : r16.uw[12345] r16.uw[0] => 1.uw[12345]
+cmovl eflags[0x8c0,0x800] : r16.uw[12345] r16.uw[0] => 1.uw[12345]
+cmovl eflags[0x8c0,0x880] : r16.uw[12345] r16.uw[0] => 1.uw[0]
+cmovl eflags[0x8c0,0x000] : m16.uw[12345] r16.uw[0] => 1.uw[0]
+cmovl eflags[0x8c0,0x080] : m16.uw[12345] r16.uw[0] => 1.uw[12345]
+cmovl eflags[0x8c0,0x800] : m16.uw[12345] r16.uw[0] => 1.uw[12345]
+cmovl eflags[0x8c0,0x880] : m16.uw[12345] r16.uw[0] => 1.uw[0]
+cmovle eflags[0x8c0,0x000] : r16.uw[12345] r16.uw[0] => 1.uw[0]
+cmovle eflags[0x8c0,0x040] : r16.uw[12345] r16.uw[0] => 1.uw[12345]
+cmovle eflags[0x8c0,0x080] : r16.uw[12345] r16.uw[0] => 1.uw[12345]
+cmovle eflags[0x8c0,0x0c0] : r16.uw[12345] r16.uw[0] => 1.uw[12345]
+cmovle eflags[0x8c0,0x800] : r16.uw[12345] r16.uw[0] => 1.uw[12345]
+cmovle eflags[0x8c0,0x840] : r16.uw[12345] r16.uw[0] => 1.uw[12345]
+cmovle eflags[0x8c0,0x880] : r16.uw[12345] r16.uw[0] => 1.uw[0]
+cmovle eflags[0x8c0,0x8c0] : r16.uw[12345] r16.uw[0] => 1.uw[12345]
+cmovle eflags[0x8c0,0x000] : m16.uw[12345] r16.uw[0] => 1.uw[0]
+cmovle eflags[0x8c0,0x040] : m16.uw[12345] r16.uw[0] => 1.uw[12345]
+cmovle eflags[0x8c0,0x080] : m16.uw[12345] r16.uw[0] => 1.uw[12345]
+cmovle eflags[0x8c0,0x0c0] : m16.uw[12345] r16.uw[0] => 1.uw[12345]
+cmovle eflags[0x8c0,0x800] : m16.uw[12345] r16.uw[0] => 1.uw[12345]
+cmovle eflags[0x8c0,0x840] : m16.uw[12345] r16.uw[0] => 1.uw[12345]
+cmovle eflags[0x8c0,0x880] : m16.uw[12345] r16.uw[0] => 1.uw[0]
+cmovle eflags[0x8c0,0x8c0] : m16.uw[12345] r16.uw[0] => 1.uw[12345]
+cmovna eflags[0x041,0x000] : r16.uw[12345] r16.uw[0] => 1.uw[0]
+cmovna eflags[0x041,0x001] : r16.uw[12345] r16.uw[0] => 1.uw[12345]
+cmovna eflags[0x041,0x040] : r16.uw[12345] r16.uw[0] => 1.uw[12345]
+cmovna eflags[0x041,0x041] : r16.uw[12345] r16.uw[0] => 1.uw[12345]
+cmovna eflags[0x041,0x000] : m16.uw[12345] r16.uw[0] => 1.uw[0]
+cmovna eflags[0x041,0x001] : m16.uw[12345] r16.uw[0] => 1.uw[12345]
+cmovna eflags[0x041,0x040] : m16.uw[12345] r16.uw[0] => 1.uw[12345]
+cmovna eflags[0x041,0x041] : m16.uw[12345] r16.uw[0] => 1.uw[12345]
+cmovnae eflags[0x001,0x000] : r16.uw[12345] r16.uw[0] => 1.uw[0]
+cmovnae eflags[0x001,0x001] : r16.uw[12345] r16.uw[0] => 1.uw[12345]
+cmovnae eflags[0x001,0x000] : m16.uw[12345] r16.uw[0] => 1.uw[0]
+cmovnae eflags[0x001,0x001] : m16.uw[12345] r16.uw[0] => 1.uw[12345]
+cmovnb eflags[0x001,0x000] : r16.uw[12345] r16.uw[0] => 1.uw[12345]
+cmovnb eflags[0x001,0x001] : r16.uw[12345] r16.uw[0] => 1.uw[0]
+cmovnb eflags[0x001,0x000] : m16.uw[12345] r16.uw[0] => 1.uw[12345]
+cmovnb eflags[0x001,0x001] : m16.uw[12345] r16.uw[0] => 1.uw[0]
+cmovnbe eflags[0x041,0x000] : r16.uw[12345] r16.uw[0] => 1.uw[12345]
+cmovnbe eflags[0x041,0x001] : r16.uw[12345] r16.uw[0] => 1.uw[0]
+cmovnbe eflags[0x041,0x040] : r16.uw[12345] r16.uw[0] => 1.uw[0]
+cmovnbe eflags[0x041,0x041] : r16.uw[12345] r16.uw[0] => 1.uw[0]
+cmovnbe eflags[0x041,0x000] : m16.uw[12345] r16.uw[0] => 1.uw[12345]
+cmovnbe eflags[0x041,0x001] : m16.uw[12345] r16.uw[0] => 1.uw[0]
+cmovnbe eflags[0x041,0x040] : m16.uw[12345] r16.uw[0] => 1.uw[0]
+cmovnbe eflags[0x041,0x041] : m16.uw[12345] r16.uw[0] => 1.uw[0]
+cmovnc eflags[0x001,0x000] : r16.uw[12345] r16.uw[0] => 1.uw[12345]
+cmovnc eflags[0x001,0x001] : r16.uw[12345] r16.uw[0] => 1.uw[0]
+cmovnc eflags[0x001,0x000] : m16.uw[12345] r16.uw[0] => 1.uw[12345]
+cmovnc eflags[0x001,0x001] : m16.uw[12345] r16.uw[0] => 1.uw[0]
+cmovne eflags[0x040,0x000] : r16.uw[12345] r16.uw[0] => 1.uw[12345]
+cmovne eflags[0x040,0x040] : r16.uw[12345] r16.uw[0] => 1.uw[0]
+cmovne eflags[0x040,0x000] : m16.uw[12345] r16.uw[0] => 1.uw[12345]
+cmovne eflags[0x040,0x040] : m16.uw[12345] r16.uw[0] => 1.uw[0]
+cmovng eflags[0x8c0,0x000] : r16.uw[12345] r16.uw[0] => 1.uw[0]
+cmovng eflags[0x8c0,0x040] : r16.uw[12345] r16.uw[0] => 1.uw[12345]
+cmovng eflags[0x8c0,0x080] : r16.uw[12345] r16.uw[0] => 1.uw[12345]
+cmovng eflags[0x8c0,0x0c0] : r16.uw[12345] r16.uw[0] => 1.uw[12345]
+cmovng eflags[0x8c0,0x800] : r16.uw[12345] r16.uw[0] => 1.uw[12345]
+cmovng eflags[0x8c0,0x840] : r16.uw[12345] r16.uw[0] => 1.uw[12345]
+cmovng eflags[0x8c0,0x880] : r16.uw[12345] r16.uw[0] => 1.uw[0]
+cmovng eflags[0x8c0,0x8c0] : r16.uw[12345] r16.uw[0] => 1.uw[12345]
+cmovng eflags[0x8c0,0x000] : m16.uw[12345] r16.uw[0] => 1.uw[0]
+cmovng eflags[0x8c0,0x040] : m16.uw[12345] r16.uw[0] => 1.uw[12345]
+cmovng eflags[0x8c0,0x080] : m16.uw[12345] r16.uw[0] => 1.uw[12345]
+cmovng eflags[0x8c0,0x0c0] : m16.uw[12345] r16.uw[0] => 1.uw[12345]
+cmovng eflags[0x8c0,0x800] : m16.uw[12345] r16.uw[0] => 1.uw[12345]
+cmovng eflags[0x8c0,0x840] : m16.uw[12345] r16.uw[0] => 1.uw[12345]
+cmovng eflags[0x8c0,0x880] : m16.uw[12345] r16.uw[0] => 1.uw[0]
+cmovng eflags[0x8c0,0x8c0] : m16.uw[12345] r16.uw[0] => 1.uw[12345]
+cmovnge eflags[0x8c0,0x000] : r16.uw[12345] r16.uw[0] => 1.uw[0]
+cmovnge eflags[0x8c0,0x080] : r16.uw[12345] r16.uw[0] => 1.uw[12345]
+cmovnge eflags[0x8c0,0x800] : r16.uw[12345] r16.uw[0] => 1.uw[12345]
+cmovnge eflags[0x8c0,0x880] : r16.uw[12345] r16.uw[0] => 1.uw[0]
+cmovnge eflags[0x8c0,0x000] : m16.uw[12345] r16.uw[0] => 1.uw[0]
+cmovnge eflags[0x8c0,0x080] : m16.uw[12345] r16.uw[0] => 1.uw[12345]
+cmovnge eflags[0x8c0,0x800] : m16.uw[12345] r16.uw[0] => 1.uw[12345]
+cmovnge eflags[0x8c0,0x880] : m16.uw[12345] r16.uw[0] => 1.uw[0]
+cmovnl eflags[0x8c0,0x000] : r16.uw[12345] r16.uw[0] => 1.uw[12345]
+cmovnl eflags[0x8c0,0x080] : r16.uw[12345] r16.uw[0] => 1.uw[0]
+cmovnl eflags[0x8c0,0x800] : r16.uw[12345] r16.uw[0] => 1.uw[0]
+cmovnl eflags[0x8c0,0x880] : r16.uw[12345] r16.uw[0] => 1.uw[12345]
+cmovnl eflags[0x8c0,0x000] : m16.uw[12345] r16.uw[0] => 1.uw[12345]
+cmovnl eflags[0x8c0,0x080] : m16.uw[12345] r16.uw[0] => 1.uw[0]
+cmovnl eflags[0x8c0,0x800] : m16.uw[12345] r16.uw[0] => 1.uw[0]
+cmovnl eflags[0x8c0,0x880] : m16.uw[12345] r16.uw[0] => 1.uw[12345]
+cmovnle eflags[0x8c0,0x000] : r16.uw[12345] r16.uw[0] => 1.uw[12345]
+cmovnle eflags[0x8c0,0x040] : r16.uw[12345] r16.uw[0] => 1.uw[0]
+cmovnle eflags[0x8c0,0x080] : r16.uw[12345] r16.uw[0] => 1.uw[0]
+cmovnle eflags[0x8c0,0x0c0] : r16.uw[12345] r16.uw[0] => 1.uw[0]
+cmovnle eflags[0x8c0,0x800] : r16.uw[12345] r16.uw[0] => 1.uw[0]
+cmovnle eflags[0x8c0,0x840] : r16.uw[12345] r16.uw[0] => 1.uw[0]
+cmovnle eflags[0x8c0,0x880] : r16.uw[12345] r16.uw[0] => 1.uw[12345]
+cmovnle eflags[0x8c0,0x8c0] : r16.uw[12345] r16.uw[0] => 1.uw[0]
+cmovnle eflags[0x8c0,0x000] : m16.uw[12345] r16.uw[0] => 1.uw[12345]
+cmovnle eflags[0x8c0,0x040] : m16.uw[12345] r16.uw[0] => 1.uw[0]
+cmovnle eflags[0x8c0,0x080] : m16.uw[12345] r16.uw[0] => 1.uw[0]
+cmovnle eflags[0x8c0,0x0c0] : m16.uw[12345] r16.uw[0] => 1.uw[0]
+cmovnle eflags[0x8c0,0x800] : m16.uw[12345] r16.uw[0] => 1.uw[0]
+cmovnle eflags[0x8c0,0x840] : m16.uw[12345] r16.uw[0] => 1.uw[0]
+cmovnle eflags[0x8c0,0x880] : m16.uw[12345] r16.uw[0] => 1.uw[12345]
+cmovnle eflags[0x8c0,0x8c0] : m16.uw[12345] r16.uw[0] => 1.uw[0]
+cmovno eflags[0x800,0x000] : r16.uw[12345] r16.uw[0] => 1.uw[12345]
+cmovno eflags[0x800,0x800] : r16.uw[12345] r16.uw[0] => 1.uw[0]
+cmovno eflags[0x800,0x000] : m16.uw[12345] r16.uw[0] => 1.uw[12345]
+cmovno eflags[0x800,0x800] : m16.uw[12345] r16.uw[0] => 1.uw[0]
+cmovnp eflags[0x004,0x000] : r16.uw[12345] r16.uw[0] => 1.uw[12345]
+cmovnp eflags[0x004,0x004] : r16.uw[12345] r16.uw[0] => 1.uw[0]
+cmovnp eflags[0x004,0x000] : m16.uw[12345] r16.uw[0] => 1.uw[12345]
+cmovnp eflags[0x004,0x004] : m16.uw[12345] r16.uw[0] => 1.uw[0]
+cmovns eflags[0x080,0x000] : r16.uw[12345] r16.uw[0] => 1.uw[12345]
+cmovns eflags[0x080,0x080] : r16.uw[12345] r16.uw[0] => 1.uw[0]
+cmovns eflags[0x080,0x000] : m16.uw[12345] r16.uw[0] => 1.uw[12345]
+cmovns eflags[0x080,0x080] : m16.uw[12345] r16.uw[0] => 1.uw[0]
+cmovnz eflags[0x040,0x000] : r16.uw[12345] r16.uw[0] => 1.uw[12345]
+cmovnz eflags[0x040,0x040] : r16.uw[12345] r16.uw[0] => 1.uw[0]
+cmovnz eflags[0x040,0x000] : m16.uw[12345] r16.uw[0] => 1.uw[12345]
+cmovnz eflags[0x040,0x040] : m16.uw[12345] r16.uw[0] => 1.uw[0]
+cmovo eflags[0x800,0x000] : r16.uw[12345] r16.uw[0] => 1.uw[0]
+cmovo eflags[0x800,0x800] : r16.uw[12345] r16.uw[0] => 1.uw[12345]
+cmovo eflags[0x800,0x000] : m16.uw[12345] r16.uw[0] => 1.uw[0]
+cmovo eflags[0x800,0x800] : m16.uw[12345] r16.uw[0] => 1.uw[12345]
+cmovp eflags[0x004,0x000] : r16.uw[12345] r16.uw[0] => 1.uw[0]
+cmovp eflags[0x004,0x004] : r16.uw[12345] r16.uw[0] => 1.uw[12345]
+cmovp eflags[0x004,0x000] : m16.uw[12345] r16.uw[0] => 1.uw[0]
+cmovp eflags[0x004,0x004] : m16.uw[12345] r16.uw[0] => 1.uw[12345]
+cmovs eflags[0x080,0x000] : r16.uw[12345] r16.uw[0] => 1.uw[0]
+cmovs eflags[0x080,0x080] : r16.uw[12345] r16.uw[0] => 1.uw[12345]
+cmovs eflags[0x080,0x000] : m16.uw[12345] r16.uw[0] => 1.uw[0]
+cmovs eflags[0x080,0x080] : m16.uw[12345] r16.uw[0] => 1.uw[12345]
+cmovz eflags[0x040,0x000] : r16.uw[12345] r16.uw[0] => 1.uw[0]
+cmovz eflags[0x040,0x040] : r16.uw[12345] r16.uw[0] => 1.uw[12345]
+cmovz eflags[0x040,0x000] : m16.uw[12345] r16.uw[0] => 1.uw[0]
+cmovz eflags[0x040,0x040] : m16.uw[12345] r16.uw[0] => 1.uw[12345]
+cmova eflags[0x041,0x000] : r32.ud[12345678] r32.ud[0] => 1.ud[12345678]
+cmova eflags[0x041,0x001] : r32.ud[12345678] r32.ud[0] => 1.ud[0]
+cmova eflags[0x041,0x040] : r32.ud[12345678] r32.ud[0] => 1.ud[0]
+cmova eflags[0x041,0x041] : r32.ud[12345678] r32.ud[0] => 1.ud[0]
+cmova eflags[0x041,0x000] : m32.ud[12345678] r32.ud[0] => 1.ud[12345678]
+cmova eflags[0x041,0x001] : m32.ud[12345678] r32.ud[0] => 1.ud[0]
+cmova eflags[0x041,0x040] : m32.ud[12345678] r32.ud[0] => 1.ud[0]
+cmova eflags[0x041,0x041] : m32.ud[12345678] r32.ud[0] => 1.ud[0]
+cmovae eflags[0x001,0x000] : r32.ud[12345678] r32.ud[0] => 1.ud[12345678]
+cmovae eflags[0x001,0x001] : r32.ud[12345678] r32.ud[0] => 1.ud[0]
+cmovae eflags[0x001,0x000] : m32.ud[12345678] r32.ud[0] => 1.ud[12345678]
+cmovae eflags[0x001,0x001] : m32.ud[12345678] r32.ud[0] => 1.ud[0]
+cmovb eflags[0x001,0x000] : r32.ud[12345678] r32.ud[0] => 1.ud[0]
+cmovb eflags[0x001,0x001] : r32.ud[12345678] r32.ud[0] => 1.ud[12345678]
+cmovb eflags[0x001,0x000] : m32.ud[12345678] r32.ud[0] => 1.ud[0]
+cmovb eflags[0x001,0x001] : m32.ud[12345678] r32.ud[0] => 1.ud[12345678]
+cmovbe eflags[0x041,0x000] : r32.ud[12345678] r32.ud[0] => 1.ud[0]
+cmovbe eflags[0x041,0x001] : r32.ud[12345678] r32.ud[0] => 1.ud[12345678]
+cmovbe eflags[0x041,0x040] : r32.ud[12345678] r32.ud[0] => 1.ud[12345678]
+cmovbe eflags[0x041,0x041] : r32.ud[12345678] r32.ud[0] => 1.ud[12345678]
+cmovbe eflags[0x041,0x000] : m32.ud[12345678] r32.ud[0] => 1.ud[0]
+cmovbe eflags[0x041,0x001] : m32.ud[12345678] r32.ud[0] => 1.ud[12345678]
+cmovbe eflags[0x041,0x040] : m32.ud[12345678] r32.ud[0] => 1.ud[12345678]
+cmovbe eflags[0x041,0x041] : m32.ud[12345678] r32.ud[0] => 1.ud[12345678]
+cmovc eflags[0x001,0x000] : r32.ud[12345678] r32.ud[0] => 1.ud[0]
+cmovc eflags[0x001,0x001] : r32.ud[12345678] r32.ud[0] => 1.ud[12345678]
+cmovc eflags[0x001,0x000] : m32.ud[12345678] r32.ud[0] => 1.ud[0]
+cmovc eflags[0x001,0x001] : m32.ud[12345678] r32.ud[0] => 1.ud[12345678]
+cmove eflags[0x040,0x000] : r32.ud[12345678] r32.ud[0] => 1.ud[0]
+cmove eflags[0x040,0x040] : r32.ud[12345678] r32.ud[0] => 1.ud[12345678]
+cmove eflags[0x040,0x000] : m32.ud[12345678] r32.ud[0] => 1.ud[0]
+cmove eflags[0x040,0x040] : m32.ud[12345678] r32.ud[0] => 1.ud[12345678]
+cmovg eflags[0x8c0,0x000] : r32.ud[12345678] r32.ud[0] => 1.ud[12345678]
+cmovg eflags[0x8c0,0x040] : r32.ud[12345678] r32.ud[0] => 1.ud[0]
+cmovg eflags[0x8c0,0x080] : r32.ud[12345678] r32.ud[0] => 1.ud[0]
+cmovg eflags[0x8c0,0x0c0] : r32.ud[12345678] r32.ud[0] => 1.ud[0]
+cmovg eflags[0x8c0,0x800] : r32.ud[12345678] r32.ud[0] => 1.ud[0]
+cmovg eflags[0x8c0,0x840] : r32.ud[12345678] r32.ud[0] => 1.ud[0]
+cmovg eflags[0x8c0,0x880] : r32.ud[12345678] r32.ud[0] => 1.ud[12345678]
+cmovg eflags[0x8c0,0x8c0] : r32.ud[12345678] r32.ud[0] => 1.ud[0]
+cmovg eflags[0x8c0,0x000] : m32.ud[12345678] r32.ud[0] => 1.ud[12345678]
+cmovg eflags[0x8c0,0x040] : m32.ud[12345678] r32.ud[0] => 1.ud[0]
+cmovg eflags[0x8c0,0x080] : m32.ud[12345678] r32.ud[0] => 1.ud[0]
+cmovg eflags[0x8c0,0x0c0] : m32.ud[12345678] r32.ud[0] => 1.ud[0]
+cmovg eflags[0x8c0,0x800] : m32.ud[12345678] r32.ud[0] => 1.ud[0]
+cmovg eflags[0x8c0,0x840] : m32.ud[12345678] r32.ud[0] => 1.ud[0]
+cmovg eflags[0x8c0,0x880] : m32.ud[12345678] r32.ud[0] => 1.ud[12345678]
+cmovg eflags[0x8c0,0x8c0] : m32.ud[12345678] r32.ud[0] => 1.ud[0]
+cmovge eflags[0x8c0,0x000] : r32.ud[12345678] r32.ud[0] => 1.ud[12345678]
+cmovge eflags[0x8c0,0x080] : r32.ud[12345678] r32.ud[0] => 1.ud[0]
+cmovge eflags[0x8c0,0x800] : r32.ud[12345678] r32.ud[0] => 1.ud[0]
+cmovge eflags[0x8c0,0x880] : r32.ud[12345678] r32.ud[0] => 1.ud[12345678]
+cmovge eflags[0x8c0,0x000] : m32.ud[12345678] r32.ud[0] => 1.ud[12345678]
+cmovge eflags[0x8c0,0x080] : m32.ud[12345678] r32.ud[0] => 1.ud[0]
+cmovge eflags[0x8c0,0x800] : m32.ud[12345678] r32.ud[0] => 1.ud[0]
+cmovge eflags[0x8c0,0x880] : m32.ud[12345678] r32.ud[0] => 1.ud[12345678]
+cmovl eflags[0x8c0,0x000] : r32.ud[12345678] r32.ud[0] => 1.ud[0]
+cmovl eflags[0x8c0,0x080] : r32.ud[12345678] r32.ud[0] => 1.ud[12345678]
+cmovl eflags[0x8c0,0x800] : r32.ud[12345678] r32.ud[0] => 1.ud[12345678]
+cmovl eflags[0x8c0,0x880] : r32.ud[12345678] r32.ud[0] => 1.ud[0]
+cmovl eflags[0x8c0,0x000] : m32.ud[12345678] r32.ud[0] => 1.ud[0]
+cmovl eflags[0x8c0,0x080] : m32.ud[12345678] r32.ud[0] => 1.ud[12345678]
+cmovl eflags[0x8c0,0x800] : m32.ud[12345678] r32.ud[0] => 1.ud[12345678]
+cmovl eflags[0x8c0,0x880] : m32.ud[12345678] r32.ud[0] => 1.ud[0]
+cmovle eflags[0x8c0,0x000] : r32.ud[12345678] r32.ud[0] => 1.ud[0]
+cmovle eflags[0x8c0,0x040] : r32.ud[12345678] r32.ud[0] => 1.ud[12345678]
+cmovle eflags[0x8c0,0x080] : r32.ud[12345678] r32.ud[0] => 1.ud[12345678]
+cmovle eflags[0x8c0,0x0c0] : r32.ud[12345678] r32.ud[0] => 1.ud[12345678]
+cmovle eflags[0x8c0,0x800] : r32.ud[12345678] r32.ud[0] => 1.ud[12345678]
+cmovle eflags[0x8c0,0x840] : r32.ud[12345678] r32.ud[0] => 1.ud[12345678]
+cmovle eflags[0x8c0,0x880] : r32.ud[12345678] r32.ud[0] => 1.ud[0]
+cmovle eflags[0x8c0,0x8c0] : r32.ud[12345678] r32.ud[0] => 1.ud[12345678]
+cmovle eflags[0x8c0,0x000] : m32.ud[12345678] r32.ud[0] => 1.ud[0]
+cmovle eflags[0x8c0,0x040] : m32.ud[12345678] r32.ud[0] => 1.ud[12345678]
+cmovle eflags[0x8c0,0x080] : m32.ud[12345678] r32.ud[0] => 1.ud[12345678]
+cmovle eflags[0x8c0,0x0c0] : m32.ud[12345678] r32.ud[0] => 1.ud[12345678]
+cmovle eflags[0x8c0,0x800] : m32.ud[12345678] r32.ud[0] => 1.ud[12345678]
+cmovle eflags[0x8c0,0x840] : m32.ud[12345678] r32.ud[0] => 1.ud[12345678]
+cmovle eflags[0x8c0,0x880] : m32.ud[12345678] r32.ud[0] => 1.ud[0]
+cmovle eflags[0x8c0,0x8c0] : m32.ud[12345678] r32.ud[0] => 1.ud[12345678]
+cmovna eflags[0x041,0x000] : r32.ud[12345678] r32.ud[0] => 1.ud[0]
+cmovna eflags[0x041,0x001] : r32.ud[12345678] r32.ud[0] => 1.ud[12345678]
+cmovna eflags[0x041,0x040] : r32.ud[12345678] r32.ud[0] => 1.ud[12345678]
+cmovna eflags[0x041,0x041] : r32.ud[12345678] r32.ud[0] => 1.ud[12345678]
+cmovna eflags[0x041,0x000] : m32.ud[12345678] r32.ud[0] => 1.ud[0]
+cmovna eflags[0x041,0x001] : m32.ud[12345678] r32.ud[0] => 1.ud[12345678]
+cmovna eflags[0x041,0x040] : m32.ud[12345678] r32.ud[0] => 1.ud[12345678]
+cmovna eflags[0x041,0x041] : m32.ud[12345678] r32.ud[0] => 1.ud[12345678]
+cmovnae eflags[0x001,0x000] : r32.ud[12345678] r32.ud[0] => 1.ud[0]
+cmovnae eflags[0x001,0x001] : r32.ud[12345678] r32.ud[0] => 1.ud[12345678]
+cmovnae eflags[0x001,0x000] : m32.ud[12345678] r32.ud[0] => 1.ud[0]
+cmovnae eflags[0x001,0x001] : m32.ud[12345678] r32.ud[0] => 1.ud[12345678]
+cmovnb eflags[0x001,0x000] : r32.ud[12345678] r32.ud[0] => 1.ud[12345678]
+cmovnb eflags[0x001,0x001] : r32.ud[12345678] r32.ud[0] => 1.ud[0]
+cmovnb eflags[0x001,0x000] : m32.ud[12345678] r32.ud[0] => 1.ud[12345678]
+cmovnb eflags[0x001,0x001] : m32.ud[12345678] r32.ud[0] => 1.ud[0]
+cmovnbe eflags[0x041,0x000] : r32.ud[12345678] r32.ud[0] => 1.ud[12345678]
+cmovnbe eflags[0x041,0x001] : r32.ud[12345678] r32.ud[0] => 1.ud[0]
+cmovnbe eflags[0x041,0x040] : r32.ud[12345678] r32.ud[0] => 1.ud[0]
+cmovnbe eflags[0x041,0x041] : r32.ud[12345678] r32.ud[0] => 1.ud[0]
+cmovnbe eflags[0x041,0x000] : m32.ud[12345678] r32.ud[0] => 1.ud[12345678]
+cmovnbe eflags[0x041,0x001] : m32.ud[12345678] r32.ud[0] => 1.ud[0]
+cmovnbe eflags[0x041,0x040] : m32.ud[12345678] r32.ud[0] => 1.ud[0]
+cmovnbe eflags[0x041,0x041] : m32.ud[12345678] r32.ud[0] => 1.ud[0]
+cmovnc eflags[0x001,0x000] : r32.ud[12345678] r32.ud[0] => 1.ud[12345678]
+cmovnc eflags[0x001,0x001] : r32.ud[12345678] r32.ud[0] => 1.ud[0]
+cmovnc eflags[0x001,0x000] : m32.ud[12345678] r32.ud[0] => 1.ud[12345678]
+cmovnc eflags[0x001,0x001] : m32.ud[12345678] r32.ud[0] => 1.ud[0]
+cmovne eflags[0x040,0x000] : r32.ud[12345678] r32.ud[0] => 1.ud[12345678]
+cmovne eflags[0x040,0x040] : r32.ud[12345678] r32.ud[0] => 1.ud[0]
+cmovne eflags[0x040,0x000] : m32.ud[12345678] r32.ud[0] => 1.ud[12345678]
+cmovne eflags[0x040,0x040] : m32.ud[12345678] r32.ud[0] => 1.ud[0]
+cmovng eflags[0x8c0,0x000] : r32.ud[12345678] r32.ud[0] => 1.ud[0]
+cmovng eflags[0x8c0,0x040] : r32.ud[12345678] r32.ud[0] => 1.ud[12345678]
+cmovng eflags[0x8c0,0x080] : r32.ud[12345678] r32.ud[0] => 1.ud[12345678]
+cmovng eflags[0x8c0,0x0c0] : r32.ud[12345678] r32.ud[0] => 1.ud[12345678]
+cmovng eflags[0x8c0,0x800] : r32.ud[12345678] r32.ud[0] => 1.ud[12345678]
+cmovng eflags[0x8c0,0x840] : r32.ud[12345678] r32.ud[0] => 1.ud[12345678]
+cmovng eflags[0x8c0,0x880] : r32.ud[12345678] r32.ud[0] => 1.ud[0]
+cmovng eflags[0x8c0,0x8c0] : r32.ud[12345678] r32.ud[0] => 1.ud[12345678]
+cmovng eflags[0x8c0,0x000] : m32.ud[12345678] r32.ud[0] => 1.ud[0]
+cmovng eflags[0x8c0,0x040] : m32.ud[12345678] r32.ud[0] => 1.ud[12345678]
+cmovng eflags[0x8c0,0x080] : m32.ud[12345678] r32.ud[0] => 1.ud[12345678]
+cmovng eflags[0x8c0,0x0c0] : m32.ud[12345678] r32.ud[0] => 1.ud[12345678]
+cmovng eflags[0x8c0,0x800] : m32.ud[12345678] r32.ud[0] => 1.ud[12345678]
+cmovng eflags[0x8c0,0x840] : m32.ud[12345678] r32.ud[0] => 1.ud[12345678]
+cmovng eflags[0x8c0,0x880] : m32.ud[12345678] r32.ud[0] => 1.ud[0]
+cmovng eflags[0x8c0,0x8c0] : m32.ud[12345678] r32.ud[0] => 1.ud[12345678]
+cmovnge eflags[0x8c0,0x000] : r32.ud[12345678] r32.ud[0] => 1.ud[0]
+cmovnge eflags[0x8c0,0x080] : r32.ud[12345678] r32.ud[0] => 1.ud[12345678]
+cmovnge eflags[0x8c0,0x800] : r32.ud[12345678] r32.ud[0] => 1.ud[12345678]
+cmovnge eflags[0x8c0,0x880] : r32.ud[12345678] r32.ud[0] => 1.ud[0]
+cmovnge eflags[0x8c0,0x000] : m32.ud[12345678] r32.ud[0] => 1.ud[0]
+cmovnge eflags[0x8c0,0x080] : m32.ud[12345678] r32.ud[0] => 1.ud[12345678]
+cmovnge eflags[0x8c0,0x800] : m32.ud[12345678] r32.ud[0] => 1.ud[12345678]
+cmovnge eflags[0x8c0,0x880] : m32.ud[12345678] r32.ud[0] => 1.ud[0]
+cmovnl eflags[0x8c0,0x000] : r32.ud[12345678] r32.ud[0] => 1.ud[12345678]
+cmovnl eflags[0x8c0,0x080] : r32.ud[12345678] r32.ud[0] => 1.ud[0]
+cmovnl eflags[0x8c0,0x800] : r32.ud[12345678] r32.ud[0] => 1.ud[0]
+cmovnl eflags[0x8c0,0x880] : r32.ud[12345678] r32.ud[0] => 1.ud[12345678]
+cmovnl eflags[0x8c0,0x000] : m32.ud[12345678] r32.ud[0] => 1.ud[12345678]
+cmovnl eflags[0x8c0,0x080] : m32.ud[12345678] r32.ud[0] => 1.ud[0]
+cmovnl eflags[0x8c0,0x800] : m32.ud[12345678] r32.ud[0] => 1.ud[0]
+cmovnl eflags[0x8c0,0x880] : m32.ud[12345678] r32.ud[0] => 1.ud[12345678]
+cmovnle eflags[0x8c0,0x000] : r32.ud[12345678] r32.ud[0] => 1.ud[12345678]
+cmovnle eflags[0x8c0,0x040] : r32.ud[12345678] r32.ud[0] => 1.ud[0]
+cmovnle eflags[0x8c0,0x080] : r32.ud[12345678] r32.ud[0] => 1.ud[0]
+cmovnle eflags[0x8c0,0x0c0] : r32.ud[12345678] r32.ud[0] => 1.ud[0]
+cmovnle eflags[0x8c0,0x800] : r32.ud[12345678] r32.ud[0] => 1.ud[0]
+cmovnle eflags[0x8c0,0x840] : r32.ud[12345678] r32.ud[0] => 1.ud[0]
+cmovnle eflags[0x8c0,0x880] : r32.ud[12345678] r32.ud[0] => 1.ud[12345678]
+cmovnle eflags[0x8c0,0x8c0] : r32.ud[12345678] r32.ud[0] => 1.ud[0]
+cmovnle eflags[0x8c0,0x000] : m32.ud[12345678] r32.ud[0] => 1.ud[12345678]
+cmovnle eflags[0x8c0,0x040] : m32.ud[12345678] r32.ud[0] => 1.ud[0]
+cmovnle eflags[0x8c0,0x080] : m32.ud[12345678] r32.ud[0] => 1.ud[0]
+cmovnle eflags[0x8c0,0x0c0] : m32.ud[12345678] r32.ud[0] => 1.ud[0]
+cmovnle eflags[0x8c0,0x800] : m32.ud[12345678] r32.ud[0] => 1.ud[0]
+cmovnle eflags[0x8c0,0x840] : m32.ud[12345678] r32.ud[0] => 1.ud[0]
+cmovnle eflags[0x8c0,0x880] : m32.ud[12345678] r32.ud[0] => 1.ud[12345678]
+cmovnle eflags[0x8c0,0x8c0] : m32.ud[12345678] r32.ud[0] => 1.ud[0]
+cmovno eflags[0x800,0x000] : r32.ud[12345678] r32.ud[0] => 1.ud[12345678]
+cmovno eflags[0x800,0x800] : r32.ud[12345678] r32.ud[0] => 1.ud[0]
+cmovno eflags[0x800,0x000] : m32.ud[12345678] r32.ud[0] => 1.ud[12345678]
+cmovno eflags[0x800,0x800] : m32.ud[12345678] r32.ud[0] => 1.ud[0]
+cmovnp eflags[0x004,0x000] : r32.ud[12345678] r32.ud[0] => 1.ud[12345678]
+cmovnp eflags[0x004,0x004] : r32.ud[12345678] r32.ud[0] => 1.ud[0]
+cmovnp eflags[0x004,0x000] : m32.ud[12345678] r32.ud[0] => 1.ud[12345678]
+cmovnp eflags[0x004,0x004] : m32.ud[12345678] r32.ud[0] => 1.ud[0]
+cmovns eflags[0x080,0x000] : r32.ud[12345678] r32.ud[0] => 1.ud[12345678]
+cmovns eflags[0x080,0x080] : r32.ud[12345678] r32.ud[0] => 1.ud[0]
+cmovns eflags[0x080,0x000] : m32.ud[12345678] r32.ud[0] => 1.ud[12345678]
+cmovns eflags[0x080,0x080] : m32.ud[12345678] r32.ud[0] => 1.ud[0]
+cmovnz eflags[0x040,0x000] : r32.ud[12345678] r32.ud[0] => 1.ud[12345678]
+cmovnz eflags[0x040,0x040] : r32.ud[12345678] r32.ud[0] => 1.ud[0]
+cmovnz eflags[0x040,0x000] : m32.ud[12345678] r32.ud[0] => 1.ud[12345678]
+cmovnz eflags[0x040,0x040] : m32.ud[12345678] r32.ud[0] => 1.ud[0]
+cmovo eflags[0x800,0x000] : r32.ud[12345678] r32.ud[0] => 1.ud[0]
+cmovo eflags[0x800,0x800] : r32.ud[12345678] r32.ud[0] => 1.ud[12345678]
+cmovo eflags[0x800,0x000] : m32.ud[12345678] r32.ud[0] => 1.ud[0]
+cmovo eflags[0x800,0x800] : m32.ud[12345678] r32.ud[0] => 1.ud[12345678]
+cmovp eflags[0x004,0x000] : r32.ud[12345678] r32.ud[0] => 1.ud[0]
+cmovp eflags[0x004,0x004] : r32.ud[12345678] r32.ud[0] => 1.ud[12345678]
+cmovp eflags[0x004,0x000] : m32.ud[12345678] r32.ud[0] => 1.ud[0]
+cmovp eflags[0x004,0x004] : m32.ud[12345678] r32.ud[0] => 1.ud[12345678]
+cmovs eflags[0x080,0x000] : r32.ud[12345678] r32.ud[0] => 1.ud[0]
+cmovs eflags[0x080,0x080] : r32.ud[12345678] r32.ud[0] => 1.ud[12345678]
+cmovs eflags[0x080,0x000] : m32.ud[12345678] r32.ud[0] => 1.ud[0]
+cmovs eflags[0x080,0x080] : m32.ud[12345678] r32.ud[0] => 1.ud[12345678]
+cmovz eflags[0x040,0x000] : r32.ud[12345678] r32.ud[0] => 1.ud[0]
+cmovz eflags[0x040,0x040] : r32.ud[12345678] r32.ud[0] => 1.ud[12345678]
+cmovz eflags[0x040,0x000] : m32.ud[12345678] r32.ud[0] => 1.ud[0]
+cmovz eflags[0x040,0x040] : m32.ud[12345678] r32.ud[0] => 1.ud[12345678]
diff --git a/none/tests/insn_cmov.stderr.exp b/none/tests/insn_cmov.stderr.exp
new file mode 100644
index 0000000..139597f
--- /dev/null
+++ b/none/tests/insn_cmov.stderr.exp
@@ -0,0 +1,2 @@
+
+
diff --git a/none/tests/insn_cmov.stdout.exp b/none/tests/insn_cmov.stdout.exp
new file mode 100644
index 0000000..31ac172
--- /dev/null
+++ b/none/tests/insn_cmov.stdout.exp
@@ -0,0 +1,384 @@
+cmova_1 ... ok
+cmova_2 ... ok
+cmova_3 ... ok
+cmova_4 ... ok
+cmova_5 ... ok
+cmova_6 ... ok
+cmova_7 ... ok
+cmova_8 ... ok
+cmovae_1 ... ok
+cmovae_2 ... ok
+cmovae_3 ... ok
+cmovae_4 ... ok
+cmovb_1 ... ok
+cmovb_2 ... ok
+cmovb_3 ... ok
+cmovb_4 ... ok
+cmovbe_1 ... ok
+cmovbe_2 ... ok
+cmovbe_3 ... ok
+cmovbe_4 ... ok
+cmovbe_5 ... ok
+cmovbe_6 ... ok
+cmovbe_7 ... ok
+cmovbe_8 ... ok
+cmovc_1 ... ok
+cmovc_2 ... ok
+cmovc_3 ... ok
+cmovc_4 ... ok
+cmove_1 ... ok
+cmove_2 ... ok
+cmove_3 ... ok
+cmove_4 ... ok
+cmovg_1 ... ok
+cmovg_2 ... ok
+cmovg_3 ... ok
+cmovg_4 ... ok
+cmovg_5 ... ok
+cmovg_6 ... ok
+cmovg_7 ... ok
+cmovg_8 ... ok
+cmovg_9 ... ok
+cmovg_10 ... ok
+cmovg_11 ... ok
+cmovg_12 ... ok
+cmovg_13 ... ok
+cmovg_14 ... ok
+cmovg_15 ... ok
+cmovg_16 ... ok
+cmovge_1 ... ok
+cmovge_2 ... ok
+cmovge_3 ... ok
+cmovge_4 ... ok
+cmovge_5 ... ok
+cmovge_6 ... ok
+cmovge_7 ... ok
+cmovge_8 ... ok
+cmovl_1 ... ok
+cmovl_2 ... ok
+cmovl_3 ... ok
+cmovl_4 ... ok
+cmovl_5 ... ok
+cmovl_6 ... ok
+cmovl_7 ... ok
+cmovl_8 ... ok
+cmovle_1 ... ok
+cmovle_2 ... ok
+cmovle_3 ... ok
+cmovle_4 ... ok
+cmovle_5 ... ok
+cmovle_6 ... ok
+cmovle_7 ... ok
+cmovle_8 ... ok
+cmovle_9 ... ok
+cmovle_10 ... ok
+cmovle_11 ... ok
+cmovle_12 ... ok
+cmovle_13 ... ok
+cmovle_14 ... ok
+cmovle_15 ... ok
+cmovle_16 ... ok
+cmovna_1 ... ok
+cmovna_2 ... ok
+cmovna_3 ... ok
+cmovna_4 ... ok
+cmovna_5 ... ok
+cmovna_6 ... ok
+cmovna_7 ... ok
+cmovna_8 ... ok
+cmovnae_1 ... ok
+cmovnae_2 ... ok
+cmovnae_3 ... ok
+cmovnae_4 ... ok
+cmovnb_1 ... ok
+cmovnb_2 ... ok
+cmovnb_3 ... ok
+cmovnb_4 ... ok
+cmovnbe_1 ... ok
+cmovnbe_2 ... ok
+cmovnbe_3 ... ok
+cmovnbe_4 ... ok
+cmovnbe_5 ... ok
+cmovnbe_6 ... ok
+cmovnbe_7 ... ok
+cmovnbe_8 ... ok
+cmovnc_1 ... ok
+cmovnc_2 ... ok
+cmovnc_3 ... ok
+cmovnc_4 ... ok
+cmovne_1 ... ok
+cmovne_2 ... ok
+cmovne_3 ... ok
+cmovne_4 ... ok
+cmovng_1 ... ok
+cmovng_2 ... ok
+cmovng_3 ... ok
+cmovng_4 ... ok
+cmovng_5 ... ok
+cmovng_6 ... ok
+cmovng_7 ... ok
+cmovng_8 ... ok
+cmovng_9 ... ok
+cmovng_10 ... ok
+cmovng_11 ... ok
+cmovng_12 ... ok
+cmovng_13 ... ok
+cmovng_14 ... ok
+cmovng_15 ... ok
+cmovng_16 ... ok
+cmovnge_1 ... ok
+cmovnge_2 ... ok
+cmovnge_3 ... ok
+cmovnge_4 ... ok
+cmovnge_5 ... ok
+cmovnge_6 ... ok
+cmovnge_7 ... ok
+cmovnge_8 ... ok
+cmovnl_1 ... ok
+cmovnl_2 ... ok
+cmovnl_3 ... ok
+cmovnl_4 ... ok
+cmovnl_5 ... ok
+cmovnl_6 ... ok
+cmovnl_7 ... ok
+cmovnl_8 ... ok
+cmovnle_1 ... ok
+cmovnle_2 ... ok
+cmovnle_3 ... ok
+cmovnle_4 ... ok
+cmovnle_5 ... ok
+cmovnle_6 ... ok
+cmovnle_7 ... ok
+cmovnle_8 ... ok
+cmovnle_9 ... ok
+cmovnle_10 ... ok
+cmovnle_11 ... ok
+cmovnle_12 ... ok
+cmovnle_13 ... ok
+cmovnle_14 ... ok
+cmovnle_15 ... ok
+cmovnle_16 ... ok
+cmovno_1 ... ok
+cmovno_2 ... ok
+cmovno_3 ... ok
+cmovno_4 ... ok
+cmovnp_1 ... ok
+cmovnp_2 ... ok
+cmovnp_3 ... ok
+cmovnp_4 ... ok
+cmovns_1 ... ok
+cmovns_2 ... ok
+cmovns_3 ... ok
+cmovns_4 ... ok
+cmovnz_1 ... ok
+cmovnz_2 ... ok
+cmovnz_3 ... ok
+cmovnz_4 ... ok
+cmovo_1 ... ok
+cmovo_2 ... ok
+cmovo_3 ... ok
+cmovo_4 ... ok
+cmovp_1 ... ok
+cmovp_2 ... ok
+cmovp_3 ... ok
+cmovp_4 ... ok
+cmovs_1 ... ok
+cmovs_2 ... ok
+cmovs_3 ... ok
+cmovs_4 ... ok
+cmovz_1 ... ok
+cmovz_2 ... ok
+cmovz_3 ... ok
+cmovz_4 ... ok
+cmova_9 ... ok
+cmova_10 ... ok
+cmova_11 ... ok
+cmova_12 ... ok
+cmova_13 ... ok
+cmova_14 ... ok
+cmova_15 ... ok
+cmova_16 ... ok
+cmovae_5 ... ok
+cmovae_6 ... ok
+cmovae_7 ... ok
+cmovae_8 ... ok
+cmovb_5 ... ok
+cmovb_6 ... ok
+cmovb_7 ... ok
+cmovb_8 ... ok
+cmovbe_9 ... ok
+cmovbe_10 ... ok
+cmovbe_11 ... ok
+cmovbe_12 ... ok
+cmovbe_13 ... ok
+cmovbe_14 ... ok
+cmovbe_15 ... ok
+cmovbe_16 ... ok
+cmovc_5 ... ok
+cmovc_6 ... ok
+cmovc_7 ... ok
+cmovc_8 ... ok
+cmove_5 ... ok
+cmove_6 ... ok
+cmove_7 ... ok
+cmove_8 ... ok
+cmovg_17 ... ok
+cmovg_18 ... ok
+cmovg_19 ... ok
+cmovg_20 ... ok
+cmovg_21 ... ok
+cmovg_22 ... ok
+cmovg_23 ... ok
+cmovg_24 ... ok
+cmovg_25 ... ok
+cmovg_26 ... ok
+cmovg_27 ... ok
+cmovg_28 ... ok
+cmovg_29 ... ok
+cmovg_30 ... ok
+cmovg_31 ... ok
+cmovg_32 ... ok
+cmovge_9 ... ok
+cmovge_10 ... ok
+cmovge_11 ... ok
+cmovge_12 ... ok
+cmovge_13 ... ok
+cmovge_14 ... ok
+cmovge_15 ... ok
+cmovge_16 ... ok
+cmovl_9 ... ok
+cmovl_10 ... ok
+cmovl_11 ... ok
+cmovl_12 ... ok
+cmovl_13 ... ok
+cmovl_14 ... ok
+cmovl_15 ... ok
+cmovl_16 ... ok
+cmovle_17 ... ok
+cmovle_18 ... ok
+cmovle_19 ... ok
+cmovle_20 ... ok
+cmovle_21 ... ok
+cmovle_22 ... ok
+cmovle_23 ... ok
+cmovle_24 ... ok
+cmovle_25 ... ok
+cmovle_26 ... ok
+cmovle_27 ... ok
+cmovle_28 ... ok
+cmovle_29 ... ok
+cmovle_30 ... ok
+cmovle_31 ... ok
+cmovle_32 ... ok
+cmovna_9 ... ok
+cmovna_10 ... ok
+cmovna_11 ... ok
+cmovna_12 ... ok
+cmovna_13 ... ok
+cmovna_14 ... ok
+cmovna_15 ... ok
+cmovna_16 ... ok
+cmovnae_5 ... ok
+cmovnae_6 ... ok
+cmovnae_7 ... ok
+cmovnae_8 ... ok
+cmovnb_5 ... ok
+cmovnb_6 ... ok
+cmovnb_7 ... ok
+cmovnb_8 ... ok
+cmovnbe_9 ... ok
+cmovnbe_10 ... ok
+cmovnbe_11 ... ok
+cmovnbe_12 ... ok
+cmovnbe_13 ... ok
+cmovnbe_14 ... ok
+cmovnbe_15 ... ok
+cmovnbe_16 ... ok
+cmovnc_5 ... ok
+cmovnc_6 ... ok
+cmovnc_7 ... ok
+cmovnc_8 ... ok
+cmovne_5 ... ok
+cmovne_6 ... ok
+cmovne_7 ... ok
+cmovne_8 ... ok
+cmovng_17 ... ok
+cmovng_18 ... ok
+cmovng_19 ... ok
+cmovng_20 ... ok
+cmovng_21 ... ok
+cmovng_22 ... ok
+cmovng_23 ... ok
+cmovng_24 ... ok
+cmovng_25 ... ok
+cmovng_26 ... ok
+cmovng_27 ... ok
+cmovng_28 ... ok
+cmovng_29 ... ok
+cmovng_30 ... ok
+cmovng_31 ... ok
+cmovng_32 ... ok
+cmovnge_9 ... ok
+cmovnge_10 ... ok
+cmovnge_11 ... ok
+cmovnge_12 ... ok
+cmovnge_13 ... ok
+cmovnge_14 ... ok
+cmovnge_15 ... ok
+cmovnge_16 ... ok
+cmovnl_9 ... ok
+cmovnl_10 ... ok
+cmovnl_11 ... ok
+cmovnl_12 ... ok
+cmovnl_13 ... ok
+cmovnl_14 ... ok
+cmovnl_15 ... ok
+cmovnl_16 ... ok
+cmovnle_17 ... ok
+cmovnle_18 ... ok
+cmovnle_19 ... ok
+cmovnle_20 ... ok
+cmovnle_21 ... ok
+cmovnle_22 ... ok
+cmovnle_23 ... ok
+cmovnle_24 ... ok
+cmovnle_25 ... ok
+cmovnle_26 ... ok
+cmovnle_27 ... ok
+cmovnle_28 ... ok
+cmovnle_29 ... ok
+cmovnle_30 ... ok
+cmovnle_31 ... ok
+cmovnle_32 ... ok
+cmovno_5 ... ok
+cmovno_6 ... ok
+cmovno_7 ... ok
+cmovno_8 ... ok
+cmovnp_5 ... ok
+cmovnp_6 ... ok
+cmovnp_7 ... ok
+cmovnp_8 ... ok
+cmovns_5 ... ok
+cmovns_6 ... ok
+cmovns_7 ... ok
+cmovns_8 ... ok
+cmovnz_5 ... ok
+cmovnz_6 ... ok
+cmovnz_7 ... ok
+cmovnz_8 ... ok
+cmovo_5 ... ok
+cmovo_6 ... ok
+cmovo_7 ... ok
+cmovo_8 ... ok
+cmovp_5 ... ok
+cmovp_6 ... ok
+cmovp_7 ... ok
+cmovp_8 ... ok
+cmovs_5 ... ok
+cmovs_6 ... ok
+cmovs_7 ... ok
+cmovs_8 ... ok
+cmovz_5 ... ok
+cmovz_6 ... ok
+cmovz_7 ... ok
+cmovz_8 ... ok
diff --git a/none/tests/insn_cmov.vgtest b/none/tests/insn_cmov.vgtest
new file mode 100644
index 0000000..ba14538
--- /dev/null
+++ b/none/tests/insn_cmov.vgtest
@@ -0,0 +1,2 @@
+prog: insn_cmov
+cpu_test: cmov
diff --git a/none/tests/insn_mmxext.def b/none/tests/insn_mmxext.def
new file mode 100644
index 0000000..fd07f87
--- /dev/null
+++ b/none/tests/insn_mmxext.def
@@ -0,0 +1,28 @@
+movntq mm.uq[0x0123456789abcdef] m64.uq[0x1212121234343434] => 1.uq[0x0123456789abcdef]
+pavgb mm.ub[11,22,33,44,55,66,77,88] mm.ub[15,25,35,45,55,65,75,85] => 1.ub[13,24,34,45,55,66,76,87]
+pavgb m64.ub[11,22,33,44,55,66,77,88] mm.ub[15,25,35,45,55,65,75,85] => 1.ub[13,24,34,45,55,66,76,87]
+pavgw mm.uw[1122,3344,5566,7788] mm.uw[1525,3545,5565,7585] => 1.uw[1324,3445,5566,7687]
+pavgw m64.uw[1122,3344,5566,7788] mm.uw[1525,3545,5565,7585] => 1.uw[1324,3445,5566,7687]
+pextrw imm8[0] mm.uw[1234,5678,4321,8765] r32.ud[0xffffffff] => 2.ud[1234]
+pextrw imm8[1] mm.uw[1234,5678,4321,8765] r32.ud[0xffffffff] => 2.ud[5678]
+pextrw imm8[2] mm.uw[1234,5678,4321,8765] r32.ud[0xffffffff] => 2.ud[4321]
+pextrw imm8[3] mm.uw[1234,5678,4321,8765] r32.ud[0xffffffff] => 2.ud[8765]
+pinsrw imm8[0] r32.ud[0xffffffff] mm.uw[1234,5678,4321,8765] => 2.uw[65535,5678,4321,8765]
+pinsrw imm8[1] r32.ud[0xffffffff] mm.uw[1234,5678,4321,8765] => 2.uw[1234,65535,4321,8765]
+pinsrw imm8[2] r32.ud[0xffffffff] mm.uw[1234,5678,4321,8765] => 2.uw[1234,5678,65535,8765]
+pinsrw imm8[3] r32.ud[0xffffffff] mm.uw[1234,5678,4321,8765] => 2.uw[1234,5678,4321,65535]
+pmaxsw mm.sw[-1,2,-3,4] mm.sw[2,-3,4,-5] => 1.sw[2,2,4,4]
+pmaxsw m64.sw[-1,2,-3,4] mm.sw[2,-3,4,-5] => 1.sw[2,2,4,4]
+pmaxub mm.ub[1,2,3,4,5,6,7,8] mm.ub[8,7,6,5,4,3,2,1] => 1.ub[8,7,6,5,5,6,7,8]
+pmaxub m64.ub[1,2,3,4,5,6,7,8] mm.ub[8,7,6,5,4,3,2,1] => 1.ub[8,7,6,5,5,6,7,8]
+pminsw mm.sw[-1,2,-3,4] mm.sw[2,-3,4,-5] => 1.sw[-1,-3,-3,-5]
+pminsw m64.sw[-1,2,-3,4] mm.sw[2,-3,4,-5] => 1.sw[-1,-3,-3,-5]
+pminub mm.ub[1,2,3,4,5,6,7,8] mm.ub[8,7,6,5,4,3,2,1] => 1.ub[1,2,3,4,4,3,2,1]
+pminub m64.ub[1,2,3,4,5,6,7,8] mm.ub[8,7,6,5,4,3,2,1] => 1.ub[1,2,3,4,4,3,2,1]
+pmovmskb mm.uq[0x8000000080008088] r32.ud[0] => 1.ud[0x8b]
+pmulhuw mm.uw[1111,2222,3333,4444] mm.uw[5555,6666,7777,8888] => 1.uw[0x005e,0x00e2,0x018b,0x025a]
+pmulhuw m64.uw[1111,2222,3333,4444] mm.uw[5555,6666,7777,8888] => 1.uw[0x005e,0x00e2,0x018b,0x025a]
+psadbw mm.ub[1,2,3,4,5,6,7,8] mm.ub[8,7,6,5,4,3,2,1] => 1.sw[32,0,0,0]
+psadbw m64.ub[1,2,3,4,5,6,7,8] mm.ub[8,7,6,5,4,3,2,1] => 1.sw[32,0,0,0]
+pshufw imm8[0x1b] mm.sw[11,22,33,44] mm.sw[0,0,0,0] => 2.sw[44,33,22,11]
+pshufw imm8[0x1b] m64.sw[11,22,33,44] mm.sw[0,0,0,0] => 2.sw[44,33,22,11]
diff --git a/none/tests/insn_mmxext.stderr.exp b/none/tests/insn_mmxext.stderr.exp
new file mode 100644
index 0000000..139597f
--- /dev/null
+++ b/none/tests/insn_mmxext.stderr.exp
@@ -0,0 +1,2 @@
+
+
diff --git a/none/tests/insn_mmxext.stdout.exp b/none/tests/insn_mmxext.stdout.exp
new file mode 100644
index 0000000..631f793
--- /dev/null
+++ b/none/tests/insn_mmxext.stdout.exp
@@ -0,0 +1,28 @@
+movntq_1 ... ok
+pavgb_1 ... ok
+pavgb_2 ... ok
+pavgw_1 ... ok
+pavgw_2 ... ok
+pextrw_1 ... ok
+pextrw_2 ... ok
+pextrw_3 ... ok
+pextrw_4 ... ok
+pinsrw_1 ... ok
+pinsrw_2 ... ok
+pinsrw_3 ... ok
+pinsrw_4 ... ok
+pmaxsw_1 ... ok
+pmaxsw_2 ... ok
+pmaxub_1 ... ok
+pmaxub_2 ... ok
+pminsw_1 ... ok
+pminsw_2 ... ok
+pminub_1 ... ok
+pminub_2 ... ok
+pmovmskb_1 ... ok
+pmulhuw_1 ... ok
+pmulhuw_2 ... ok
+psadbw_1 ... ok
+psadbw_2 ... ok
+pshufw_1 ... ok
+pshufw_2 ... ok
diff --git a/none/tests/insn_mmxext.vgtest b/none/tests/insn_mmxext.vgtest
new file mode 100644
index 0000000..32dd1e6
--- /dev/null
+++ b/none/tests/insn_mmxext.vgtest
@@ -0,0 +1,2 @@
+prog: insn_mmxext
+cpu_test: mmxext