Rename the SSE and MMX uinstrs which read/write integer registers, in
a way consistent with the position of the register field in the
instruction. In Intel encoding parlance, the G register is in bits
5,4,3 and the E register is bits 2,1,0, and so we adopt this scheme
consistently. Considering how much confusion this has caused me in
this recent bout of SSE hacking, consistent renaming can only be a
good thing. It makes it a lot easier to figure out if parts of the
SSE handling machinery are correct, or not.
git-svn-id: svn://svn.valgrind.org/valgrind/trunk@1698 a5019735-40e9-0310-863c-91ae7b9d1cf9
diff --git a/coregrind/vg_from_ucode.c b/coregrind/vg_from_ucode.c
index 8b699e6..9bf4332 100644
--- a/coregrind/vg_from_ucode.c
+++ b/coregrind/vg_from_ucode.c
@@ -3744,7 +3744,7 @@
u->val2 );
break;
- case MMX2_RegRd:
+ case MMX2_ERegRd:
vg_assert(u->tag1 == Lit16);
vg_assert(u->tag2 == RealReg);
vg_assert(u->tag3 == NoValue);
@@ -3759,7 +3759,7 @@
u->val2 );
break;
- case MMX2_RegWr:
+ case MMX2_ERegWr:
vg_assert(u->tag1 == Lit16);
vg_assert(u->tag2 == RealReg);
vg_assert(u->tag3 == NoValue);
@@ -3849,7 +3849,7 @@
u->val3 );
break;
- case SSE3g_RegRd:
+ case SSE3e_RegRd:
case SSE3g_RegWr:
vg_assert(u->size == 4);
vg_assert(u->tag1 == Lit16);
@@ -3860,7 +3860,7 @@
emit_get_sse_state();
*sselive = True;
}
- if (u->opcode==SSE3g_RegRd) {
+ if (u->opcode==SSE3e_RegRd) {
emit_SSE3g_RegRd ( u->flags_r, u->flags_w,
(u->val1 >> 8) & 0xFF,
u->val1 & 0xFF,
@@ -3896,7 +3896,7 @@
u->val3 );
break;
- case SSE3g1_RegRd:
+ case SSE3e1_RegRd:
vg_assert(u->size == 2);
vg_assert(u->tag1 == Lit16);
vg_assert(u->tag2 == Lit16);