Removed the need for the user to generate a cache simulation -- now do
automatic cache configuration detection using the CPUID instruction.
This can be overridden from the command-line if necessary.
vg_include.h:
- added the cache_t type and UNDEFINED_CACHE macro
- added command line args (of type cache_t) allowing manual override of
I1/D1/L2 configuration
- added log2(), which is generally useful
vg_main.c, valgrind.in, cachegrind.in:
- added handling of the new --{I1,D1,L2}=<size>,<assoc>,<line_size>
options
vg_cachesim.c:
- lots of stuff for auto-detecting cache configuration with CPUID.
Only handles Intel and AMD chips at the moment, and possibly not all of
them. Falls back onto defaults if anything goes wrong, and the configs
can be manually overridden from the command line anyway.
- now not printing cache summary stats if verbosity == 0. Still writing
cachegrind.out, though.
vg_cachesim_gen.c:
- new file containing stuff shared by the I1/D1/L2 simulations
vg_cachesim_{I1,D1,L2}:
- removed most of it; each now just calls a macro defined in
vg_cachesim_gen.c
vg_cachegen:
- has been cvs removed as it is no longer needed.
Makefile.am:
- added vg_cachesim_gen.c
- removed vg_cachegen
configure.in:
- removed vg_cachegen
git-svn-id: svn://svn.valgrind.org/valgrind/trunk@400 a5019735-40e9-0310-863c-91ae7b9d1cf9
diff --git a/cachegrind/cg_sim_D1.c b/cachegrind/cg_sim_D1.c
index 4a5b0bb..7b8a8da 100644
--- a/cachegrind/cg_sim_D1.c
+++ b/cachegrind/cg_sim_D1.c
@@ -1,93 +1,38 @@
-/* D1 cache simulator, generated by vg_cachegen.
- * total size = 65536 bytes
- * line size = 64 bytes
- * associativity = 2-way associative
- *
- * This file should be #include-d into vg_cachesim.c
- */
+/*--------------------------------------------------------------------*/
+/*--- D1 cache simulation. ---*/
+/*--- vg_cachesim_D1.c ---*/
+/*--------------------------------------------------------------------*/
-static char D1_desc_line[] =
- "desc: D1 cache: 65536 B, 64 B, 2-way associative\n";
+/*
+ This file is part of Valgrind, an x86 protected-mode emulator
+ designed for debugging and profiling binaries on x86-Unixes.
-static UInt D1_tags[512][2];
+ Copyright (C) 2002 Nicholas Nethercote
+ njn25@cam.ac.uk
-static void cachesim_D1_initcache(void)
-{
- UInt set, way;
- for (set = 0; set < 512; set++)
- for (way = 0; way < 2; way++)
- D1_tags[set][way] = 0;
-}
+ This program is free software; you can redistribute it and/or
+ modify it under the terms of the GNU General Public License as
+ published by the Free Software Foundation; either version 2 of the
+ License, or (at your option) any later version.
-static __inline__
-void cachesim_D1_doref(Addr a, UChar size, ULong* m1, ULong *m2)
-{
- register UInt set1 = ( a >> 6) & (512-1);
- register UInt set2 = ((a + size - 1) >> 6) & (512-1);
- register UInt tag = a >> (6 + 9);
+ This program is distributed in the hope that it will be useful, but
+ WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ General Public License for more details.
- if (set1 == set2) {
+ You should have received a copy of the GNU General Public License
+ along with this program; if not, write to the Free Software
+ Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA
+ 02111-1307, USA.
- if (tag == D1_tags[set1][0]) {
- return;
- }
- else if (tag == D1_tags[set1][1]) {
- D1_tags[set1][1] = D1_tags[set1][0];
- D1_tags[set1][0] = tag;
- return;
- }
- else {
- /* A miss */
- D1_tags[set1][1] = D1_tags[set1][0];
- D1_tags[set1][0] = tag;
+ The GNU General Public License is contained in the file LICENSE.
+*/
- (*m1)++;
- cachesim_L2_doref(a, size, m2);
- }
+#include "vg_cachesim_gen.c"
- } else if ((set1 + 1) % 512 == set2) {
+CACHESIM(D1, { (*m1)++; cachesim_L2_doref(a, size, m1, m2); } );
- Bool is_D1_miss = False;
+/*--------------------------------------------------------------------*/
+/*--- end vg_cachesim_D1.c ---*/
+/*--------------------------------------------------------------------*/
- /* Block one */
- if (tag == D1_tags[set1][0]) {
- }
- else if (tag == D1_tags[set1][1]) {
- D1_tags[set1][1] = D1_tags[set1][0];
- D1_tags[set1][0] = tag;
- }
- else {
- /* A miss */
- D1_tags[set1][1] = D1_tags[set1][0];
- D1_tags[set1][0] = tag;
-
- is_D1_miss = True;
- }
-
- /* Block two */
- if (tag == D1_tags[set2][0]) {
- }
- else if (tag == D1_tags[set2][1]) {
- D1_tags[set2][1] = D1_tags[set2][0];
- D1_tags[set2][0] = tag;
- }
- else {
- /* A miss */
- D1_tags[set2][1] = D1_tags[set2][0];
- D1_tags[set2][0] = tag;
-
- is_D1_miss = True;
- }
-
- /* Miss treatment */
- if (is_D1_miss) {
- (*m1)++;
- cachesim_L2_doref(a, size, m2);
- }
-
- } else {
- VG_(printf)("\nERROR: Data item 0x%x of size %u bytes is in two non-adjacent\n", a, size);
- VG_(printf)("sets %d and %d.\n", set1, set2);
- VG_(panic)("D1 cache set mismatch");
- }
-}