vg_symtab2.c:
Discovered sometimes a SLINE stabs entry is the last one (which broke an
assertion). In such a case, we must guess the line's instruction address
range -- I've guessed 4, arbitrarily.
vg_cachegen.in, vg_cachesim_{I1,D1,L2}.c:
Discovered a bad bug in the cache simulation: when determining if a
references straddles two memory blocks, to find the end of the range I was
adding 'size' to the base address, rather than 'size - 1'. This was
causing way too many straddled references, which would inflate the miss
counts.
vg_cachesim.c:
Minor stuff
git-svn-id: svn://svn.valgrind.org/valgrind/trunk@176 a5019735-40e9-0310-863c-91ae7b9d1cf9
11 files changed