commit d7971010f75e299ecba7a28eb836d872549beef1
author sewardj <sewardj@a5019735-40e9-0310-863c-91ae7b9d1cf9> Fri Apr 04 00:21:58 2003 +0000
committer sewardj <sewardj@a5019735-40e9-0310-863c-91ae7b9d1cf9> Fri Apr 04 00:21:58 2003 +0000
tree 857becb4b2e6c5636f9a397e00002b04c3df121b
parent 5488880abdc014b03320238cf2241d2d0b2e7dff

Rationalise ucode generation for 4-byte moves into the MMX unit (movd).


git-svn-id: svn://svn.valgrind.org/valgrind/trunk@1506 a5019735-40e9-0310-863c-91ae7b9d1cf9

cachegrind/cg_main.c

diff --git a/cachegrind/cg_main.c b/cachegrind/cg_main.c
index 0b5cb70..63c3e62 100644
--- a/cachegrind/cg_main.c
+++ b/cachegrind/cg_main.c
@@ -539,7 +539,7 @@
             break;
 
          case MMX2_MemRd:
-            sk_assert(u_in->size == 8);
+            sk_assert(u_in->size == 4 || u_in->size == 8);
             /* fall through */
          case FPU_R:
             sk_assert(!is_LOAD && !is_STORE && !is_FPU_R && !is_FPU_W);
@@ -548,7 +548,7 @@
             break;
 
          case MMX2_MemWr:
-            sk_assert(u_in->size == 8);
+            sk_assert(u_in->size == 4 || u_in->size == 8);
             /* fall through */
          case FPU_W:
             sk_assert(!is_LOAD && !is_STORE && !is_FPU_R && !is_FPU_W);
@@ -752,7 +752,7 @@
             break;
 
          case MMX2_MemRd:
-            sk_assert(u_in->size == 8);
+            sk_assert(u_in->size == 4 || u_in->size == 8);
             /* fall through */
          case FPU_R:
             t_read      = u_in->val2;
@@ -770,7 +770,7 @@
           * As for the MOV, if it's a mod instruction it's redundant, but it's
           * not expensive and mod instructions are rare anyway. */
          case MMX2_MemWr:
-            sk_assert(u_in->size == 8);
+            sk_assert(u_in->size == 4 || u_in->size == 8);
             /* fall through */
          case STORE:
          case FPU_W: