Add a test for vex ppc64 code generation bug fixed by vex r1739
(When generating 64-bit code, ensure that any addresses used in 4 or 8
byte loads or stores of the form reg+imm have the lowest 2 bits of imm
set to zero, so that they can safely be used in ld/ldu/lda/std/stdu
instructions.)



git-svn-id: svn://svn.valgrind.org/valgrind/trunk@6645 a5019735-40e9-0310-863c-91ae7b9d1cf9
5 files changed