sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 1 | |
| 2 | /*--------------------------------------------------------------------*/ |
| 3 | /*--- The JITter: translate ucode back to x86 code. ---*/ |
| 4 | /*--- vg_from_ucode.c ---*/ |
| 5 | /*--------------------------------------------------------------------*/ |
njn | c953984 | 2002-10-02 13:26:35 +0000 | [diff] [blame] | 6 | |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 7 | /* |
njn | c953984 | 2002-10-02 13:26:35 +0000 | [diff] [blame] | 8 | This file is part of Valgrind, an extensible x86 protected-mode |
| 9 | emulator for monitoring program execution on x86-Unixes. |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 10 | |
| 11 | Copyright (C) 2000-2002 Julian Seward |
| 12 | jseward@acm.org |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 13 | |
| 14 | This program is free software; you can redistribute it and/or |
| 15 | modify it under the terms of the GNU General Public License as |
| 16 | published by the Free Software Foundation; either version 2 of the |
| 17 | License, or (at your option) any later version. |
| 18 | |
| 19 | This program is distributed in the hope that it will be useful, but |
| 20 | WITHOUT ANY WARRANTY; without even the implied warranty of |
| 21 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU |
| 22 | General Public License for more details. |
| 23 | |
| 24 | You should have received a copy of the GNU General Public License |
| 25 | along with this program; if not, write to the Free Software |
| 26 | Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA |
| 27 | 02111-1307, USA. |
| 28 | |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 29 | The GNU General Public License is contained in the file COPYING. |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 30 | */ |
| 31 | |
| 32 | #include "vg_include.h" |
| 33 | |
| 34 | |
| 35 | /*------------------------------------------------------------*/ |
| 36 | /*--- Renamings of frequently-used global functions. ---*/ |
| 37 | /*------------------------------------------------------------*/ |
| 38 | |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 39 | #define dis VG_(print_codegen) |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 40 | |
| 41 | /*------------------------------------------------------------*/ |
| 42 | /*--- Instruction emission -- turning final uinstrs back ---*/ |
| 43 | /*--- into x86 code. ---*/ |
| 44 | /*------------------------------------------------------------*/ |
| 45 | |
| 46 | /* [2001-07-08 This comment is now somewhat out of date.] |
| 47 | |
| 48 | This is straightforward but for one thing: to facilitate generating |
| 49 | code in a single pass, we generate position-independent code. To |
| 50 | do this, calls and jmps to fixed addresses must specify the address |
| 51 | by first loading it into a register, and jump to/call that |
| 52 | register. Fortunately, the only jump to a literal is the jump back |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 53 | to vg_dispatch, and only %eax is live then, conveniently. UCode |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 54 | call insns may only have a register as target anyway, so there's no |
| 55 | need to do anything fancy for them. |
| 56 | |
| 57 | The emit_* routines constitute the lowest level of instruction |
| 58 | emission. They simply emit the sequence of bytes corresponding to |
| 59 | the relevant instruction, with no further ado. In particular there |
| 60 | is no checking about whether uses of byte registers makes sense, |
| 61 | nor whether shift insns have their first operand in %cl, etc. |
| 62 | |
| 63 | These issues are taken care of by the level above, the synth_* |
| 64 | routines. These detect impossible operand combinations and turn |
| 65 | them into sequences of legal instructions. Finally, emitUInstr is |
| 66 | phrased in terms of the synth_* abstraction layer. */ |
| 67 | |
| 68 | static UChar* emitted_code; |
| 69 | static Int emitted_code_used; |
| 70 | static Int emitted_code_size; |
| 71 | |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 72 | /* Statistics about C functions called from generated code. */ |
| 73 | static UInt ccalls = 0; |
| 74 | static UInt ccall_reg_saves = 0; |
| 75 | static UInt ccall_args = 0; |
| 76 | static UInt ccall_arg_setup_instrs = 0; |
| 77 | static UInt ccall_stack_clears = 0; |
| 78 | static UInt ccall_retvals = 0; |
| 79 | static UInt ccall_retval_movs = 0; |
| 80 | |
| 81 | /* Statistics about frequency of each UInstr */ |
| 82 | typedef |
| 83 | struct { |
| 84 | UInt counts; |
| 85 | UInt size; |
| 86 | } Histogram; |
| 87 | |
| 88 | /* Automatically zeroed because it's static. */ |
| 89 | static Histogram histogram[100]; |
| 90 | |
| 91 | void VG_(print_ccall_stats)(void) |
| 92 | { |
| 93 | VG_(message)(Vg_DebugMsg, |
| 94 | " ccalls: %u C calls, %u%% saves+restores avoided" |
| 95 | " (%d bytes)", |
| 96 | ccalls, |
| 97 | 100-(UInt)(ccall_reg_saves/(double)(ccalls*3)*100), |
| 98 | ((ccalls*3) - ccall_reg_saves)*2); |
| 99 | VG_(message)(Vg_DebugMsg, |
| 100 | " %u args, avg 0.%d setup instrs each (%d bytes)", |
| 101 | ccall_args, |
| 102 | (UInt)(ccall_arg_setup_instrs/(double)ccall_args*100), |
| 103 | (ccall_args - ccall_arg_setup_instrs)*2); |
| 104 | VG_(message)(Vg_DebugMsg, |
| 105 | " %d%% clear the stack (%d bytes)", |
| 106 | (UInt)(ccall_stack_clears/(double)ccalls*100), |
| 107 | (ccalls - ccall_stack_clears)*3); |
| 108 | VG_(message)(Vg_DebugMsg, |
| 109 | " %u retvals, %u%% of reg-reg movs avoided (%d bytes)", |
| 110 | ccall_retvals, |
| 111 | ( ccall_retvals == 0 |
| 112 | ? 100 |
| 113 | : 100-(UInt)(ccall_retval_movs / |
| 114 | (double)ccall_retvals*100)), |
| 115 | (ccall_retvals-ccall_retval_movs)*2); |
| 116 | } |
| 117 | |
| 118 | void VG_(print_UInstr_histogram)(void) |
| 119 | { |
| 120 | Int i, j; |
| 121 | UInt total_counts = 0; |
| 122 | UInt total_size = 0; |
| 123 | |
| 124 | for (i = 0; i < 100; i++) { |
| 125 | total_counts += histogram[i].counts; |
| 126 | total_size += histogram[i].size; |
| 127 | } |
| 128 | |
| 129 | VG_(printf)("-- UInstr frequencies -----------\n"); |
| 130 | for (i = 0; i < 100; i++) { |
| 131 | if (0 != histogram[i].counts) { |
| 132 | |
| 133 | UInt count_pc = |
| 134 | (UInt)(histogram[i].counts/(double)total_counts*100 + 0.5); |
| 135 | UInt size_pc = |
| 136 | (UInt)(histogram[i].size /(double)total_size *100 + 0.5); |
| 137 | UInt avg_size = |
| 138 | (UInt)(histogram[i].size / (double)histogram[i].counts + 0.5); |
| 139 | |
| 140 | VG_(printf)("%-7s:%8u (%2u%%), avg %2dB (%2u%%) |", |
njn | 4ba5a79 | 2002-09-30 10:23:54 +0000 | [diff] [blame] | 141 | VG_(name_UOpcode)(True, i), |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 142 | histogram[i].counts, count_pc, |
| 143 | avg_size, size_pc); |
| 144 | |
| 145 | for (j = 0; j < size_pc; j++) VG_(printf)("O"); |
| 146 | VG_(printf)("\n"); |
| 147 | |
| 148 | } else { |
| 149 | vg_assert(0 == histogram[i].size); |
| 150 | } |
| 151 | } |
| 152 | |
| 153 | VG_(printf)("total UInstrs %u, total size %u\n", total_counts, total_size); |
| 154 | } |
| 155 | |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 156 | static void expandEmittedCode ( void ) |
| 157 | { |
| 158 | Int i; |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 159 | UChar *tmp = VG_(arena_malloc)(VG_AR_JITTER, 2 * emitted_code_size); |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 160 | /* VG_(printf)("expand to %d\n", 2 * emitted_code_size); */ |
| 161 | for (i = 0; i < emitted_code_size; i++) |
| 162 | tmp[i] = emitted_code[i]; |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 163 | VG_(arena_free)(VG_AR_JITTER, emitted_code); |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 164 | emitted_code = tmp; |
| 165 | emitted_code_size *= 2; |
| 166 | } |
| 167 | |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 168 | /* Local calls will be inlined, cross-module ones not */ |
| 169 | __inline__ void VG_(emitB) ( UInt b ) |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 170 | { |
| 171 | if (dis) { |
| 172 | if (b < 16) VG_(printf)("0%x ", b); else VG_(printf)("%2x ", b); |
| 173 | } |
| 174 | if (emitted_code_used == emitted_code_size) |
| 175 | expandEmittedCode(); |
| 176 | |
| 177 | emitted_code[emitted_code_used] = (UChar)b; |
| 178 | emitted_code_used++; |
| 179 | } |
| 180 | |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 181 | __inline__ void VG_(emitW) ( UInt l ) |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 182 | { |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 183 | VG_(emitB) ( (l) & 0x000000FF ); |
| 184 | VG_(emitB) ( (l >> 8) & 0x000000FF ); |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 185 | } |
| 186 | |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 187 | __inline__ void VG_(emitL) ( UInt l ) |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 188 | { |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 189 | VG_(emitB) ( (l) & 0x000000FF ); |
| 190 | VG_(emitB) ( (l >> 8) & 0x000000FF ); |
| 191 | VG_(emitB) ( (l >> 16) & 0x000000FF ); |
| 192 | VG_(emitB) ( (l >> 24) & 0x000000FF ); |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 193 | } |
| 194 | |
njn | 4ba5a79 | 2002-09-30 10:23:54 +0000 | [diff] [blame] | 195 | __inline__ void VG_(new_emit) ( void ) |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 196 | { |
| 197 | if (dis) |
| 198 | VG_(printf)("\t %4d: ", emitted_code_used ); |
| 199 | } |
| 200 | |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 201 | |
| 202 | /*----------------------------------------------------*/ |
| 203 | /*--- Addressing modes ---*/ |
| 204 | /*----------------------------------------------------*/ |
| 205 | |
| 206 | static __inline__ UChar mkModRegRM ( UChar mod, UChar reg, UChar regmem ) |
| 207 | { |
| 208 | return ((mod & 3) << 6) | ((reg & 7) << 3) | (regmem & 7); |
| 209 | } |
| 210 | |
| 211 | static __inline__ UChar mkSIB ( Int scale, Int regindex, Int regbase ) |
| 212 | { |
| 213 | Int shift; |
| 214 | switch (scale) { |
| 215 | case 1: shift = 0; break; |
| 216 | case 2: shift = 1; break; |
| 217 | case 4: shift = 2; break; |
| 218 | case 8: shift = 3; break; |
njn | e427a66 | 2002-10-02 11:08:25 +0000 | [diff] [blame] | 219 | default: VG_(core_panic)( "mkSIB" ); |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 220 | } |
| 221 | return ((shift & 3) << 6) | ((regindex & 7) << 3) | (regbase & 7); |
| 222 | } |
| 223 | |
| 224 | static __inline__ void emit_amode_litmem_reg ( Addr addr, Int reg ) |
| 225 | { |
| 226 | /* ($ADDR), reg */ |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 227 | VG_(emitB) ( mkModRegRM(0, reg, 5) ); |
| 228 | VG_(emitL) ( addr ); |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 229 | } |
| 230 | |
| 231 | static __inline__ void emit_amode_regmem_reg ( Int regmem, Int reg ) |
| 232 | { |
| 233 | /* (regmem), reg */ |
| 234 | if (regmem == R_ESP) |
njn | e427a66 | 2002-10-02 11:08:25 +0000 | [diff] [blame] | 235 | VG_(core_panic)("emit_amode_regmem_reg"); |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 236 | if (regmem == R_EBP) { |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 237 | VG_(emitB) ( mkModRegRM(1, reg, 5) ); |
| 238 | VG_(emitB) ( 0x00 ); |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 239 | } else { |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 240 | VG_(emitB)( mkModRegRM(0, reg, regmem) ); |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 241 | } |
| 242 | } |
| 243 | |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 244 | void VG_(emit_amode_offregmem_reg) ( Int off, Int regmem, Int reg ) |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 245 | { |
| 246 | if (regmem == R_ESP) |
njn | e427a66 | 2002-10-02 11:08:25 +0000 | [diff] [blame] | 247 | VG_(core_panic)("emit_amode_offregmem_reg(ESP)"); |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 248 | if (off < -128 || off > 127) { |
| 249 | /* Use a large offset */ |
| 250 | /* d32(regmem), reg */ |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 251 | VG_(emitB) ( mkModRegRM(2, reg, regmem) ); |
| 252 | VG_(emitL) ( off ); |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 253 | } else { |
| 254 | /* d8(regmem), reg */ |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 255 | VG_(emitB) ( mkModRegRM(1, reg, regmem) ); |
| 256 | VG_(emitB) ( off & 0xFF ); |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 257 | } |
| 258 | } |
| 259 | |
| 260 | static __inline__ void emit_amode_sib_reg ( Int off, Int scale, Int regbase, |
| 261 | Int regindex, Int reg ) |
| 262 | { |
| 263 | if (regindex == R_ESP) |
njn | e427a66 | 2002-10-02 11:08:25 +0000 | [diff] [blame] | 264 | VG_(core_panic)("emit_amode_sib_reg(ESP)"); |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 265 | if (off < -128 || off > 127) { |
| 266 | /* Use a 32-bit offset */ |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 267 | VG_(emitB) ( mkModRegRM(2, reg, 4) ); /* SIB with 32-bit displacement */ |
| 268 | VG_(emitB) ( mkSIB( scale, regindex, regbase ) ); |
| 269 | VG_(emitL) ( off ); |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 270 | } else { |
| 271 | /* Use an 8-bit offset */ |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 272 | VG_(emitB) ( mkModRegRM(1, reg, 4) ); /* SIB with 8-bit displacement */ |
| 273 | VG_(emitB) ( mkSIB( scale, regindex, regbase ) ); |
| 274 | VG_(emitB) ( off & 0xFF ); |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 275 | } |
| 276 | } |
| 277 | |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 278 | void VG_(emit_amode_ereg_greg) ( Int e_reg, Int g_reg ) |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 279 | { |
| 280 | /* other_reg, reg */ |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 281 | VG_(emitB) ( mkModRegRM(3, g_reg, e_reg) ); |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 282 | } |
| 283 | |
| 284 | static __inline__ void emit_amode_greg_ereg ( Int g_reg, Int e_reg ) |
| 285 | { |
| 286 | /* other_reg, reg */ |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 287 | VG_(emitB) ( mkModRegRM(3, g_reg, e_reg) ); |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 288 | } |
| 289 | |
| 290 | |
| 291 | /*----------------------------------------------------*/ |
| 292 | /*--- Opcode translation ---*/ |
| 293 | /*----------------------------------------------------*/ |
| 294 | |
| 295 | static __inline__ Int mkGrp1opcode ( Opcode opc ) |
| 296 | { |
| 297 | switch (opc) { |
| 298 | case ADD: return 0; |
| 299 | case OR: return 1; |
| 300 | case ADC: return 2; |
| 301 | case SBB: return 3; |
| 302 | case AND: return 4; |
| 303 | case SUB: return 5; |
| 304 | case XOR: return 6; |
njn | e427a66 | 2002-10-02 11:08:25 +0000 | [diff] [blame] | 305 | default: VG_(core_panic)("mkGrp1opcode"); |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 306 | } |
| 307 | } |
| 308 | |
| 309 | static __inline__ Int mkGrp2opcode ( Opcode opc ) |
| 310 | { |
| 311 | switch (opc) { |
| 312 | case ROL: return 0; |
| 313 | case ROR: return 1; |
| 314 | case RCL: return 2; |
| 315 | case RCR: return 3; |
| 316 | case SHL: return 4; |
| 317 | case SHR: return 5; |
| 318 | case SAR: return 7; |
njn | e427a66 | 2002-10-02 11:08:25 +0000 | [diff] [blame] | 319 | default: VG_(core_panic)("mkGrp2opcode"); |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 320 | } |
| 321 | } |
| 322 | |
| 323 | static __inline__ Int mkGrp3opcode ( Opcode opc ) |
| 324 | { |
| 325 | switch (opc) { |
| 326 | case NOT: return 2; |
| 327 | case NEG: return 3; |
njn | e427a66 | 2002-10-02 11:08:25 +0000 | [diff] [blame] | 328 | default: VG_(core_panic)("mkGrp3opcode"); |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 329 | } |
| 330 | } |
| 331 | |
| 332 | static __inline__ Int mkGrp4opcode ( Opcode opc ) |
| 333 | { |
| 334 | switch (opc) { |
| 335 | case INC: return 0; |
| 336 | case DEC: return 1; |
njn | e427a66 | 2002-10-02 11:08:25 +0000 | [diff] [blame] | 337 | default: VG_(core_panic)("mkGrp4opcode"); |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 338 | } |
| 339 | } |
| 340 | |
| 341 | static __inline__ Int mkGrp5opcode ( Opcode opc ) |
| 342 | { |
| 343 | switch (opc) { |
| 344 | case CALLM: return 2; |
| 345 | case JMP: return 4; |
njn | e427a66 | 2002-10-02 11:08:25 +0000 | [diff] [blame] | 346 | default: VG_(core_panic)("mkGrp5opcode"); |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 347 | } |
| 348 | } |
| 349 | |
| 350 | static __inline__ UChar mkPrimaryOpcode ( Opcode opc ) |
| 351 | { |
| 352 | switch (opc) { |
| 353 | case ADD: return 0x00; |
| 354 | case ADC: return 0x10; |
| 355 | case AND: return 0x20; |
| 356 | case XOR: return 0x30; |
| 357 | case OR: return 0x08; |
| 358 | case SBB: return 0x18; |
| 359 | case SUB: return 0x28; |
njn | e427a66 | 2002-10-02 11:08:25 +0000 | [diff] [blame] | 360 | default: VG_(core_panic)("mkPrimaryOpcode"); |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 361 | } |
| 362 | } |
| 363 | |
| 364 | /*----------------------------------------------------*/ |
| 365 | /*--- v-size (4, or 2 with OSO) insn emitters ---*/ |
| 366 | /*----------------------------------------------------*/ |
| 367 | |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 368 | void VG_(emit_movv_offregmem_reg) ( Int sz, Int off, Int areg, Int reg ) |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 369 | { |
njn | 4ba5a79 | 2002-09-30 10:23:54 +0000 | [diff] [blame] | 370 | VG_(new_emit)(); |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 371 | if (sz == 2) VG_(emitB) ( 0x66 ); |
| 372 | VG_(emitB) ( 0x8B ); /* MOV Ev, Gv */ |
| 373 | VG_(emit_amode_offregmem_reg) ( off, areg, reg ); |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 374 | if (dis) |
| 375 | VG_(printf)( "\n\t\tmov%c\t0x%x(%s), %s\n", |
| 376 | nameISize(sz), off, nameIReg(4,areg), nameIReg(sz,reg)); |
| 377 | } |
| 378 | |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 379 | void VG_(emit_movv_reg_offregmem) ( Int sz, Int reg, Int off, Int areg ) |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 380 | { |
njn | 4ba5a79 | 2002-09-30 10:23:54 +0000 | [diff] [blame] | 381 | VG_(new_emit)(); |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 382 | if (sz == 2) VG_(emitB) ( 0x66 ); |
| 383 | VG_(emitB) ( 0x89 ); /* MOV Gv, Ev */ |
| 384 | VG_(emit_amode_offregmem_reg) ( off, areg, reg ); |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 385 | if (dis) |
| 386 | VG_(printf)( "\n\t\tmov%c\t%s, 0x%x(%s)\n", |
| 387 | nameISize(sz), nameIReg(sz,reg), off, nameIReg(4,areg)); |
| 388 | } |
| 389 | |
| 390 | static void emit_movv_regmem_reg ( Int sz, Int reg1, Int reg2 ) |
| 391 | { |
njn | 4ba5a79 | 2002-09-30 10:23:54 +0000 | [diff] [blame] | 392 | VG_(new_emit)(); |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 393 | if (sz == 2) VG_(emitB) ( 0x66 ); |
| 394 | VG_(emitB) ( 0x8B ); /* MOV Ev, Gv */ |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 395 | emit_amode_regmem_reg ( reg1, reg2 ); |
| 396 | if (dis) |
| 397 | VG_(printf)( "\n\t\tmov%c\t(%s), %s\n", |
| 398 | nameISize(sz), nameIReg(4,reg1), nameIReg(sz,reg2)); |
| 399 | } |
| 400 | |
| 401 | static void emit_movv_reg_regmem ( Int sz, Int reg1, Int reg2 ) |
| 402 | { |
njn | 4ba5a79 | 2002-09-30 10:23:54 +0000 | [diff] [blame] | 403 | VG_(new_emit)(); |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 404 | if (sz == 2) VG_(emitB) ( 0x66 ); |
| 405 | VG_(emitB) ( 0x89 ); /* MOV Gv, Ev */ |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 406 | emit_amode_regmem_reg ( reg2, reg1 ); |
| 407 | if (dis) |
| 408 | VG_(printf)( "\n\t\tmov%c\t%s, (%s)\n", |
| 409 | nameISize(sz), nameIReg(sz,reg1), nameIReg(4,reg2)); |
| 410 | } |
| 411 | |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 412 | void VG_(emit_movv_reg_reg) ( Int sz, Int reg1, Int reg2 ) |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 413 | { |
njn | 4ba5a79 | 2002-09-30 10:23:54 +0000 | [diff] [blame] | 414 | VG_(new_emit)(); |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 415 | if (sz == 2) VG_(emitB) ( 0x66 ); |
| 416 | VG_(emitB) ( 0x89 ); /* MOV Gv, Ev */ |
| 417 | VG_(emit_amode_ereg_greg) ( reg2, reg1 ); |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 418 | if (dis) |
| 419 | VG_(printf)( "\n\t\tmov%c\t%s, %s\n", |
| 420 | nameISize(sz), nameIReg(sz,reg1), nameIReg(sz,reg2)); |
| 421 | } |
| 422 | |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 423 | void VG_(emit_nonshiftopv_lit_reg) ( Int sz, Opcode opc, UInt lit, Int reg ) |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 424 | { |
njn | 4ba5a79 | 2002-09-30 10:23:54 +0000 | [diff] [blame] | 425 | VG_(new_emit)(); |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 426 | if (sz == 2) VG_(emitB) ( 0x66 ); |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 427 | if (lit == VG_(extend_s_8to32)(lit & 0x000000FF)) { |
| 428 | /* short form OK */ |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 429 | VG_(emitB) ( 0x83 ); /* Grp1 Ib,Ev */ |
| 430 | VG_(emit_amode_ereg_greg) ( reg, mkGrp1opcode(opc) ); |
| 431 | VG_(emitB) ( lit & 0x000000FF ); |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 432 | } else { |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 433 | VG_(emitB) ( 0x81 ); /* Grp1 Iv,Ev */ |
| 434 | VG_(emit_amode_ereg_greg) ( reg, mkGrp1opcode(opc) ); |
| 435 | if (sz == 2) VG_(emitW) ( lit ); else VG_(emitL) ( lit ); |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 436 | } |
| 437 | if (dis) |
| 438 | VG_(printf)( "\n\t\t%s%c\t$0x%x, %s\n", |
njn | 4ba5a79 | 2002-09-30 10:23:54 +0000 | [diff] [blame] | 439 | VG_(name_UOpcode)(False,opc), nameISize(sz), |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 440 | lit, nameIReg(sz,reg)); |
| 441 | } |
| 442 | |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 443 | void VG_(emit_shiftopv_lit_reg) ( Int sz, Opcode opc, UInt lit, Int reg ) |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 444 | { |
njn | 4ba5a79 | 2002-09-30 10:23:54 +0000 | [diff] [blame] | 445 | VG_(new_emit)(); |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 446 | if (sz == 2) VG_(emitB) ( 0x66 ); |
| 447 | VG_(emitB) ( 0xC1 ); /* Grp2 Ib,Ev */ |
| 448 | VG_(emit_amode_ereg_greg) ( reg, mkGrp2opcode(opc) ); |
| 449 | VG_(emitB) ( lit ); |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 450 | if (dis) |
| 451 | VG_(printf)( "\n\t\t%s%c\t$%d, %s\n", |
njn | 4ba5a79 | 2002-09-30 10:23:54 +0000 | [diff] [blame] | 452 | VG_(name_UOpcode)(False,opc), nameISize(sz), |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 453 | lit, nameIReg(sz,reg)); |
| 454 | } |
| 455 | |
| 456 | static void emit_shiftopv_cl_stack0 ( Int sz, Opcode opc ) |
| 457 | { |
njn | 4ba5a79 | 2002-09-30 10:23:54 +0000 | [diff] [blame] | 458 | VG_(new_emit)(); |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 459 | if (sz == 2) VG_(emitB) ( 0x66 ); |
| 460 | VG_(emitB) ( 0xD3 ); /* Grp2 CL,Ev */ |
| 461 | VG_(emitB) ( mkModRegRM ( 1, mkGrp2opcode(opc), 4 ) ); |
| 462 | VG_(emitB) ( 0x24 ); /* a SIB, I think `d8(%esp)' */ |
| 463 | VG_(emitB) ( 0x00 ); /* the d8 displacement */ |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 464 | if (dis) |
| 465 | VG_(printf)("\n\t\t%s%c %%cl, 0(%%esp)\n", |
njn | 4ba5a79 | 2002-09-30 10:23:54 +0000 | [diff] [blame] | 466 | VG_(name_UOpcode)(False,opc), nameISize(sz) ); |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 467 | } |
| 468 | |
| 469 | static void emit_shiftopb_cl_stack0 ( Opcode opc ) |
| 470 | { |
njn | 4ba5a79 | 2002-09-30 10:23:54 +0000 | [diff] [blame] | 471 | VG_(new_emit)(); |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 472 | VG_(emitB) ( 0xD2 ); /* Grp2 CL,Eb */ |
| 473 | VG_(emitB) ( mkModRegRM ( 1, mkGrp2opcode(opc), 4 ) ); |
| 474 | VG_(emitB) ( 0x24 ); /* a SIB, I think `d8(%esp)' */ |
| 475 | VG_(emitB) ( 0x00 ); /* the d8 displacement */ |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 476 | if (dis) |
| 477 | VG_(printf)("\n\t\t%s%c %%cl, 0(%%esp)\n", |
njn | 4ba5a79 | 2002-09-30 10:23:54 +0000 | [diff] [blame] | 478 | VG_(name_UOpcode)(False,opc), nameISize(1) ); |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 479 | } |
| 480 | |
| 481 | static void emit_nonshiftopv_offregmem_reg ( Int sz, Opcode opc, |
| 482 | Int off, Int areg, Int reg ) |
| 483 | { |
njn | 4ba5a79 | 2002-09-30 10:23:54 +0000 | [diff] [blame] | 484 | VG_(new_emit)(); |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 485 | if (sz == 2) VG_(emitB) ( 0x66 ); |
| 486 | VG_(emitB) ( 3 + mkPrimaryOpcode(opc) ); /* op Ev, Gv */ |
| 487 | VG_(emit_amode_offregmem_reg) ( off, areg, reg ); |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 488 | if (dis) |
| 489 | VG_(printf)( "\n\t\t%s%c\t0x%x(%s), %s\n", |
njn | 4ba5a79 | 2002-09-30 10:23:54 +0000 | [diff] [blame] | 490 | VG_(name_UOpcode)(False,opc), nameISize(sz), |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 491 | off, nameIReg(4,areg), nameIReg(sz,reg)); |
| 492 | } |
| 493 | |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 494 | void VG_(emit_nonshiftopv_reg_reg) ( Int sz, Opcode opc, |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 495 | Int reg1, Int reg2 ) |
| 496 | { |
njn | 4ba5a79 | 2002-09-30 10:23:54 +0000 | [diff] [blame] | 497 | VG_(new_emit)(); |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 498 | if (sz == 2) VG_(emitB) ( 0x66 ); |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 499 | # if 0 |
| 500 | /* Perfectly correct, but the GNU assembler uses the other form. |
| 501 | Therefore we too use the other form, to aid verification. */ |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 502 | VG_(emitB) ( 3 + mkPrimaryOpcode(opc) ); /* op Ev, Gv */ |
| 503 | VG_(emit_amode_ereg_greg) ( reg1, reg2 ); |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 504 | # else |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 505 | VG_(emitB) ( 1 + mkPrimaryOpcode(opc) ); /* op Gv, Ev */ |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 506 | emit_amode_greg_ereg ( reg1, reg2 ); |
| 507 | # endif |
| 508 | if (dis) |
| 509 | VG_(printf)( "\n\t\t%s%c\t%s, %s\n", |
njn | 4ba5a79 | 2002-09-30 10:23:54 +0000 | [diff] [blame] | 510 | VG_(name_UOpcode)(False,opc), nameISize(sz), |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 511 | nameIReg(sz,reg1), nameIReg(sz,reg2)); |
| 512 | } |
| 513 | |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 514 | void VG_(emit_movv_lit_reg) ( Int sz, UInt lit, Int reg ) |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 515 | { |
| 516 | if (lit == 0) { |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 517 | VG_(emit_nonshiftopv_reg_reg) ( sz, XOR, reg, reg ); |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 518 | return; |
| 519 | } |
njn | 4ba5a79 | 2002-09-30 10:23:54 +0000 | [diff] [blame] | 520 | VG_(new_emit)(); |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 521 | if (sz == 2) VG_(emitB) ( 0x66 ); |
| 522 | VG_(emitB) ( 0xB8+reg ); /* MOV imm, Gv */ |
| 523 | if (sz == 2) VG_(emitW) ( lit ); else VG_(emitL) ( lit ); |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 524 | if (dis) |
| 525 | VG_(printf)( "\n\t\tmov%c\t$0x%x, %s\n", |
| 526 | nameISize(sz), lit, nameIReg(sz,reg)); |
| 527 | } |
| 528 | |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 529 | void VG_(emit_unaryopv_reg) ( Int sz, Opcode opc, Int reg ) |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 530 | { |
njn | 4ba5a79 | 2002-09-30 10:23:54 +0000 | [diff] [blame] | 531 | VG_(new_emit)(); |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 532 | if (sz == 2) VG_(emitB) ( 0x66 ); |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 533 | switch (opc) { |
| 534 | case NEG: |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 535 | VG_(emitB) ( 0xF7 ); |
| 536 | VG_(emit_amode_ereg_greg) ( reg, mkGrp3opcode(NEG) ); |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 537 | if (dis) |
| 538 | VG_(printf)( "\n\t\tneg%c\t%s\n", |
| 539 | nameISize(sz), nameIReg(sz,reg)); |
| 540 | break; |
| 541 | case NOT: |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 542 | VG_(emitB) ( 0xF7 ); |
| 543 | VG_(emit_amode_ereg_greg) ( reg, mkGrp3opcode(NOT) ); |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 544 | if (dis) |
| 545 | VG_(printf)( "\n\t\tnot%c\t%s\n", |
| 546 | nameISize(sz), nameIReg(sz,reg)); |
| 547 | break; |
| 548 | case DEC: |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 549 | VG_(emitB) ( 0x48 + reg ); |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 550 | if (dis) |
| 551 | VG_(printf)( "\n\t\tdec%c\t%s\n", |
| 552 | nameISize(sz), nameIReg(sz,reg)); |
| 553 | break; |
| 554 | case INC: |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 555 | VG_(emitB) ( 0x40 + reg ); |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 556 | if (dis) |
| 557 | VG_(printf)( "\n\t\tinc%c\t%s\n", |
| 558 | nameISize(sz), nameIReg(sz,reg)); |
| 559 | break; |
| 560 | default: |
njn | e427a66 | 2002-10-02 11:08:25 +0000 | [diff] [blame] | 561 | VG_(core_panic)("VG_(emit_unaryopv_reg)"); |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 562 | } |
| 563 | } |
| 564 | |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 565 | void VG_(emit_pushv_reg) ( Int sz, Int reg ) |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 566 | { |
njn | 4ba5a79 | 2002-09-30 10:23:54 +0000 | [diff] [blame] | 567 | VG_(new_emit)(); |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 568 | if (sz == 2) { |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 569 | VG_(emitB) ( 0x66 ); |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 570 | } else { |
| 571 | vg_assert(sz == 4); |
| 572 | } |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 573 | VG_(emitB) ( 0x50 + reg ); |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 574 | if (dis) |
| 575 | VG_(printf)("\n\t\tpush%c %s\n", nameISize(sz), nameIReg(sz,reg)); |
| 576 | } |
| 577 | |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 578 | void VG_(emit_popv_reg) ( Int sz, Int reg ) |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 579 | { |
njn | 4ba5a79 | 2002-09-30 10:23:54 +0000 | [diff] [blame] | 580 | VG_(new_emit)(); |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 581 | if (sz == 2) { |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 582 | VG_(emitB) ( 0x66 ); |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 583 | } else { |
| 584 | vg_assert(sz == 4); |
| 585 | } |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 586 | VG_(emitB) ( 0x58 + reg ); |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 587 | if (dis) |
| 588 | VG_(printf)("\n\t\tpop%c %s\n", nameISize(sz), nameIReg(sz,reg)); |
| 589 | } |
| 590 | |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 591 | void VG_(emit_pushl_lit32) ( UInt int32 ) |
| 592 | { |
njn | 4ba5a79 | 2002-09-30 10:23:54 +0000 | [diff] [blame] | 593 | VG_(new_emit)(); |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 594 | VG_(emitB) ( 0x68 ); |
| 595 | VG_(emitL) ( int32 ); |
| 596 | if (dis) |
| 597 | VG_(printf)("\n\t\tpushl $0x%x\n", int32 ); |
| 598 | } |
| 599 | |
| 600 | void VG_(emit_pushl_lit8) ( Int lit8 ) |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 601 | { |
| 602 | vg_assert(lit8 >= -128 && lit8 < 128); |
njn | 4ba5a79 | 2002-09-30 10:23:54 +0000 | [diff] [blame] | 603 | VG_(new_emit)(); |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 604 | VG_(emitB) ( 0x6A ); |
| 605 | VG_(emitB) ( (UChar)((UInt)lit8) ); |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 606 | if (dis) |
| 607 | VG_(printf)("\n\t\tpushl $%d\n", lit8 ); |
| 608 | } |
| 609 | |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 610 | void VG_(emit_cmpl_zero_reg) ( Int reg ) |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 611 | { |
njn | 4ba5a79 | 2002-09-30 10:23:54 +0000 | [diff] [blame] | 612 | VG_(new_emit)(); |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 613 | VG_(emitB) ( 0x83 ); |
| 614 | VG_(emit_amode_ereg_greg) ( reg, 7 /* Grp 3 opcode for CMP */ ); |
| 615 | VG_(emitB) ( 0x00 ); |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 616 | if (dis) |
| 617 | VG_(printf)("\n\t\tcmpl $0, %s\n", nameIReg(4,reg)); |
| 618 | } |
| 619 | |
| 620 | static void emit_swapl_reg_ECX ( Int reg ) |
| 621 | { |
njn | 4ba5a79 | 2002-09-30 10:23:54 +0000 | [diff] [blame] | 622 | VG_(new_emit)(); |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 623 | VG_(emitB) ( 0x87 ); /* XCHG Gv,Ev */ |
| 624 | VG_(emit_amode_ereg_greg) ( reg, R_ECX ); |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 625 | if (dis) |
| 626 | VG_(printf)("\n\t\txchgl %%ecx, %s\n", nameIReg(4,reg)); |
| 627 | } |
| 628 | |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 629 | void VG_(emit_swapl_reg_EAX) ( Int reg ) |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 630 | { |
njn | 4ba5a79 | 2002-09-30 10:23:54 +0000 | [diff] [blame] | 631 | VG_(new_emit)(); |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 632 | VG_(emitB) ( 0x90 + reg ); /* XCHG Gv,eAX */ |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 633 | if (dis) |
| 634 | VG_(printf)("\n\t\txchgl %%eax, %s\n", nameIReg(4,reg)); |
| 635 | } |
| 636 | |
| 637 | static void emit_swapl_reg_reg ( Int reg1, Int reg2 ) |
| 638 | { |
njn | 4ba5a79 | 2002-09-30 10:23:54 +0000 | [diff] [blame] | 639 | VG_(new_emit)(); |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 640 | VG_(emitB) ( 0x87 ); /* XCHG Gv,Ev */ |
| 641 | VG_(emit_amode_ereg_greg) ( reg1, reg2 ); |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 642 | if (dis) |
| 643 | VG_(printf)("\n\t\txchgl %s, %s\n", nameIReg(4,reg1), |
| 644 | nameIReg(4,reg2)); |
| 645 | } |
| 646 | |
| 647 | static void emit_bswapl_reg ( Int reg ) |
| 648 | { |
njn | 4ba5a79 | 2002-09-30 10:23:54 +0000 | [diff] [blame] | 649 | VG_(new_emit)(); |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 650 | VG_(emitB) ( 0x0F ); |
| 651 | VG_(emitB) ( 0xC8 + reg ); /* BSWAP r32 */ |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 652 | if (dis) |
| 653 | VG_(printf)("\n\t\tbswapl %s\n", nameIReg(4,reg)); |
| 654 | } |
| 655 | |
| 656 | static void emit_movl_reg_reg ( Int regs, Int regd ) |
| 657 | { |
njn | 4ba5a79 | 2002-09-30 10:23:54 +0000 | [diff] [blame] | 658 | VG_(new_emit)(); |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 659 | VG_(emitB) ( 0x89 ); /* MOV Gv,Ev */ |
| 660 | VG_(emit_amode_ereg_greg) ( regd, regs ); |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 661 | if (dis) |
| 662 | VG_(printf)("\n\t\tmovl %s, %s\n", nameIReg(4,regs), nameIReg(4,regd)); |
| 663 | } |
| 664 | |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 665 | void VG_(emit_movv_lit_offregmem) ( Int sz, UInt lit, Int off, Int memreg ) |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 666 | { |
njn | 4ba5a79 | 2002-09-30 10:23:54 +0000 | [diff] [blame] | 667 | VG_(new_emit)(); |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 668 | if (sz == 2) { |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 669 | VG_(emitB) ( 0x66 ); |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 670 | } else { |
| 671 | vg_assert(sz == 4); |
| 672 | } |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 673 | VG_(emitB) ( 0xC7 ); /* Grp11 Ev */ |
| 674 | VG_(emit_amode_offregmem_reg) ( off, memreg, 0 /* Grp11 subopcode for MOV */ ); |
| 675 | if (sz == 2) VG_(emitW) ( lit ); else VG_(emitL) ( lit ); |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 676 | if (dis) |
| 677 | VG_(printf)( "\n\t\tmov%c\t$0x%x, 0x%x(%s)\n", |
| 678 | nameISize(sz), lit, off, nameIReg(4,memreg) ); |
| 679 | } |
| 680 | |
| 681 | |
| 682 | /*----------------------------------------------------*/ |
| 683 | /*--- b-size (1 byte) instruction emitters ---*/ |
| 684 | /*----------------------------------------------------*/ |
| 685 | |
| 686 | /* There is some doubt as to whether C6 (Grp 11) is in the |
| 687 | 486 insn set. ToDo: investigate. */ |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 688 | void VG_(emit_movb_lit_offregmem) ( UInt lit, Int off, Int memreg ) |
| 689 | { |
njn | 4ba5a79 | 2002-09-30 10:23:54 +0000 | [diff] [blame] | 690 | VG_(new_emit)(); |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 691 | VG_(emitB) ( 0xC6 ); /* Grp11 Eb */ |
| 692 | VG_(emit_amode_offregmem_reg) ( off, memreg, 0 /* Grp11 subopcode for MOV */ ); |
| 693 | VG_(emitB) ( lit ); |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 694 | if (dis) |
| 695 | VG_(printf)( "\n\t\tmovb\t$0x%x, 0x%x(%s)\n", |
| 696 | lit, off, nameIReg(4,memreg) ); |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 697 | } |
| 698 | |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 699 | static void emit_nonshiftopb_offregmem_reg ( Opcode opc, |
| 700 | Int off, Int areg, Int reg ) |
| 701 | { |
njn | 4ba5a79 | 2002-09-30 10:23:54 +0000 | [diff] [blame] | 702 | VG_(new_emit)(); |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 703 | VG_(emitB) ( 2 + mkPrimaryOpcode(opc) ); /* op Eb, Gb */ |
| 704 | VG_(emit_amode_offregmem_reg) ( off, areg, reg ); |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 705 | if (dis) |
| 706 | VG_(printf)( "\n\t\t%sb\t0x%x(%s), %s\n", |
njn | 4ba5a79 | 2002-09-30 10:23:54 +0000 | [diff] [blame] | 707 | VG_(name_UOpcode)(False,opc), off, nameIReg(4,areg), |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 708 | nameIReg(1,reg)); |
| 709 | } |
| 710 | |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 711 | void VG_(emit_movb_reg_offregmem) ( Int reg, Int off, Int areg ) |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 712 | { |
| 713 | /* Could do better when reg == %al. */ |
njn | 4ba5a79 | 2002-09-30 10:23:54 +0000 | [diff] [blame] | 714 | VG_(new_emit)(); |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 715 | VG_(emitB) ( 0x88 ); /* MOV G1, E1 */ |
| 716 | VG_(emit_amode_offregmem_reg) ( off, areg, reg ); |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 717 | if (dis) |
| 718 | VG_(printf)( "\n\t\tmovb\t%s, 0x%x(%s)\n", |
| 719 | nameIReg(1,reg), off, nameIReg(4,areg)); |
| 720 | } |
| 721 | |
| 722 | static void emit_nonshiftopb_reg_reg ( Opcode opc, Int reg1, Int reg2 ) |
| 723 | { |
njn | 4ba5a79 | 2002-09-30 10:23:54 +0000 | [diff] [blame] | 724 | VG_(new_emit)(); |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 725 | VG_(emitB) ( 2 + mkPrimaryOpcode(opc) ); /* op Eb, Gb */ |
| 726 | VG_(emit_amode_ereg_greg) ( reg1, reg2 ); |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 727 | if (dis) |
| 728 | VG_(printf)( "\n\t\t%sb\t%s, %s\n", |
njn | 4ba5a79 | 2002-09-30 10:23:54 +0000 | [diff] [blame] | 729 | VG_(name_UOpcode)(False,opc), |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 730 | nameIReg(1,reg1), nameIReg(1,reg2)); |
| 731 | } |
| 732 | |
| 733 | static void emit_movb_reg_regmem ( Int reg1, Int reg2 ) |
| 734 | { |
njn | 4ba5a79 | 2002-09-30 10:23:54 +0000 | [diff] [blame] | 735 | VG_(new_emit)(); |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 736 | VG_(emitB) ( 0x88 ); /* MOV G1, E1 */ |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 737 | emit_amode_regmem_reg ( reg2, reg1 ); |
| 738 | if (dis) |
| 739 | VG_(printf)( "\n\t\tmovb\t%s, (%s)\n", nameIReg(1,reg1), |
| 740 | nameIReg(4,reg2)); |
| 741 | } |
| 742 | |
| 743 | static void emit_nonshiftopb_lit_reg ( Opcode opc, UInt lit, Int reg ) |
| 744 | { |
njn | 4ba5a79 | 2002-09-30 10:23:54 +0000 | [diff] [blame] | 745 | VG_(new_emit)(); |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 746 | VG_(emitB) ( 0x80 ); /* Grp1 Ib,Eb */ |
| 747 | VG_(emit_amode_ereg_greg) ( reg, mkGrp1opcode(opc) ); |
| 748 | VG_(emitB) ( lit & 0x000000FF ); |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 749 | if (dis) |
njn | 4ba5a79 | 2002-09-30 10:23:54 +0000 | [diff] [blame] | 750 | VG_(printf)( "\n\t\t%sb\t$0x%x, %s\n", VG_(name_UOpcode)(False,opc), |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 751 | lit, nameIReg(1,reg)); |
| 752 | } |
| 753 | |
| 754 | static void emit_shiftopb_lit_reg ( Opcode opc, UInt lit, Int reg ) |
| 755 | { |
njn | 4ba5a79 | 2002-09-30 10:23:54 +0000 | [diff] [blame] | 756 | VG_(new_emit)(); |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 757 | VG_(emitB) ( 0xC0 ); /* Grp2 Ib,Eb */ |
| 758 | VG_(emit_amode_ereg_greg) ( reg, mkGrp2opcode(opc) ); |
| 759 | VG_(emitB) ( lit ); |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 760 | if (dis) |
| 761 | VG_(printf)( "\n\t\t%sb\t$%d, %s\n", |
njn | 4ba5a79 | 2002-09-30 10:23:54 +0000 | [diff] [blame] | 762 | VG_(name_UOpcode)(False,opc), |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 763 | lit, nameIReg(1,reg)); |
| 764 | } |
| 765 | |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 766 | void VG_(emit_unaryopb_reg) ( Opcode opc, Int reg ) |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 767 | { |
njn | 4ba5a79 | 2002-09-30 10:23:54 +0000 | [diff] [blame] | 768 | VG_(new_emit)(); |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 769 | switch (opc) { |
| 770 | case INC: |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 771 | VG_(emitB) ( 0xFE ); |
| 772 | VG_(emit_amode_ereg_greg) ( reg, mkGrp4opcode(INC) ); |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 773 | if (dis) |
| 774 | VG_(printf)( "\n\t\tincb\t%s\n", nameIReg(1,reg)); |
| 775 | break; |
| 776 | case DEC: |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 777 | VG_(emitB) ( 0xFE ); |
| 778 | VG_(emit_amode_ereg_greg) ( reg, mkGrp4opcode(DEC) ); |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 779 | if (dis) |
| 780 | VG_(printf)( "\n\t\tdecb\t%s\n", nameIReg(1,reg)); |
| 781 | break; |
| 782 | case NOT: |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 783 | VG_(emitB) ( 0xF6 ); |
| 784 | VG_(emit_amode_ereg_greg) ( reg, mkGrp3opcode(NOT) ); |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 785 | if (dis) |
| 786 | VG_(printf)( "\n\t\tnotb\t%s\n", nameIReg(1,reg)); |
| 787 | break; |
| 788 | case NEG: |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 789 | VG_(emitB) ( 0xF6 ); |
| 790 | VG_(emit_amode_ereg_greg) ( reg, mkGrp3opcode(NEG) ); |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 791 | if (dis) |
| 792 | VG_(printf)( "\n\t\tnegb\t%s\n", nameIReg(1,reg)); |
| 793 | break; |
| 794 | default: |
njn | e427a66 | 2002-10-02 11:08:25 +0000 | [diff] [blame] | 795 | VG_(core_panic)("VG_(emit_unaryopb_reg)"); |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 796 | } |
| 797 | } |
| 798 | |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 799 | void VG_(emit_testb_lit_reg) ( UInt lit, Int reg ) |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 800 | { |
njn | 4ba5a79 | 2002-09-30 10:23:54 +0000 | [diff] [blame] | 801 | VG_(new_emit)(); |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 802 | VG_(emitB) ( 0xF6 ); /* Grp3 Eb */ |
| 803 | VG_(emit_amode_ereg_greg) ( reg, 0 /* Grp3 subopcode for TEST */ ); |
| 804 | VG_(emitB) ( lit ); |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 805 | if (dis) |
| 806 | VG_(printf)("\n\t\ttestb $0x%x, %s\n", lit, nameIReg(1,reg)); |
| 807 | } |
| 808 | |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 809 | /*----------------------------------------------------*/ |
| 810 | /*--- zero-extended load emitters ---*/ |
| 811 | /*----------------------------------------------------*/ |
| 812 | |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 813 | void VG_(emit_movzbl_offregmem_reg) ( Int off, Int regmem, Int reg ) |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 814 | { |
njn | 4ba5a79 | 2002-09-30 10:23:54 +0000 | [diff] [blame] | 815 | VG_(new_emit)(); |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 816 | VG_(emitB) ( 0x0F ); VG_(emitB) ( 0xB6 ); /* MOVZBL */ |
| 817 | VG_(emit_amode_offregmem_reg) ( off, regmem, reg ); |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 818 | if (dis) |
| 819 | VG_(printf)( "\n\t\tmovzbl\t0x%x(%s), %s\n", |
| 820 | off, nameIReg(4,regmem), nameIReg(4,reg)); |
| 821 | } |
| 822 | |
| 823 | static void emit_movzbl_regmem_reg ( Int reg1, Int reg2 ) |
| 824 | { |
njn | 4ba5a79 | 2002-09-30 10:23:54 +0000 | [diff] [blame] | 825 | VG_(new_emit)(); |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 826 | VG_(emitB) ( 0x0F ); VG_(emitB) ( 0xB6 ); /* MOVZBL */ |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 827 | emit_amode_regmem_reg ( reg1, reg2 ); |
| 828 | if (dis) |
| 829 | VG_(printf)( "\n\t\tmovzbl\t(%s), %s\n", nameIReg(4,reg1), |
| 830 | nameIReg(4,reg2)); |
| 831 | } |
| 832 | |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 833 | void VG_(emit_movzwl_offregmem_reg) ( Int off, Int areg, Int reg ) |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 834 | { |
njn | 4ba5a79 | 2002-09-30 10:23:54 +0000 | [diff] [blame] | 835 | VG_(new_emit)(); |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 836 | VG_(emitB) ( 0x0F ); VG_(emitB) ( 0xB7 ); /* MOVZWL */ |
| 837 | VG_(emit_amode_offregmem_reg) ( off, areg, reg ); |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 838 | if (dis) |
| 839 | VG_(printf)( "\n\t\tmovzwl\t0x%x(%s), %s\n", |
| 840 | off, nameIReg(4,areg), nameIReg(4,reg)); |
| 841 | } |
| 842 | |
| 843 | static void emit_movzwl_regmem_reg ( Int reg1, Int reg2 ) |
| 844 | { |
njn | 4ba5a79 | 2002-09-30 10:23:54 +0000 | [diff] [blame] | 845 | VG_(new_emit)(); |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 846 | VG_(emitB) ( 0x0F ); VG_(emitB) ( 0xB7 ); /* MOVZWL */ |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 847 | emit_amode_regmem_reg ( reg1, reg2 ); |
| 848 | if (dis) |
| 849 | VG_(printf)( "\n\t\tmovzwl\t(%s), %s\n", nameIReg(4,reg1), |
| 850 | nameIReg(4,reg2)); |
| 851 | } |
| 852 | |
| 853 | /*----------------------------------------------------*/ |
| 854 | /*--- FPU instruction emitters ---*/ |
| 855 | /*----------------------------------------------------*/ |
| 856 | |
| 857 | static void emit_get_fpu_state ( void ) |
| 858 | { |
| 859 | Int off = 4 * VGOFF_(m_fpustate); |
njn | 4ba5a79 | 2002-09-30 10:23:54 +0000 | [diff] [blame] | 860 | VG_(new_emit)(); |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 861 | VG_(emitB) ( 0xDD ); VG_(emitB) ( 0xA5 ); /* frstor d32(%ebp) */ |
| 862 | VG_(emitL) ( off ); |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 863 | if (dis) |
| 864 | VG_(printf)("\n\t\tfrstor\t%d(%%ebp)\n", off ); |
| 865 | } |
| 866 | |
| 867 | static void emit_put_fpu_state ( void ) |
| 868 | { |
| 869 | Int off = 4 * VGOFF_(m_fpustate); |
njn | 4ba5a79 | 2002-09-30 10:23:54 +0000 | [diff] [blame] | 870 | VG_(new_emit)(); |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 871 | VG_(emitB) ( 0xDD ); VG_(emitB) ( 0xB5 ); /* fnsave d32(%ebp) */ |
| 872 | VG_(emitL) ( off ); |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 873 | if (dis) |
| 874 | VG_(printf)("\n\t\tfnsave\t%d(%%ebp)\n", off ); |
| 875 | } |
| 876 | |
| 877 | static void emit_fpu_no_mem ( UChar first_byte, |
| 878 | UChar second_byte ) |
| 879 | { |
njn | 4ba5a79 | 2002-09-30 10:23:54 +0000 | [diff] [blame] | 880 | VG_(new_emit)(); |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 881 | VG_(emitB) ( first_byte ); |
| 882 | VG_(emitB) ( second_byte ); |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 883 | if (dis) |
| 884 | VG_(printf)("\n\t\tfpu-0x%x:0x%x\n", |
| 885 | (UInt)first_byte, (UInt)second_byte ); |
| 886 | } |
| 887 | |
| 888 | static void emit_fpu_regmem ( UChar first_byte, |
| 889 | UChar second_byte_masked, |
| 890 | Int reg ) |
| 891 | { |
njn | 4ba5a79 | 2002-09-30 10:23:54 +0000 | [diff] [blame] | 892 | VG_(new_emit)(); |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 893 | VG_(emitB) ( first_byte ); |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 894 | emit_amode_regmem_reg ( reg, second_byte_masked >> 3 ); |
| 895 | if (dis) |
| 896 | VG_(printf)("\n\t\tfpu-0x%x:0x%x-(%s)\n", |
| 897 | (UInt)first_byte, (UInt)second_byte_masked, |
| 898 | nameIReg(4,reg) ); |
| 899 | } |
| 900 | |
| 901 | |
| 902 | /*----------------------------------------------------*/ |
| 903 | /*--- misc instruction emitters ---*/ |
| 904 | /*----------------------------------------------------*/ |
| 905 | |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 906 | void VG_(emit_call_reg) ( Int reg ) |
| 907 | { |
njn | 4ba5a79 | 2002-09-30 10:23:54 +0000 | [diff] [blame] | 908 | VG_(new_emit)(); |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 909 | VG_(emitB) ( 0xFF ); /* Grp5 */ |
| 910 | VG_(emit_amode_ereg_greg) ( reg, mkGrp5opcode(CALLM) ); |
| 911 | if (dis) |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 912 | VG_(printf)( "\n\t\tcall\t*%s\n", nameIReg(4,reg) ); |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 913 | } |
| 914 | |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 915 | static void emit_call_star_EBP_off ( Int byte_off ) |
| 916 | { |
njn | 4ba5a79 | 2002-09-30 10:23:54 +0000 | [diff] [blame] | 917 | VG_(new_emit)(); |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 918 | if (byte_off < -128 || byte_off > 127) { |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 919 | VG_(emitB) ( 0xFF ); |
| 920 | VG_(emitB) ( 0x95 ); |
| 921 | VG_(emitL) ( byte_off ); |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 922 | } else { |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 923 | VG_(emitB) ( 0xFF ); |
| 924 | VG_(emitB) ( 0x55 ); |
| 925 | VG_(emitB) ( byte_off ); |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 926 | } |
| 927 | if (dis) |
| 928 | VG_(printf)( "\n\t\tcall * %d(%%ebp)\n", byte_off ); |
| 929 | } |
| 930 | |
| 931 | |
| 932 | static void emit_addlit8_offregmem ( Int lit8, Int regmem, Int off ) |
| 933 | { |
| 934 | vg_assert(lit8 >= -128 && lit8 < 128); |
njn | 4ba5a79 | 2002-09-30 10:23:54 +0000 | [diff] [blame] | 935 | VG_(new_emit)(); |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 936 | VG_(emitB) ( 0x83 ); /* Grp1 Ib,Ev */ |
| 937 | VG_(emit_amode_offregmem_reg) ( off, regmem, |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 938 | 0 /* Grp1 subopcode for ADD */ ); |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 939 | VG_(emitB) ( lit8 & 0xFF ); |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 940 | if (dis) |
| 941 | VG_(printf)( "\n\t\taddl $%d, %d(%s)\n", lit8, off, |
| 942 | nameIReg(4,regmem)); |
| 943 | } |
| 944 | |
| 945 | |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 946 | void VG_(emit_add_lit_to_esp) ( Int lit ) |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 947 | { |
njn | e427a66 | 2002-10-02 11:08:25 +0000 | [diff] [blame] | 948 | if (lit < -128 || lit > 127) VG_(core_panic)("VG_(emit_add_lit_to_esp)"); |
njn | 4ba5a79 | 2002-09-30 10:23:54 +0000 | [diff] [blame] | 949 | VG_(new_emit)(); |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 950 | VG_(emitB) ( 0x83 ); |
| 951 | VG_(emitB) ( 0xC4 ); |
| 952 | VG_(emitB) ( lit & 0xFF ); |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 953 | if (dis) |
| 954 | VG_(printf)( "\n\t\taddl $%d, %%esp\n", lit ); |
| 955 | } |
| 956 | |
| 957 | |
| 958 | static void emit_movb_AL_zeroESPmem ( void ) |
| 959 | { |
| 960 | /* movb %al, 0(%esp) */ |
| 961 | /* 88442400 movb %al, 0(%esp) */ |
njn | 4ba5a79 | 2002-09-30 10:23:54 +0000 | [diff] [blame] | 962 | VG_(new_emit)(); |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 963 | VG_(emitB) ( 0x88 ); |
| 964 | VG_(emitB) ( 0x44 ); |
| 965 | VG_(emitB) ( 0x24 ); |
| 966 | VG_(emitB) ( 0x00 ); |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 967 | if (dis) |
| 968 | VG_(printf)( "\n\t\tmovb %%al, 0(%%esp)\n" ); |
| 969 | } |
| 970 | |
| 971 | static void emit_movb_zeroESPmem_AL ( void ) |
| 972 | { |
| 973 | /* movb 0(%esp), %al */ |
| 974 | /* 8A442400 movb 0(%esp), %al */ |
njn | 4ba5a79 | 2002-09-30 10:23:54 +0000 | [diff] [blame] | 975 | VG_(new_emit)(); |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 976 | VG_(emitB) ( 0x8A ); |
| 977 | VG_(emitB) ( 0x44 ); |
| 978 | VG_(emitB) ( 0x24 ); |
| 979 | VG_(emitB) ( 0x00 ); |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 980 | if (dis) |
| 981 | VG_(printf)( "\n\t\tmovb 0(%%esp), %%al\n" ); |
| 982 | } |
| 983 | |
| 984 | |
| 985 | /* Emit a jump short with an 8-bit signed offset. Note that the |
| 986 | offset is that which should be added to %eip once %eip has been |
| 987 | advanced over this insn. */ |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 988 | void VG_(emit_jcondshort_delta) ( Condcode cond, Int delta ) |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 989 | { |
| 990 | vg_assert(delta >= -128 && delta <= 127); |
njn | 4ba5a79 | 2002-09-30 10:23:54 +0000 | [diff] [blame] | 991 | VG_(new_emit)(); |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 992 | VG_(emitB) ( 0x70 + (UInt)cond ); |
| 993 | VG_(emitB) ( (UChar)delta ); |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 994 | if (dis) |
| 995 | VG_(printf)( "\n\t\tj%s-8\t%%eip+%d\n", |
| 996 | VG_(nameCondcode)(cond), delta ); |
| 997 | } |
| 998 | |
| 999 | static void emit_get_eflags ( void ) |
| 1000 | { |
| 1001 | Int off = 4 * VGOFF_(m_eflags); |
| 1002 | vg_assert(off >= 0 && off < 128); |
njn | 4ba5a79 | 2002-09-30 10:23:54 +0000 | [diff] [blame] | 1003 | VG_(new_emit)(); |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 1004 | VG_(emitB) ( 0xFF ); /* PUSHL off(%ebp) */ |
| 1005 | VG_(emitB) ( 0x75 ); |
| 1006 | VG_(emitB) ( off ); |
| 1007 | VG_(emitB) ( 0x9D ); /* POPFL */ |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 1008 | if (dis) |
| 1009 | VG_(printf)( "\n\t\tpushl %d(%%ebp) ; popfl\n", off ); |
| 1010 | } |
| 1011 | |
| 1012 | static void emit_put_eflags ( void ) |
| 1013 | { |
| 1014 | Int off = 4 * VGOFF_(m_eflags); |
| 1015 | vg_assert(off >= 0 && off < 128); |
njn | 4ba5a79 | 2002-09-30 10:23:54 +0000 | [diff] [blame] | 1016 | VG_(new_emit)(); |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 1017 | VG_(emitB) ( 0x9C ); /* PUSHFL */ |
| 1018 | VG_(emitB) ( 0x8F ); /* POPL vg_m_state.m_eflags */ |
| 1019 | VG_(emitB) ( 0x45 ); |
| 1020 | VG_(emitB) ( off ); |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 1021 | if (dis) |
| 1022 | VG_(printf)( "\n\t\tpushfl ; popl %d(%%ebp)\n", off ); |
| 1023 | } |
| 1024 | |
| 1025 | static void emit_setb_reg ( Int reg, Condcode cond ) |
| 1026 | { |
njn | 4ba5a79 | 2002-09-30 10:23:54 +0000 | [diff] [blame] | 1027 | VG_(new_emit)(); |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 1028 | VG_(emitB) ( 0x0F ); VG_(emitB) ( 0x90 + (UChar)cond ); |
| 1029 | VG_(emit_amode_ereg_greg) ( reg, 0 ); |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 1030 | if (dis) |
| 1031 | VG_(printf)("\n\t\tset%s %s\n", |
| 1032 | VG_(nameCondcode)(cond), nameIReg(1,reg)); |
| 1033 | } |
| 1034 | |
| 1035 | static void emit_ret ( void ) |
| 1036 | { |
njn | 4ba5a79 | 2002-09-30 10:23:54 +0000 | [diff] [blame] | 1037 | VG_(new_emit)(); |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 1038 | VG_(emitB) ( 0xC3 ); /* RET */ |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 1039 | if (dis) |
| 1040 | VG_(printf)("\n\t\tret\n"); |
| 1041 | } |
| 1042 | |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 1043 | void VG_(emit_pushal) ( void ) |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 1044 | { |
njn | 4ba5a79 | 2002-09-30 10:23:54 +0000 | [diff] [blame] | 1045 | VG_(new_emit)(); |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 1046 | VG_(emitB) ( 0x60 ); /* PUSHAL */ |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 1047 | if (dis) |
| 1048 | VG_(printf)("\n\t\tpushal\n"); |
| 1049 | } |
| 1050 | |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 1051 | void VG_(emit_popal) ( void ) |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 1052 | { |
njn | 4ba5a79 | 2002-09-30 10:23:54 +0000 | [diff] [blame] | 1053 | VG_(new_emit)(); |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 1054 | VG_(emitB) ( 0x61 ); /* POPAL */ |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 1055 | if (dis) |
| 1056 | VG_(printf)("\n\t\tpopal\n"); |
| 1057 | } |
| 1058 | |
| 1059 | static void emit_lea_litreg_reg ( UInt lit, Int regmem, Int reg ) |
| 1060 | { |
njn | 4ba5a79 | 2002-09-30 10:23:54 +0000 | [diff] [blame] | 1061 | VG_(new_emit)(); |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 1062 | VG_(emitB) ( 0x8D ); /* LEA M,Gv */ |
| 1063 | VG_(emit_amode_offregmem_reg) ( (Int)lit, regmem, reg ); |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 1064 | if (dis) |
| 1065 | VG_(printf)("\n\t\tleal 0x%x(%s), %s\n", |
| 1066 | lit, nameIReg(4,regmem), nameIReg(4,reg) ); |
| 1067 | } |
| 1068 | |
| 1069 | static void emit_lea_sib_reg ( UInt lit, Int scale, |
| 1070 | Int regbase, Int regindex, Int reg ) |
| 1071 | { |
njn | 4ba5a79 | 2002-09-30 10:23:54 +0000 | [diff] [blame] | 1072 | VG_(new_emit)(); |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 1073 | VG_(emitB) ( 0x8D ); /* LEA M,Gv */ |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 1074 | emit_amode_sib_reg ( (Int)lit, scale, regbase, regindex, reg ); |
| 1075 | if (dis) |
| 1076 | VG_(printf)("\n\t\tleal 0x%x(%s,%s,%d), %s\n", |
| 1077 | lit, nameIReg(4,regbase), |
| 1078 | nameIReg(4,regindex), scale, |
| 1079 | nameIReg(4,reg) ); |
| 1080 | } |
| 1081 | |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 1082 | void VG_(emit_AMD_prefetch_reg) ( Int reg ) |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 1083 | { |
njn | 4ba5a79 | 2002-09-30 10:23:54 +0000 | [diff] [blame] | 1084 | VG_(new_emit)(); |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 1085 | VG_(emitB) ( 0x0F ); |
| 1086 | VG_(emitB) ( 0x0D ); |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 1087 | emit_amode_regmem_reg ( reg, 1 /* 0 is prefetch; 1 is prefetchw */ ); |
| 1088 | if (dis) |
| 1089 | VG_(printf)("\n\t\tamd-prefetch (%s)\n", nameIReg(4,reg) ); |
| 1090 | } |
| 1091 | |
| 1092 | /*----------------------------------------------------*/ |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 1093 | /*--- Helper offset -> addr translation ---*/ |
| 1094 | /*----------------------------------------------------*/ |
| 1095 | |
| 1096 | /* Finds the baseBlock offset of a skin-specified helper. |
| 1097 | * Searches through compacts first, then non-compacts. */ |
| 1098 | Int VG_(helper_offset)(Addr a) |
| 1099 | { |
| 1100 | Int i; |
| 1101 | |
| 1102 | for (i = 0; i < VG_(n_compact_helpers); i++) |
| 1103 | if (VG_(compact_helper_addrs)[i] == a) |
| 1104 | return VG_(compact_helper_offsets)[i]; |
| 1105 | for (i = 0; i < VG_(n_noncompact_helpers); i++) |
| 1106 | if (VG_(noncompact_helper_addrs)[i] == a) |
| 1107 | return VG_(noncompact_helper_offsets)[i]; |
| 1108 | |
| 1109 | /* Shouldn't get here */ |
| 1110 | VG_(printf)( |
| 1111 | "\nCouldn't find offset of helper from its address (%p).\n" |
| 1112 | "A helper function probably used hasn't been registered?\n\n", a); |
| 1113 | |
| 1114 | VG_(printf)(" compact helpers: "); |
| 1115 | for (i = 0; i < VG_(n_compact_helpers); i++) |
| 1116 | VG_(printf)("%p ", VG_(compact_helper_addrs)[i]); |
| 1117 | |
| 1118 | VG_(printf)("\n non-compact helpers: "); |
| 1119 | for (i = 0; i < VG_(n_noncompact_helpers); i++) |
| 1120 | VG_(printf)("%p ", VG_(noncompact_helper_addrs)[i]); |
| 1121 | |
| 1122 | VG_(printf)("\n"); |
njn | e427a66 | 2002-10-02 11:08:25 +0000 | [diff] [blame] | 1123 | VG_(skin_panic)("Unfound helper"); |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 1124 | } |
| 1125 | |
| 1126 | /*----------------------------------------------------*/ |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 1127 | /*--- Instruction synthesisers ---*/ |
| 1128 | /*----------------------------------------------------*/ |
| 1129 | |
| 1130 | static Condcode invertCondition ( Condcode cond ) |
| 1131 | { |
| 1132 | return (Condcode)(1 ^ (UInt)cond); |
| 1133 | } |
| 1134 | |
| 1135 | |
| 1136 | /* Synthesise a call to *baseBlock[offset], ie, |
| 1137 | call * (4 x offset)(%ebp). |
| 1138 | */ |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 1139 | void VG_(synth_call) ( Bool ensure_shortform, Int word_offset ) |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 1140 | { |
| 1141 | vg_assert(word_offset >= 0); |
| 1142 | vg_assert(word_offset < VG_BASEBLOCK_WORDS); |
| 1143 | if (ensure_shortform) |
| 1144 | vg_assert(word_offset < 32); |
| 1145 | emit_call_star_EBP_off ( 4 * word_offset ); |
| 1146 | } |
| 1147 | |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 1148 | static void maybe_emit_movl_reg_reg ( UInt src, UInt dst ) |
njn | 6431be7 | 2002-07-28 09:53:34 +0000 | [diff] [blame] | 1149 | { |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 1150 | if (src != dst) { |
| 1151 | VG_(emit_movv_reg_reg) ( 4, src, dst ); |
| 1152 | ccall_arg_setup_instrs++; |
| 1153 | } |
njn | 6431be7 | 2002-07-28 09:53:34 +0000 | [diff] [blame] | 1154 | } |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 1155 | |
| 1156 | /* 'maybe' because it is sometimes skipped eg. for "movl %eax,%eax" */ |
| 1157 | static void maybe_emit_movl_litOrReg_reg ( UInt litOrReg, Tag tag, UInt reg ) |
| 1158 | { |
| 1159 | if (RealReg == tag) { |
| 1160 | maybe_emit_movl_reg_reg ( litOrReg, reg ); |
| 1161 | } else if (Literal == tag) { |
| 1162 | VG_(emit_movv_lit_reg) ( 4, litOrReg, reg ); |
| 1163 | ccall_arg_setup_instrs++; |
| 1164 | } |
| 1165 | else |
njn | e427a66 | 2002-10-02 11:08:25 +0000 | [diff] [blame] | 1166 | VG_(core_panic)("emit_movl_litOrReg_reg: unexpected tag"); |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 1167 | } |
| 1168 | |
| 1169 | static |
| 1170 | void emit_swapl_arg_regs ( UInt reg1, UInt reg2 ) |
| 1171 | { |
| 1172 | if (R_EAX == reg1) { |
| 1173 | VG_(emit_swapl_reg_EAX) ( reg2 ); |
| 1174 | } else if (R_EAX == reg2) { |
| 1175 | VG_(emit_swapl_reg_EAX) ( reg1 ); |
| 1176 | } else { |
| 1177 | emit_swapl_reg_reg ( reg1, reg2 ); |
| 1178 | } |
| 1179 | ccall_arg_setup_instrs++; |
| 1180 | } |
| 1181 | |
| 1182 | static |
| 1183 | void emit_two_regs_args_setup ( UInt src1, UInt src2, UInt dst1, UInt dst2) |
| 1184 | { |
| 1185 | if (dst1 != src2) { |
| 1186 | maybe_emit_movl_reg_reg ( src1, dst1 ); |
| 1187 | maybe_emit_movl_reg_reg ( src2, dst2 ); |
| 1188 | |
| 1189 | } else if (dst2 != src1) { |
| 1190 | maybe_emit_movl_reg_reg ( src2, dst2 ); |
| 1191 | maybe_emit_movl_reg_reg ( src1, dst1 ); |
| 1192 | |
| 1193 | } else { |
| 1194 | /* swap to break cycle */ |
| 1195 | emit_swapl_arg_regs ( dst1, dst2 ); |
| 1196 | } |
| 1197 | } |
| 1198 | |
| 1199 | static |
| 1200 | void emit_three_regs_args_setup ( UInt src1, UInt src2, UInt src3, |
| 1201 | UInt dst1, UInt dst2, UInt dst3) |
| 1202 | { |
| 1203 | if (dst1 != src2 && dst1 != src3) { |
| 1204 | maybe_emit_movl_reg_reg ( src1, dst1 ); |
| 1205 | emit_two_regs_args_setup ( src2, src3, dst2, dst3 ); |
| 1206 | |
| 1207 | } else if (dst2 != src1 && dst2 != src3) { |
| 1208 | maybe_emit_movl_reg_reg ( src2, dst2 ); |
| 1209 | emit_two_regs_args_setup ( src1, src3, dst1, dst3 ); |
| 1210 | |
| 1211 | } else if (dst3 != src1 && dst3 != src2) { |
| 1212 | maybe_emit_movl_reg_reg ( src3, dst3 ); |
| 1213 | emit_two_regs_args_setup ( src1, src2, dst1, dst2 ); |
| 1214 | |
| 1215 | } else { |
| 1216 | /* break cycle */ |
| 1217 | if (dst1 == src2 && dst2 == src3 && dst3 == src1) { |
| 1218 | emit_swapl_arg_regs ( dst1, dst2 ); |
| 1219 | emit_swapl_arg_regs ( dst1, dst3 ); |
| 1220 | |
| 1221 | } else if (dst1 == src3 && dst2 == src1 && dst3 == src2) { |
| 1222 | emit_swapl_arg_regs ( dst1, dst3 ); |
| 1223 | emit_swapl_arg_regs ( dst1, dst2 ); |
| 1224 | |
| 1225 | } else { |
njn | e427a66 | 2002-10-02 11:08:25 +0000 | [diff] [blame] | 1226 | VG_(core_panic)("impossible 3-cycle"); |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 1227 | } |
| 1228 | } |
| 1229 | } |
| 1230 | |
| 1231 | static |
| 1232 | void emit_two_regs_or_lits_args_setup ( UInt argv[], Tag tagv[], |
| 1233 | UInt src1, UInt src2, |
| 1234 | UInt dst1, UInt dst2) |
| 1235 | { |
| 1236 | /* If either are lits, order doesn't matter */ |
| 1237 | if (Literal == tagv[src1] || Literal == tagv[src2]) { |
| 1238 | maybe_emit_movl_litOrReg_reg ( argv[src1], tagv[src1], dst1 ); |
| 1239 | maybe_emit_movl_litOrReg_reg ( argv[src2], tagv[src2], dst2 ); |
| 1240 | |
| 1241 | } else { |
| 1242 | emit_two_regs_args_setup ( argv[src1], argv[src2], dst1, dst2 ); |
| 1243 | } |
| 1244 | } |
| 1245 | |
| 1246 | static |
| 1247 | void emit_three_regs_or_lits_args_setup ( UInt argv[], Tag tagv[], |
| 1248 | UInt src1, UInt src2, UInt src3, |
| 1249 | UInt dst1, UInt dst2, UInt dst3) |
| 1250 | { |
| 1251 | // SSS: fix this eventually -- make STOREV use two RealRegs? |
| 1252 | /* Not supporting literals for 3-arg C functions -- they're only used |
| 1253 | by STOREV which has 2 args */ |
| 1254 | vg_assert(RealReg == tagv[src1] && |
| 1255 | RealReg == tagv[src2] && |
| 1256 | RealReg == tagv[src3]); |
| 1257 | emit_three_regs_args_setup ( argv[src1], argv[src2], argv[src3], |
| 1258 | dst1, dst2, dst3 ); |
| 1259 | } |
| 1260 | |
| 1261 | /* Synthesise a call to a C function `fn' (which must be registered in |
| 1262 | baseBlock) doing all the reg saving and arg handling work. |
| 1263 | |
| 1264 | WARNING: a UInstr should *not* be translated with synth_ccall followed |
| 1265 | by some other x86 assembly code; vg_liveness_analysis() doesn't expect |
| 1266 | such behaviour and everything will fall over. |
| 1267 | */ |
| 1268 | void VG_(synth_ccall) ( Addr fn, Int argc, Int regparms_n, UInt argv[], |
| 1269 | Tag tagv[], Int ret_reg, |
| 1270 | RRegSet regs_live_before, RRegSet regs_live_after ) |
| 1271 | { |
| 1272 | Int i; |
| 1273 | Int stack_used = 0; |
| 1274 | Bool preserve_eax, preserve_ecx, preserve_edx; |
| 1275 | |
| 1276 | vg_assert(0 <= regparms_n && regparms_n <= 3); |
| 1277 | |
| 1278 | ccalls++; |
| 1279 | |
| 1280 | /* If %e[acd]x is live before and after the C call, save/restore it. |
| 1281 | Unless the return values clobbers the reg; in this case we must not |
| 1282 | save/restore the reg, because the restore would clobber the return |
| 1283 | value. (Before and after the UInstr really constitute separate live |
| 1284 | ranges, but you miss this if you don't consider what happens during |
| 1285 | the UInstr.) */ |
| 1286 | # define PRESERVE_REG(realReg) \ |
njn | 4ba5a79 | 2002-09-30 10:23:54 +0000 | [diff] [blame] | 1287 | (IS_RREG_LIVE(VG_(realreg_to_rank)(realReg), regs_live_before) && \ |
| 1288 | IS_RREG_LIVE(VG_(realreg_to_rank)(realReg), regs_live_after) && \ |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 1289 | ret_reg != realReg) |
| 1290 | |
| 1291 | preserve_eax = PRESERVE_REG(R_EAX); |
| 1292 | preserve_ecx = PRESERVE_REG(R_ECX); |
| 1293 | preserve_edx = PRESERVE_REG(R_EDX); |
| 1294 | |
| 1295 | # undef PRESERVE_REG |
| 1296 | |
| 1297 | /* Save caller-save regs as required */ |
| 1298 | if (preserve_eax) { VG_(emit_pushv_reg) ( 4, R_EAX ); ccall_reg_saves++; } |
| 1299 | if (preserve_ecx) { VG_(emit_pushv_reg) ( 4, R_ECX ); ccall_reg_saves++; } |
| 1300 | if (preserve_edx) { VG_(emit_pushv_reg) ( 4, R_EDX ); ccall_reg_saves++; } |
| 1301 | |
| 1302 | /* Args are passed in two groups: (a) via stack (b) via regs. regparms_n |
| 1303 | is the number of args passed in regs (maximum 3 for GCC on x86). */ |
| 1304 | |
| 1305 | ccall_args += argc; |
njn | 6431be7 | 2002-07-28 09:53:34 +0000 | [diff] [blame] | 1306 | |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 1307 | /* First push stack args (RealRegs or Literals) in reverse order. */ |
| 1308 | for (i = argc-1; i >= regparms_n; i--) { |
| 1309 | switch (tagv[i]) { |
| 1310 | case RealReg: |
| 1311 | VG_(emit_pushv_reg) ( 4, argv[i] ); |
| 1312 | break; |
| 1313 | case Literal: |
| 1314 | /* Use short form of pushl if possible. */ |
| 1315 | if (argv[i] == VG_(extend_s_8to32) ( argv[i] )) |
| 1316 | VG_(emit_pushl_lit8) ( VG_(extend_s_8to32)(argv[i]) ); |
| 1317 | else |
| 1318 | VG_(emit_pushl_lit32)( argv[i] ); |
| 1319 | break; |
| 1320 | default: |
| 1321 | VG_(printf)("tag=%d\n", tagv[i]); |
njn | e427a66 | 2002-10-02 11:08:25 +0000 | [diff] [blame] | 1322 | VG_(core_panic)("VG_(synth_ccall): bad tag"); |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 1323 | } |
| 1324 | stack_used += 4; |
| 1325 | ccall_arg_setup_instrs++; |
| 1326 | } |
njn | 6431be7 | 2002-07-28 09:53:34 +0000 | [diff] [blame] | 1327 | |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 1328 | /* Then setup args in registers (arg[123] --> %e[adc]x; note order!). |
| 1329 | If moving values between registers, be careful not to clobber any on |
| 1330 | the way. Happily we can use xchgl to swap registers. |
| 1331 | */ |
| 1332 | switch (regparms_n) { |
njn | 6431be7 | 2002-07-28 09:53:34 +0000 | [diff] [blame] | 1333 | |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 1334 | /* Trickiest. Args passed in %eax, %edx, and %ecx. */ |
| 1335 | case 3: |
| 1336 | emit_three_regs_or_lits_args_setup ( argv, tagv, 0, 1, 2, |
| 1337 | R_EAX, R_EDX, R_ECX ); |
| 1338 | break; |
njn | 6431be7 | 2002-07-28 09:53:34 +0000 | [diff] [blame] | 1339 | |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 1340 | /* Less-tricky. Args passed in %eax and %edx. */ |
| 1341 | case 2: |
| 1342 | emit_two_regs_or_lits_args_setup ( argv, tagv, 0, 1, R_EAX, R_EDX ); |
| 1343 | break; |
| 1344 | |
| 1345 | /* Easy. Just move arg1 into %eax (if not already in there). */ |
| 1346 | case 1: |
| 1347 | maybe_emit_movl_litOrReg_reg ( argv[0], tagv[0], R_EAX ); |
| 1348 | break; |
| 1349 | |
| 1350 | case 0: |
| 1351 | break; |
| 1352 | |
| 1353 | default: |
njn | e427a66 | 2002-10-02 11:08:25 +0000 | [diff] [blame] | 1354 | VG_(core_panic)("VG_(synth_call): regparms_n value not in range 0..3"); |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 1355 | } |
| 1356 | |
| 1357 | /* Call the function */ |
| 1358 | VG_(synth_call) ( False, VG_(helper_offset) ( fn ) ); |
| 1359 | |
| 1360 | /* Clear any args from stack */ |
| 1361 | if (0 != stack_used) { |
| 1362 | VG_(emit_add_lit_to_esp) ( stack_used ); |
| 1363 | ccall_stack_clears++; |
| 1364 | } |
| 1365 | |
| 1366 | /* Move return value into ret_reg if necessary and not already there */ |
| 1367 | if (INVALID_REALREG != ret_reg) { |
| 1368 | ccall_retvals++; |
| 1369 | if (R_EAX != ret_reg) { |
| 1370 | VG_(emit_movv_reg_reg) ( 4, R_EAX, ret_reg ); |
| 1371 | ccall_retval_movs++; |
| 1372 | } |
| 1373 | } |
| 1374 | |
| 1375 | /* Restore live caller-save regs as required */ |
| 1376 | if (preserve_edx) VG_(emit_popv_reg) ( 4, R_EDX ); |
| 1377 | if (preserve_ecx) VG_(emit_popv_reg) ( 4, R_ECX ); |
| 1378 | if (preserve_eax) VG_(emit_popv_reg) ( 4, R_EAX ); |
njn | 6431be7 | 2002-07-28 09:53:34 +0000 | [diff] [blame] | 1379 | } |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 1380 | |
sewardj | 2e93c50 | 2002-04-12 11:12:52 +0000 | [diff] [blame] | 1381 | static void load_ebp_from_JmpKind ( JmpKind jmpkind ) |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 1382 | { |
sewardj | 2e93c50 | 2002-04-12 11:12:52 +0000 | [diff] [blame] | 1383 | switch (jmpkind) { |
| 1384 | case JmpBoring: |
| 1385 | break; |
sewardj | 2e93c50 | 2002-04-12 11:12:52 +0000 | [diff] [blame] | 1386 | case JmpRet: |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 1387 | break; |
| 1388 | case JmpCall: |
sewardj | 2e93c50 | 2002-04-12 11:12:52 +0000 | [diff] [blame] | 1389 | break; |
| 1390 | case JmpSyscall: |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 1391 | VG_(emit_movv_lit_reg) ( 4, VG_TRC_EBP_JMP_SYSCALL, R_EBP ); |
sewardj | 2e93c50 | 2002-04-12 11:12:52 +0000 | [diff] [blame] | 1392 | break; |
| 1393 | case JmpClientReq: |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 1394 | VG_(emit_movv_lit_reg) ( 4, VG_TRC_EBP_JMP_CLIENTREQ, R_EBP ); |
sewardj | 2e93c50 | 2002-04-12 11:12:52 +0000 | [diff] [blame] | 1395 | break; |
| 1396 | default: |
njn | e427a66 | 2002-10-02 11:08:25 +0000 | [diff] [blame] | 1397 | VG_(core_panic)("load_ebp_from_JmpKind"); |
sewardj | 2e93c50 | 2002-04-12 11:12:52 +0000 | [diff] [blame] | 1398 | } |
| 1399 | } |
| 1400 | |
| 1401 | /* Jump to the next translation, by loading its original addr into |
| 1402 | %eax and returning to the scheduler. Signal special requirements |
| 1403 | by loading a special value into %ebp first. |
| 1404 | */ |
| 1405 | static void synth_jmp_reg ( Int reg, JmpKind jmpkind ) |
| 1406 | { |
| 1407 | load_ebp_from_JmpKind ( jmpkind ); |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 1408 | if (reg != R_EAX) |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 1409 | VG_(emit_movv_reg_reg) ( 4, reg, R_EAX ); |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 1410 | emit_ret(); |
| 1411 | } |
| 1412 | |
| 1413 | |
| 1414 | /* Same deal as synth_jmp_reg. */ |
sewardj | 2e93c50 | 2002-04-12 11:12:52 +0000 | [diff] [blame] | 1415 | static void synth_jmp_lit ( Addr addr, JmpKind jmpkind ) |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 1416 | { |
sewardj | 2e93c50 | 2002-04-12 11:12:52 +0000 | [diff] [blame] | 1417 | load_ebp_from_JmpKind ( jmpkind ); |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 1418 | VG_(emit_movv_lit_reg) ( 4, addr, R_EAX ); |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 1419 | emit_ret(); |
| 1420 | } |
| 1421 | |
| 1422 | |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 1423 | static void synth_jcond_lit ( Condcode cond, Addr addr ) |
| 1424 | { |
| 1425 | /* Do the following: |
| 1426 | get eflags |
| 1427 | jmp short if not cond to xyxyxy |
| 1428 | addr -> eax |
| 1429 | ret |
| 1430 | xyxyxy |
| 1431 | |
| 1432 | 2 0000 750C jnz xyxyxy |
| 1433 | 3 0002 B877665544 movl $0x44556677, %eax |
| 1434 | 4 0007 C3 ret |
| 1435 | 5 0008 FFE3 jmp *%ebx |
| 1436 | 6 xyxyxy: |
| 1437 | */ |
| 1438 | emit_get_eflags(); |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 1439 | VG_(emit_jcondshort_delta) ( invertCondition(cond), 5+1 ); |
sewardj | 2e93c50 | 2002-04-12 11:12:52 +0000 | [diff] [blame] | 1440 | synth_jmp_lit ( addr, JmpBoring ); |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 1441 | } |
| 1442 | |
| 1443 | |
| 1444 | static void synth_jmp_ifzero_reg_lit ( Int reg, Addr addr ) |
| 1445 | { |
| 1446 | /* 0000 83FF00 cmpl $0, %edi |
| 1447 | 0003 750A jnz next |
| 1448 | 0005 B844332211 movl $0x11223344, %eax |
| 1449 | 000a C3 ret |
| 1450 | next: |
| 1451 | */ |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 1452 | VG_(emit_cmpl_zero_reg) ( reg ); |
| 1453 | VG_(emit_jcondshort_delta) ( CondNZ, 5+1 ); |
sewardj | 2e93c50 | 2002-04-12 11:12:52 +0000 | [diff] [blame] | 1454 | synth_jmp_lit ( addr, JmpBoring ); |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 1455 | } |
| 1456 | |
| 1457 | |
| 1458 | static void synth_mov_lit_reg ( Int size, UInt lit, Int reg ) |
| 1459 | { |
| 1460 | /* Load the zero-extended literal into reg, at size l, |
| 1461 | regardless of the request size. */ |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 1462 | VG_(emit_movv_lit_reg) ( 4, lit, reg ); |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 1463 | } |
| 1464 | |
| 1465 | |
| 1466 | static void synth_mov_regmem_reg ( Int size, Int reg1, Int reg2 ) |
| 1467 | { |
| 1468 | switch (size) { |
| 1469 | case 4: emit_movv_regmem_reg ( 4, reg1, reg2 ); break; |
| 1470 | case 2: emit_movzwl_regmem_reg ( reg1, reg2 ); break; |
| 1471 | case 1: emit_movzbl_regmem_reg ( reg1, reg2 ); break; |
njn | e427a66 | 2002-10-02 11:08:25 +0000 | [diff] [blame] | 1472 | default: VG_(core_panic)("synth_mov_regmem_reg"); |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 1473 | } |
| 1474 | } |
| 1475 | |
| 1476 | |
| 1477 | static void synth_mov_offregmem_reg ( Int size, Int off, Int areg, Int reg ) |
| 1478 | { |
| 1479 | switch (size) { |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 1480 | case 4: VG_(emit_movv_offregmem_reg) ( 4, off, areg, reg ); break; |
| 1481 | case 2: VG_(emit_movzwl_offregmem_reg) ( off, areg, reg ); break; |
| 1482 | case 1: VG_(emit_movzbl_offregmem_reg) ( off, areg, reg ); break; |
njn | e427a66 | 2002-10-02 11:08:25 +0000 | [diff] [blame] | 1483 | default: VG_(core_panic)("synth_mov_offregmem_reg"); |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 1484 | } |
| 1485 | } |
| 1486 | |
| 1487 | |
| 1488 | static void synth_mov_reg_offregmem ( Int size, Int reg, |
| 1489 | Int off, Int areg ) |
| 1490 | { |
| 1491 | switch (size) { |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 1492 | case 4: VG_(emit_movv_reg_offregmem) ( 4, reg, off, areg ); break; |
| 1493 | case 2: VG_(emit_movv_reg_offregmem) ( 2, reg, off, areg ); break; |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 1494 | case 1: if (reg < 4) { |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 1495 | VG_(emit_movb_reg_offregmem) ( reg, off, areg ); |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 1496 | } |
| 1497 | else { |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 1498 | VG_(emit_swapl_reg_EAX) ( reg ); |
| 1499 | VG_(emit_movb_reg_offregmem) ( R_AL, off, areg ); |
| 1500 | VG_(emit_swapl_reg_EAX) ( reg ); |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 1501 | } |
| 1502 | break; |
njn | e427a66 | 2002-10-02 11:08:25 +0000 | [diff] [blame] | 1503 | default: VG_(core_panic)("synth_mov_reg_offregmem"); |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 1504 | } |
| 1505 | } |
| 1506 | |
| 1507 | |
| 1508 | static void synth_mov_reg_memreg ( Int size, Int reg1, Int reg2 ) |
| 1509 | { |
| 1510 | Int s1; |
| 1511 | switch (size) { |
| 1512 | case 4: emit_movv_reg_regmem ( 4, reg1, reg2 ); break; |
| 1513 | case 2: emit_movv_reg_regmem ( 2, reg1, reg2 ); break; |
| 1514 | case 1: if (reg1 < 4) { |
| 1515 | emit_movb_reg_regmem ( reg1, reg2 ); |
| 1516 | } |
| 1517 | else { |
| 1518 | /* Choose a swap reg which is < 4 and not reg1 or reg2. */ |
| 1519 | for (s1 = 0; s1 == reg1 || s1 == reg2; s1++) ; |
| 1520 | emit_swapl_reg_reg ( s1, reg1 ); |
| 1521 | emit_movb_reg_regmem ( s1, reg2 ); |
| 1522 | emit_swapl_reg_reg ( s1, reg1 ); |
| 1523 | } |
| 1524 | break; |
njn | e427a66 | 2002-10-02 11:08:25 +0000 | [diff] [blame] | 1525 | default: VG_(core_panic)("synth_mov_reg_litmem"); |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 1526 | } |
| 1527 | } |
| 1528 | |
| 1529 | |
njn | 5a74eb8 | 2002-08-06 20:56:40 +0000 | [diff] [blame] | 1530 | static void synth_unaryop_reg ( Bool wr_cc, |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 1531 | Opcode opcode, Int size, |
| 1532 | Int reg ) |
| 1533 | { |
| 1534 | /* NB! opcode is a uinstr opcode, not an x86 one! */ |
| 1535 | switch (size) { |
njn | 5a74eb8 | 2002-08-06 20:56:40 +0000 | [diff] [blame] | 1536 | case 4: //if (rd_cc) emit_get_eflags(); (never needed --njn) |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 1537 | VG_(emit_unaryopv_reg) ( 4, opcode, reg ); |
njn | 5a74eb8 | 2002-08-06 20:56:40 +0000 | [diff] [blame] | 1538 | if (wr_cc) emit_put_eflags(); |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 1539 | break; |
njn | 5a74eb8 | 2002-08-06 20:56:40 +0000 | [diff] [blame] | 1540 | case 2: //if (rd_cc) emit_get_eflags(); (never needed --njn) |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 1541 | VG_(emit_unaryopv_reg) ( 2, opcode, reg ); |
njn | 5a74eb8 | 2002-08-06 20:56:40 +0000 | [diff] [blame] | 1542 | if (wr_cc) emit_put_eflags(); |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 1543 | break; |
| 1544 | case 1: if (reg < 4) { |
njn | 5a74eb8 | 2002-08-06 20:56:40 +0000 | [diff] [blame] | 1545 | //if (rd_cc) emit_get_eflags(); (never needed --njn) |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 1546 | VG_(emit_unaryopb_reg) ( opcode, reg ); |
njn | 5a74eb8 | 2002-08-06 20:56:40 +0000 | [diff] [blame] | 1547 | if (wr_cc) emit_put_eflags(); |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 1548 | } else { |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 1549 | VG_(emit_swapl_reg_EAX) ( reg ); |
njn | 5a74eb8 | 2002-08-06 20:56:40 +0000 | [diff] [blame] | 1550 | //if (rd_cc) emit_get_eflags(); (never needed --njn) |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 1551 | VG_(emit_unaryopb_reg) ( opcode, R_AL ); |
njn | 5a74eb8 | 2002-08-06 20:56:40 +0000 | [diff] [blame] | 1552 | if (wr_cc) emit_put_eflags(); |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 1553 | VG_(emit_swapl_reg_EAX) ( reg ); |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 1554 | } |
| 1555 | break; |
njn | e427a66 | 2002-10-02 11:08:25 +0000 | [diff] [blame] | 1556 | default: VG_(core_panic)("synth_unaryop_reg"); |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 1557 | } |
| 1558 | } |
| 1559 | |
| 1560 | |
| 1561 | |
njn | 5a74eb8 | 2002-08-06 20:56:40 +0000 | [diff] [blame] | 1562 | static void synth_nonshiftop_reg_reg ( Bool rd_cc, Bool wr_cc, |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 1563 | Opcode opcode, Int size, |
| 1564 | Int reg1, Int reg2 ) |
| 1565 | { |
| 1566 | /* NB! opcode is a uinstr opcode, not an x86 one! */ |
| 1567 | switch (size) { |
njn | 5a74eb8 | 2002-08-06 20:56:40 +0000 | [diff] [blame] | 1568 | case 4: if (rd_cc) emit_get_eflags(); |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 1569 | VG_(emit_nonshiftopv_reg_reg) ( 4, opcode, reg1, reg2 ); |
njn | 5a74eb8 | 2002-08-06 20:56:40 +0000 | [diff] [blame] | 1570 | if (wr_cc) emit_put_eflags(); |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 1571 | break; |
njn | 5a74eb8 | 2002-08-06 20:56:40 +0000 | [diff] [blame] | 1572 | case 2: if (rd_cc) emit_get_eflags(); |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 1573 | VG_(emit_nonshiftopv_reg_reg) ( 2, opcode, reg1, reg2 ); |
njn | 5a74eb8 | 2002-08-06 20:56:40 +0000 | [diff] [blame] | 1574 | if (wr_cc) emit_put_eflags(); |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 1575 | break; |
| 1576 | case 1: { /* Horrible ... */ |
| 1577 | Int s1, s2; |
| 1578 | /* Choose s1 and s2 to be x86 regs which we can talk about the |
| 1579 | lowest 8 bits, ie either %eax, %ebx, %ecx or %edx. Make |
| 1580 | sure s1 != s2 and that neither of them equal either reg1 or |
| 1581 | reg2. Then use them as temporaries to make things work. */ |
| 1582 | if (reg1 < 4 && reg2 < 4) { |
njn | 5a74eb8 | 2002-08-06 20:56:40 +0000 | [diff] [blame] | 1583 | if (rd_cc) emit_get_eflags(); |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 1584 | emit_nonshiftopb_reg_reg(opcode, reg1, reg2); |
njn | 5a74eb8 | 2002-08-06 20:56:40 +0000 | [diff] [blame] | 1585 | if (wr_cc) emit_put_eflags(); |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 1586 | break; |
| 1587 | } |
| 1588 | for (s1 = 0; s1 == reg1 || s1 == reg2; s1++) ; |
| 1589 | if (reg1 >= 4 && reg2 < 4) { |
| 1590 | emit_swapl_reg_reg ( reg1, s1 ); |
njn | 5a74eb8 | 2002-08-06 20:56:40 +0000 | [diff] [blame] | 1591 | if (rd_cc) emit_get_eflags(); |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 1592 | emit_nonshiftopb_reg_reg(opcode, s1, reg2); |
njn | 5a74eb8 | 2002-08-06 20:56:40 +0000 | [diff] [blame] | 1593 | if (wr_cc) emit_put_eflags(); |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 1594 | emit_swapl_reg_reg ( reg1, s1 ); |
| 1595 | break; |
| 1596 | } |
| 1597 | for (s2 = 0; s2 == reg1 || s2 == reg2 || s2 == s1; s2++) ; |
| 1598 | if (reg1 < 4 && reg2 >= 4) { |
| 1599 | emit_swapl_reg_reg ( reg2, s2 ); |
njn | 5a74eb8 | 2002-08-06 20:56:40 +0000 | [diff] [blame] | 1600 | if (rd_cc) emit_get_eflags(); |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 1601 | emit_nonshiftopb_reg_reg(opcode, reg1, s2); |
njn | 5a74eb8 | 2002-08-06 20:56:40 +0000 | [diff] [blame] | 1602 | if (wr_cc) emit_put_eflags(); |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 1603 | emit_swapl_reg_reg ( reg2, s2 ); |
| 1604 | break; |
| 1605 | } |
| 1606 | if (reg1 >= 4 && reg2 >= 4 && reg1 != reg2) { |
| 1607 | emit_swapl_reg_reg ( reg1, s1 ); |
| 1608 | emit_swapl_reg_reg ( reg2, s2 ); |
njn | 5a74eb8 | 2002-08-06 20:56:40 +0000 | [diff] [blame] | 1609 | if (rd_cc) emit_get_eflags(); |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 1610 | emit_nonshiftopb_reg_reg(opcode, s1, s2); |
njn | 5a74eb8 | 2002-08-06 20:56:40 +0000 | [diff] [blame] | 1611 | if (wr_cc) emit_put_eflags(); |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 1612 | emit_swapl_reg_reg ( reg1, s1 ); |
| 1613 | emit_swapl_reg_reg ( reg2, s2 ); |
| 1614 | break; |
| 1615 | } |
| 1616 | if (reg1 >= 4 && reg2 >= 4 && reg1 == reg2) { |
| 1617 | emit_swapl_reg_reg ( reg1, s1 ); |
njn | 5a74eb8 | 2002-08-06 20:56:40 +0000 | [diff] [blame] | 1618 | if (rd_cc) emit_get_eflags(); |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 1619 | emit_nonshiftopb_reg_reg(opcode, s1, s1); |
njn | 5a74eb8 | 2002-08-06 20:56:40 +0000 | [diff] [blame] | 1620 | if (wr_cc) emit_put_eflags(); |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 1621 | emit_swapl_reg_reg ( reg1, s1 ); |
| 1622 | break; |
| 1623 | } |
njn | e427a66 | 2002-10-02 11:08:25 +0000 | [diff] [blame] | 1624 | VG_(core_panic)("synth_nonshiftopb_reg_reg"); |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 1625 | } |
njn | e427a66 | 2002-10-02 11:08:25 +0000 | [diff] [blame] | 1626 | default: VG_(core_panic)("synth_nonshiftop_reg_reg"); |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 1627 | } |
| 1628 | } |
| 1629 | |
| 1630 | |
| 1631 | static void synth_nonshiftop_offregmem_reg ( |
njn | 5a74eb8 | 2002-08-06 20:56:40 +0000 | [diff] [blame] | 1632 | Bool rd_cc, Bool wr_cc, |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 1633 | Opcode opcode, Int size, |
| 1634 | Int off, Int areg, Int reg ) |
| 1635 | { |
| 1636 | switch (size) { |
| 1637 | case 4: |
njn | 5a74eb8 | 2002-08-06 20:56:40 +0000 | [diff] [blame] | 1638 | if (rd_cc) emit_get_eflags(); |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 1639 | emit_nonshiftopv_offregmem_reg ( 4, opcode, off, areg, reg ); |
njn | 5a74eb8 | 2002-08-06 20:56:40 +0000 | [diff] [blame] | 1640 | if (wr_cc) emit_put_eflags(); |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 1641 | break; |
| 1642 | case 2: |
njn | 5a74eb8 | 2002-08-06 20:56:40 +0000 | [diff] [blame] | 1643 | if (rd_cc) emit_get_eflags(); |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 1644 | emit_nonshiftopv_offregmem_reg ( 2, opcode, off, areg, reg ); |
njn | 5a74eb8 | 2002-08-06 20:56:40 +0000 | [diff] [blame] | 1645 | if (wr_cc) emit_put_eflags(); |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 1646 | break; |
| 1647 | case 1: |
| 1648 | if (reg < 4) { |
njn | 5a74eb8 | 2002-08-06 20:56:40 +0000 | [diff] [blame] | 1649 | if (rd_cc) emit_get_eflags(); |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 1650 | emit_nonshiftopb_offregmem_reg ( opcode, off, areg, reg ); |
njn | 5a74eb8 | 2002-08-06 20:56:40 +0000 | [diff] [blame] | 1651 | if (wr_cc) emit_put_eflags(); |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 1652 | } else { |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 1653 | VG_(emit_swapl_reg_EAX) ( reg ); |
njn | 5a74eb8 | 2002-08-06 20:56:40 +0000 | [diff] [blame] | 1654 | if (rd_cc) emit_get_eflags(); |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 1655 | emit_nonshiftopb_offregmem_reg ( opcode, off, areg, R_AL ); |
njn | 5a74eb8 | 2002-08-06 20:56:40 +0000 | [diff] [blame] | 1656 | if (wr_cc) emit_put_eflags(); |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 1657 | VG_(emit_swapl_reg_EAX) ( reg ); |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 1658 | } |
| 1659 | break; |
| 1660 | default: |
njn | e427a66 | 2002-10-02 11:08:25 +0000 | [diff] [blame] | 1661 | VG_(core_panic)("synth_nonshiftop_offregmem_reg"); |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 1662 | } |
| 1663 | } |
| 1664 | |
| 1665 | |
njn | 5a74eb8 | 2002-08-06 20:56:40 +0000 | [diff] [blame] | 1666 | static void synth_nonshiftop_lit_reg ( Bool rd_cc, Bool wr_cc, |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 1667 | Opcode opcode, Int size, |
| 1668 | UInt lit, Int reg ) |
| 1669 | { |
| 1670 | switch (size) { |
njn | 5a74eb8 | 2002-08-06 20:56:40 +0000 | [diff] [blame] | 1671 | case 4: if (rd_cc) emit_get_eflags(); |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 1672 | VG_(emit_nonshiftopv_lit_reg) ( 4, opcode, lit, reg ); |
njn | 5a74eb8 | 2002-08-06 20:56:40 +0000 | [diff] [blame] | 1673 | if (wr_cc) emit_put_eflags(); |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 1674 | break; |
njn | 5a74eb8 | 2002-08-06 20:56:40 +0000 | [diff] [blame] | 1675 | case 2: if (rd_cc) emit_get_eflags(); |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 1676 | VG_(emit_nonshiftopv_lit_reg) ( 2, opcode, lit, reg ); |
njn | 5a74eb8 | 2002-08-06 20:56:40 +0000 | [diff] [blame] | 1677 | if (wr_cc) emit_put_eflags(); |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 1678 | break; |
| 1679 | case 1: if (reg < 4) { |
njn | 5a74eb8 | 2002-08-06 20:56:40 +0000 | [diff] [blame] | 1680 | if (rd_cc) emit_get_eflags(); |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 1681 | emit_nonshiftopb_lit_reg ( opcode, lit, reg ); |
njn | 5a74eb8 | 2002-08-06 20:56:40 +0000 | [diff] [blame] | 1682 | if (wr_cc) emit_put_eflags(); |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 1683 | } else { |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 1684 | VG_(emit_swapl_reg_EAX) ( reg ); |
njn | 5a74eb8 | 2002-08-06 20:56:40 +0000 | [diff] [blame] | 1685 | if (rd_cc) emit_get_eflags(); |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 1686 | emit_nonshiftopb_lit_reg ( opcode, lit, R_AL ); |
njn | 5a74eb8 | 2002-08-06 20:56:40 +0000 | [diff] [blame] | 1687 | if (wr_cc) emit_put_eflags(); |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 1688 | VG_(emit_swapl_reg_EAX) ( reg ); |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 1689 | } |
| 1690 | break; |
njn | e427a66 | 2002-10-02 11:08:25 +0000 | [diff] [blame] | 1691 | default: VG_(core_panic)("synth_nonshiftop_lit_reg"); |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 1692 | } |
| 1693 | } |
| 1694 | |
| 1695 | |
| 1696 | static void synth_push_reg ( Int size, Int reg ) |
| 1697 | { |
| 1698 | switch (size) { |
| 1699 | case 4: |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 1700 | VG_(emit_pushv_reg) ( 4, reg ); |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 1701 | break; |
| 1702 | case 2: |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 1703 | VG_(emit_pushv_reg) ( 2, reg ); |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 1704 | break; |
| 1705 | /* Pray that we don't have to generate this really cruddy bit of |
| 1706 | code very often. Could do better, but can I be bothered? */ |
| 1707 | case 1: |
| 1708 | vg_assert(reg != R_ESP); /* duh */ |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 1709 | VG_(emit_add_lit_to_esp)(-1); |
| 1710 | if (reg != R_EAX) VG_(emit_swapl_reg_EAX) ( reg ); |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 1711 | emit_movb_AL_zeroESPmem(); |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 1712 | if (reg != R_EAX) VG_(emit_swapl_reg_EAX) ( reg ); |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 1713 | break; |
| 1714 | default: |
njn | e427a66 | 2002-10-02 11:08:25 +0000 | [diff] [blame] | 1715 | VG_(core_panic)("synth_push_reg"); |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 1716 | } |
| 1717 | } |
| 1718 | |
| 1719 | |
| 1720 | static void synth_pop_reg ( Int size, Int reg ) |
| 1721 | { |
| 1722 | switch (size) { |
| 1723 | case 4: |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 1724 | VG_(emit_popv_reg) ( 4, reg ); |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 1725 | break; |
| 1726 | case 2: |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 1727 | VG_(emit_popv_reg) ( 2, reg ); |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 1728 | break; |
| 1729 | case 1: |
| 1730 | /* Same comment as above applies. */ |
| 1731 | vg_assert(reg != R_ESP); /* duh */ |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 1732 | if (reg != R_EAX) VG_(emit_swapl_reg_EAX) ( reg ); |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 1733 | emit_movb_zeroESPmem_AL(); |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 1734 | if (reg != R_EAX) VG_(emit_swapl_reg_EAX) ( reg ); |
| 1735 | VG_(emit_add_lit_to_esp)(1); |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 1736 | break; |
njn | e427a66 | 2002-10-02 11:08:25 +0000 | [diff] [blame] | 1737 | default: VG_(core_panic)("synth_pop_reg"); |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 1738 | } |
| 1739 | } |
| 1740 | |
| 1741 | |
njn | 5a74eb8 | 2002-08-06 20:56:40 +0000 | [diff] [blame] | 1742 | static void synth_shiftop_reg_reg ( Bool rd_cc, Bool wr_cc, |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 1743 | Opcode opcode, Int size, |
| 1744 | Int regs, Int regd ) |
| 1745 | { |
| 1746 | synth_push_reg ( size, regd ); |
| 1747 | if (regs != R_ECX) emit_swapl_reg_ECX ( regs ); |
njn | 5a74eb8 | 2002-08-06 20:56:40 +0000 | [diff] [blame] | 1748 | if (rd_cc) emit_get_eflags(); |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 1749 | switch (size) { |
| 1750 | case 4: emit_shiftopv_cl_stack0 ( 4, opcode ); break; |
| 1751 | case 2: emit_shiftopv_cl_stack0 ( 2, opcode ); break; |
| 1752 | case 1: emit_shiftopb_cl_stack0 ( opcode ); break; |
njn | e427a66 | 2002-10-02 11:08:25 +0000 | [diff] [blame] | 1753 | default: VG_(core_panic)("synth_shiftop_reg_reg"); |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 1754 | } |
njn | 5a74eb8 | 2002-08-06 20:56:40 +0000 | [diff] [blame] | 1755 | if (wr_cc) emit_put_eflags(); |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 1756 | if (regs != R_ECX) emit_swapl_reg_ECX ( regs ); |
| 1757 | synth_pop_reg ( size, regd ); |
| 1758 | } |
| 1759 | |
| 1760 | |
njn | 5a74eb8 | 2002-08-06 20:56:40 +0000 | [diff] [blame] | 1761 | static void synth_shiftop_lit_reg ( Bool rd_cc, Bool wr_cc, |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 1762 | Opcode opcode, Int size, |
| 1763 | UInt lit, Int reg ) |
| 1764 | { |
| 1765 | switch (size) { |
njn | 5a74eb8 | 2002-08-06 20:56:40 +0000 | [diff] [blame] | 1766 | case 4: if (rd_cc) emit_get_eflags(); |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 1767 | VG_(emit_shiftopv_lit_reg) ( 4, opcode, lit, reg ); |
njn | 5a74eb8 | 2002-08-06 20:56:40 +0000 | [diff] [blame] | 1768 | if (wr_cc) emit_put_eflags(); |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 1769 | break; |
njn | 5a74eb8 | 2002-08-06 20:56:40 +0000 | [diff] [blame] | 1770 | case 2: if (rd_cc) emit_get_eflags(); |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 1771 | VG_(emit_shiftopv_lit_reg) ( 2, opcode, lit, reg ); |
njn | 5a74eb8 | 2002-08-06 20:56:40 +0000 | [diff] [blame] | 1772 | if (wr_cc) emit_put_eflags(); |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 1773 | break; |
| 1774 | case 1: if (reg < 4) { |
njn | 5a74eb8 | 2002-08-06 20:56:40 +0000 | [diff] [blame] | 1775 | if (rd_cc) emit_get_eflags(); |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 1776 | emit_shiftopb_lit_reg ( opcode, lit, reg ); |
njn | 5a74eb8 | 2002-08-06 20:56:40 +0000 | [diff] [blame] | 1777 | if (wr_cc) emit_put_eflags(); |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 1778 | } else { |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 1779 | VG_(emit_swapl_reg_EAX) ( reg ); |
njn | 5a74eb8 | 2002-08-06 20:56:40 +0000 | [diff] [blame] | 1780 | if (rd_cc) emit_get_eflags(); |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 1781 | emit_shiftopb_lit_reg ( opcode, lit, R_AL ); |
njn | 5a74eb8 | 2002-08-06 20:56:40 +0000 | [diff] [blame] | 1782 | if (wr_cc) emit_put_eflags(); |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 1783 | VG_(emit_swapl_reg_EAX) ( reg ); |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 1784 | } |
| 1785 | break; |
njn | e427a66 | 2002-10-02 11:08:25 +0000 | [diff] [blame] | 1786 | default: VG_(core_panic)("synth_shiftop_lit_reg"); |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 1787 | } |
| 1788 | } |
| 1789 | |
| 1790 | |
| 1791 | static void synth_setb_reg ( Int reg, Condcode cond ) |
| 1792 | { |
| 1793 | emit_get_eflags(); |
| 1794 | if (reg < 4) { |
| 1795 | emit_setb_reg ( reg, cond ); |
| 1796 | } else { |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 1797 | VG_(emit_swapl_reg_EAX) ( reg ); |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 1798 | emit_setb_reg ( R_AL, cond ); |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 1799 | VG_(emit_swapl_reg_EAX) ( reg ); |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 1800 | } |
| 1801 | } |
| 1802 | |
| 1803 | |
| 1804 | static void synth_fpu_regmem ( UChar first_byte, |
| 1805 | UChar second_byte_masked, |
| 1806 | Int reg ) |
| 1807 | { |
| 1808 | emit_get_fpu_state(); |
| 1809 | emit_fpu_regmem ( first_byte, second_byte_masked, reg ); |
| 1810 | emit_put_fpu_state(); |
| 1811 | } |
| 1812 | |
| 1813 | |
| 1814 | static void synth_fpu_no_mem ( UChar first_byte, |
| 1815 | UChar second_byte ) |
| 1816 | { |
| 1817 | emit_get_fpu_state(); |
| 1818 | emit_fpu_no_mem ( first_byte, second_byte ); |
| 1819 | emit_put_fpu_state(); |
| 1820 | } |
| 1821 | |
| 1822 | |
| 1823 | static void synth_movl_reg_reg ( Int src, Int dst ) |
| 1824 | { |
| 1825 | emit_movl_reg_reg ( src, dst ); |
| 1826 | } |
| 1827 | |
| 1828 | static void synth_cmovl_reg_reg ( Condcode cond, Int src, Int dst ) |
| 1829 | { |
| 1830 | emit_get_eflags(); |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 1831 | VG_(emit_jcondshort_delta) ( invertCondition(cond), |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 1832 | 2 /* length of the next insn */ ); |
| 1833 | emit_movl_reg_reg ( src, dst ); |
| 1834 | } |
| 1835 | |
| 1836 | |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 1837 | /*----------------------------------------------------*/ |
| 1838 | /*--- Top level of the uinstr -> x86 translation. ---*/ |
| 1839 | /*----------------------------------------------------*/ |
| 1840 | |
| 1841 | /* Return the byte offset from %ebp (ie, into baseBlock) |
| 1842 | for the specified ArchReg or SpillNo. */ |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 1843 | static Int spillOrArchOffset ( Int size, Tag tag, UInt value ) |
| 1844 | { |
| 1845 | if (tag == SpillNo) { |
| 1846 | vg_assert(size == 4); |
| 1847 | vg_assert(value >= 0 && value < VG_MAX_SPILLSLOTS); |
| 1848 | return 4 * (value + VGOFF_(spillslots)); |
| 1849 | } |
| 1850 | if (tag == ArchReg) { |
| 1851 | switch (value) { |
| 1852 | case R_EAX: return 4 * VGOFF_(m_eax); |
| 1853 | case R_ECX: return 4 * VGOFF_(m_ecx); |
| 1854 | case R_EDX: return 4 * VGOFF_(m_edx); |
| 1855 | case R_EBX: return 4 * VGOFF_(m_ebx); |
| 1856 | case R_ESP: |
| 1857 | if (size == 1) return 4 * VGOFF_(m_eax) + 1; |
| 1858 | else return 4 * VGOFF_(m_esp); |
| 1859 | case R_EBP: |
| 1860 | if (size == 1) return 4 * VGOFF_(m_ecx) + 1; |
| 1861 | else return 4 * VGOFF_(m_ebp); |
| 1862 | case R_ESI: |
| 1863 | if (size == 1) return 4 * VGOFF_(m_edx) + 1; |
| 1864 | else return 4 * VGOFF_(m_esi); |
| 1865 | case R_EDI: |
| 1866 | if (size == 1) return 4 * VGOFF_(m_ebx) + 1; |
| 1867 | else return 4 * VGOFF_(m_edi); |
| 1868 | } |
| 1869 | } |
njn | e427a66 | 2002-10-02 11:08:25 +0000 | [diff] [blame] | 1870 | VG_(core_panic)("spillOrArchOffset"); |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 1871 | } |
| 1872 | |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 1873 | static Int eflagsOffset ( void ) |
| 1874 | { |
| 1875 | return 4 * VGOFF_(m_eflags); |
| 1876 | } |
| 1877 | |
sewardj | e104247 | 2002-09-30 12:33:11 +0000 | [diff] [blame] | 1878 | static Int segRegOffset ( UInt archregs ) |
| 1879 | { |
| 1880 | switch (archregs) { |
| 1881 | case R_CS: return 4 * VGOFF_(m_cs); |
| 1882 | case R_SS: return 4 * VGOFF_(m_ss); |
| 1883 | case R_DS: return 4 * VGOFF_(m_ds); |
| 1884 | case R_ES: return 4 * VGOFF_(m_es); |
| 1885 | case R_FS: return 4 * VGOFF_(m_fs); |
| 1886 | case R_GS: return 4 * VGOFF_(m_gs); |
njn | e427a66 | 2002-10-02 11:08:25 +0000 | [diff] [blame] | 1887 | default: VG_(core_panic)("segRegOffset"); |
sewardj | e104247 | 2002-09-30 12:33:11 +0000 | [diff] [blame] | 1888 | } |
| 1889 | } |
| 1890 | |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 1891 | |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 1892 | /* Return the byte offset from %ebp (ie, into baseBlock) |
| 1893 | for the specified shadow register */ |
njn | 4ba5a79 | 2002-09-30 10:23:54 +0000 | [diff] [blame] | 1894 | Int VG_(shadow_reg_offset) ( Int arch ) |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 1895 | { |
| 1896 | switch (arch) { |
| 1897 | case R_EAX: return 4 * VGOFF_(sh_eax); |
| 1898 | case R_ECX: return 4 * VGOFF_(sh_ecx); |
| 1899 | case R_EDX: return 4 * VGOFF_(sh_edx); |
| 1900 | case R_EBX: return 4 * VGOFF_(sh_ebx); |
| 1901 | case R_ESP: return 4 * VGOFF_(sh_esp); |
| 1902 | case R_EBP: return 4 * VGOFF_(sh_ebp); |
| 1903 | case R_ESI: return 4 * VGOFF_(sh_esi); |
| 1904 | case R_EDI: return 4 * VGOFF_(sh_edi); |
njn | e427a66 | 2002-10-02 11:08:25 +0000 | [diff] [blame] | 1905 | default: VG_(core_panic)( "shadowOffset"); |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 1906 | } |
| 1907 | } |
| 1908 | |
njn | 4ba5a79 | 2002-09-30 10:23:54 +0000 | [diff] [blame] | 1909 | Int VG_(shadow_flags_offset) ( void ) |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 1910 | { |
| 1911 | return 4 * VGOFF_(sh_eflags); |
| 1912 | } |
| 1913 | |
| 1914 | |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 1915 | |
| 1916 | static void synth_WIDEN_signed ( Int sz_src, Int sz_dst, Int reg ) |
| 1917 | { |
| 1918 | if (sz_src == 1 && sz_dst == 4) { |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 1919 | VG_(emit_shiftopv_lit_reg) ( 4, SHL, 24, reg ); |
| 1920 | VG_(emit_shiftopv_lit_reg) ( 4, SAR, 24, reg ); |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 1921 | } |
| 1922 | else if (sz_src == 2 && sz_dst == 4) { |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 1923 | VG_(emit_shiftopv_lit_reg) ( 4, SHL, 16, reg ); |
| 1924 | VG_(emit_shiftopv_lit_reg) ( 4, SAR, 16, reg ); |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 1925 | } |
| 1926 | else if (sz_src == 1 && sz_dst == 2) { |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 1927 | VG_(emit_shiftopv_lit_reg) ( 2, SHL, 8, reg ); |
| 1928 | VG_(emit_shiftopv_lit_reg) ( 2, SAR, 8, reg ); |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 1929 | } |
| 1930 | else |
njn | e427a66 | 2002-10-02 11:08:25 +0000 | [diff] [blame] | 1931 | VG_(core_panic)("synth_WIDEN"); |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 1932 | } |
| 1933 | |
| 1934 | |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 1935 | static void synth_handle_esp_assignment ( Int i, Int reg, |
| 1936 | RRegSet regs_live_before, |
| 1937 | RRegSet regs_live_after ) |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 1938 | { |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 1939 | UInt argv[] = { reg }; |
| 1940 | Tag tagv[] = { RealReg }; |
| 1941 | |
| 1942 | VG_(synth_ccall) ( (Addr) VG_(handle_esp_assignment), 1, 1, argv, tagv, |
| 1943 | INVALID_REALREG, regs_live_before, regs_live_after); |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 1944 | } |
| 1945 | |
| 1946 | |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 1947 | /*----------------------------------------------------*/ |
| 1948 | /*--- Generate code for a single UInstr. ---*/ |
| 1949 | /*----------------------------------------------------*/ |
| 1950 | |
njn | 5a74eb8 | 2002-08-06 20:56:40 +0000 | [diff] [blame] | 1951 | static Bool readFlagUse ( UInstr* u ) |
| 1952 | { |
| 1953 | return (u->flags_r != FlagsEmpty); |
| 1954 | } |
| 1955 | |
| 1956 | static Bool writeFlagUse ( UInstr* u ) |
| 1957 | { |
| 1958 | return (u->flags_w != FlagsEmpty); |
| 1959 | } |
| 1960 | |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 1961 | static void emitUInstr ( UCodeBlock* cb, Int i, RRegSet regs_live_before ) |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 1962 | { |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 1963 | Int old_emitted_code_used; |
| 1964 | UInstr* u = &cb->instrs[i]; |
| 1965 | |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 1966 | if (dis) |
njn | 4ba5a79 | 2002-09-30 10:23:54 +0000 | [diff] [blame] | 1967 | VG_(pp_UInstr_regs)(i, u); |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 1968 | |
| 1969 | # if 0 |
| 1970 | if (0&& VG_(translations_done) >= 600) { |
| 1971 | Bool old_dis = dis; |
| 1972 | dis = False; |
| 1973 | synth_OINK(i); |
| 1974 | dis = old_dis; |
| 1975 | } |
| 1976 | # endif |
| 1977 | |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 1978 | old_emitted_code_used = emitted_code_used; |
| 1979 | |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 1980 | switch (u->opcode) { |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 1981 | case NOP: case CALLM_S: case CALLM_E: break; |
| 1982 | |
| 1983 | case INCEIP: { |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 1984 | /* Note: Redundant INCEIP merging. A potentially useful |
| 1985 | performance enhancementa, but currently disabled. Reason |
| 1986 | is that it needs a surefire way to know if a UInstr might |
| 1987 | give rise to a stack snapshot being taken. The logic below |
| 1988 | is correct (hopefully ...) for the core UInstrs, but is |
| 1989 | incorrect if a skin has its own UInstrs, since the logic |
| 1990 | currently assumes that none of them can cause a stack |
| 1991 | trace, and that's just wrong. Note this isn't |
| 1992 | mission-critical -- the system still functions -- but will |
| 1993 | cause incorrect source locations in some situations, |
| 1994 | specifically for the memcheck skin. This is known to |
| 1995 | confuse programmers, understandable. */ |
| 1996 | # if 0 |
| 1997 | Bool can_skip; |
| 1998 | Int j; |
| 1999 | |
| 2000 | /* Scan forwards to see if this INCEIP dominates (in the |
| 2001 | technical sense) a later one, AND there are no CCALLs in |
| 2002 | between. If so, skip this one and instead add its count |
| 2003 | with the later one. */ |
| 2004 | can_skip = True; |
| 2005 | j = i+1; |
| 2006 | while (True) { |
| 2007 | if (cb->instrs[j].opcode == CCALL |
| 2008 | || cb->instrs[j].opcode == CALLM) { |
| 2009 | /* CCALL -- we can't skip this INCEIP. */ |
| 2010 | can_skip = False; |
| 2011 | break; |
| 2012 | } |
| 2013 | if (cb->instrs[j].opcode == INCEIP) { |
| 2014 | /* Another INCEIP. Check that the sum will fit. */ |
| 2015 | if (cb->instrs[i].val1 + cb->instrs[j].val1 > 127) |
| 2016 | can_skip = False; |
| 2017 | break; |
| 2018 | } |
| 2019 | if (cb->instrs[j].opcode == JMP || cb->instrs[j].opcode == JIFZ) { |
| 2020 | /* Execution is not guaranteed to get beyond this |
| 2021 | point. Give up. */ |
| 2022 | can_skip = False; |
| 2023 | break; |
| 2024 | } |
| 2025 | j++; |
| 2026 | /* Assertion should hold because all blocks should end in an |
| 2027 | unconditional JMP, so the above test should get us out of |
| 2028 | the loop at the end of a block. */ |
| 2029 | vg_assert(j < cb->used); |
| 2030 | } |
| 2031 | if (can_skip) { |
| 2032 | /* yay! Accumulate the delta into the next INCEIP. */ |
| 2033 | // VG_(printf)("skip INCEIP %d\n", cb->instrs[i].val1); |
| 2034 | vg_assert(j > i); |
| 2035 | vg_assert(j < cb->used); |
| 2036 | vg_assert(cb->instrs[j].opcode == INCEIP); |
| 2037 | vg_assert(cb->instrs[i].opcode == INCEIP); |
| 2038 | vg_assert(cb->instrs[j].tag1 == Lit16); |
| 2039 | vg_assert(cb->instrs[i].tag1 == Lit16); |
| 2040 | cb->instrs[j].val1 += cb->instrs[i].val1; |
| 2041 | /* do nothing now */ |
| 2042 | } else |
| 2043 | # endif |
| 2044 | |
| 2045 | { |
| 2046 | /* no, we really have to do this, alas */ |
| 2047 | // VG_(printf)(" do INCEIP %d\n", cb->instrs[i].val1); |
| 2048 | vg_assert(u->tag1 == Lit16); |
| 2049 | emit_addlit8_offregmem ( u->val1, R_EBP, 4 * VGOFF_(m_eip) ); |
| 2050 | } |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 2051 | break; |
| 2052 | } |
| 2053 | |
| 2054 | case LEA1: { |
| 2055 | vg_assert(u->tag1 == RealReg); |
| 2056 | vg_assert(u->tag2 == RealReg); |
| 2057 | emit_lea_litreg_reg ( u->lit32, u->val1, u->val2 ); |
| 2058 | break; |
| 2059 | } |
| 2060 | |
| 2061 | case LEA2: { |
| 2062 | vg_assert(u->tag1 == RealReg); |
| 2063 | vg_assert(u->tag2 == RealReg); |
| 2064 | vg_assert(u->tag3 == RealReg); |
| 2065 | emit_lea_sib_reg ( u->lit32, u->extra4b, |
| 2066 | u->val1, u->val2, u->val3 ); |
| 2067 | break; |
| 2068 | } |
| 2069 | |
| 2070 | case WIDEN: { |
| 2071 | vg_assert(u->tag1 == RealReg); |
| 2072 | if (u->signed_widen) { |
| 2073 | synth_WIDEN_signed ( u->extra4b, u->size, u->val1 ); |
| 2074 | } else { |
| 2075 | /* no need to generate any code. */ |
| 2076 | } |
| 2077 | break; |
| 2078 | } |
| 2079 | |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 2080 | case STORE: { |
| 2081 | vg_assert(u->tag1 == RealReg); |
| 2082 | vg_assert(u->tag2 == RealReg); |
| 2083 | synth_mov_reg_memreg ( u->size, u->val1, u->val2 ); |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 2084 | break; |
| 2085 | } |
| 2086 | |
| 2087 | case LOAD: { |
| 2088 | vg_assert(u->tag1 == RealReg); |
| 2089 | vg_assert(u->tag2 == RealReg); |
| 2090 | synth_mov_regmem_reg ( u->size, u->val1, u->val2 ); |
| 2091 | break; |
| 2092 | } |
| 2093 | |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 2094 | case GET: { |
| 2095 | vg_assert(u->tag1 == ArchReg || u->tag1 == SpillNo); |
| 2096 | vg_assert(u->tag2 == RealReg); |
| 2097 | synth_mov_offregmem_reg ( |
| 2098 | u->size, |
| 2099 | spillOrArchOffset( u->size, u->tag1, u->val1 ), |
| 2100 | R_EBP, |
| 2101 | u->val2 |
| 2102 | ); |
| 2103 | break; |
| 2104 | } |
| 2105 | |
| 2106 | case PUT: { |
| 2107 | vg_assert(u->tag2 == ArchReg || u->tag2 == SpillNo); |
| 2108 | vg_assert(u->tag1 == RealReg); |
| 2109 | if (u->tag2 == ArchReg |
| 2110 | && u->val2 == R_ESP |
| 2111 | && u->size == 4 |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 2112 | && (VG_(track_events).new_mem_stack || |
| 2113 | VG_(track_events).new_mem_stack_aligned || |
| 2114 | VG_(track_events).die_mem_stack || |
| 2115 | VG_(track_events).die_mem_stack_aligned || |
| 2116 | VG_(track_events).post_mem_write)) |
| 2117 | { |
| 2118 | synth_handle_esp_assignment ( i, u->val1, regs_live_before, |
| 2119 | u->regs_live_after ); |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 2120 | } |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 2121 | else { |
| 2122 | synth_mov_reg_offregmem ( |
| 2123 | u->size, |
| 2124 | u->val1, |
| 2125 | spillOrArchOffset( u->size, u->tag2, u->val2 ), |
| 2126 | R_EBP |
| 2127 | ); |
| 2128 | } |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 2129 | break; |
| 2130 | } |
| 2131 | |
sewardj | e104247 | 2002-09-30 12:33:11 +0000 | [diff] [blame] | 2132 | case GETSEG: { |
| 2133 | vg_assert(u->tag1 == ArchRegS); |
| 2134 | vg_assert(u->tag2 == RealReg); |
| 2135 | vg_assert(u->size == 2); |
| 2136 | synth_mov_offregmem_reg ( |
| 2137 | 4, |
| 2138 | segRegOffset( u->val1 ), |
| 2139 | R_EBP, |
| 2140 | u->val2 |
| 2141 | ); |
| 2142 | break; |
| 2143 | } |
| 2144 | |
| 2145 | case PUTSEG: { |
| 2146 | vg_assert(u->tag1 == RealReg); |
| 2147 | vg_assert(u->tag2 == ArchRegS); |
| 2148 | vg_assert(u->size == 2); |
| 2149 | synth_mov_reg_offregmem ( |
| 2150 | 4, |
| 2151 | u->val1, |
| 2152 | segRegOffset( u->val2 ), |
| 2153 | R_EBP |
| 2154 | ); |
| 2155 | break; |
| 2156 | } |
| 2157 | |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 2158 | case GETF: { |
| 2159 | vg_assert(u->size == 2 || u->size == 4); |
| 2160 | vg_assert(u->tag1 == RealReg); |
| 2161 | synth_mov_offregmem_reg ( |
| 2162 | u->size, |
| 2163 | eflagsOffset(), |
| 2164 | R_EBP, |
| 2165 | u->val1 |
| 2166 | ); |
| 2167 | break; |
| 2168 | } |
| 2169 | |
| 2170 | case PUTF: { |
| 2171 | vg_assert(u->size == 2 || u->size == 4); |
| 2172 | vg_assert(u->tag1 == RealReg); |
| 2173 | synth_mov_reg_offregmem ( |
| 2174 | u->size, |
| 2175 | u->val1, |
| 2176 | eflagsOffset(), |
| 2177 | R_EBP |
| 2178 | ); |
| 2179 | break; |
| 2180 | } |
| 2181 | |
| 2182 | case MOV: { |
| 2183 | vg_assert(u->tag1 == RealReg || u->tag1 == Literal); |
| 2184 | vg_assert(u->tag2 == RealReg); |
| 2185 | switch (u->tag1) { |
| 2186 | case RealReg: vg_assert(u->size == 4); |
| 2187 | if (u->val1 != u->val2) |
| 2188 | synth_movl_reg_reg ( u->val1, u->val2 ); |
| 2189 | break; |
| 2190 | case Literal: synth_mov_lit_reg ( u->size, u->lit32, u->val2 ); |
| 2191 | break; |
njn | e427a66 | 2002-10-02 11:08:25 +0000 | [diff] [blame] | 2192 | default: VG_(core_panic)("emitUInstr:mov"); |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 2193 | } |
| 2194 | break; |
| 2195 | } |
| 2196 | |
sewardj | e104247 | 2002-09-30 12:33:11 +0000 | [diff] [blame] | 2197 | case USESEG: { |
| 2198 | /* Lazy: copy all three vals; synth_ccall ignores any unnecessary |
| 2199 | ones. */ |
sewardj | d077f53 | 2002-09-30 21:52:50 +0000 | [diff] [blame] | 2200 | UInt argv[] = { u->val1, u->val2 }; |
| 2201 | UInt tagv[] = { RealReg, RealReg }; |
sewardj | e104247 | 2002-09-30 12:33:11 +0000 | [diff] [blame] | 2202 | UInt ret_reg = u->val2; |
| 2203 | |
| 2204 | vg_assert(u->tag1 == RealReg); |
| 2205 | vg_assert(u->tag2 == RealReg); |
| 2206 | vg_assert(u->size == 0); |
| 2207 | |
| 2208 | VG_(synth_ccall) ( (Addr) & VG_(do_useseg), |
| 2209 | 2, /* args */ |
| 2210 | 0, /* regparms_n */ |
| 2211 | argv, tagv, |
| 2212 | ret_reg, regs_live_before, u->regs_live_after ); |
| 2213 | break; |
| 2214 | } |
| 2215 | |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 2216 | case XOR: |
| 2217 | case OR: |
| 2218 | case AND: |
| 2219 | case SUB: |
njn | 5a74eb8 | 2002-08-06 20:56:40 +0000 | [diff] [blame] | 2220 | case ADD: |
| 2221 | vg_assert(! readFlagUse ( u )); |
| 2222 | /* fall thru */ |
| 2223 | case SBB: |
| 2224 | case ADC: { |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 2225 | vg_assert(u->tag2 == RealReg); |
| 2226 | switch (u->tag1) { |
| 2227 | case Literal: synth_nonshiftop_lit_reg ( |
njn | 5a74eb8 | 2002-08-06 20:56:40 +0000 | [diff] [blame] | 2228 | readFlagUse(u), writeFlagUse(u), |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 2229 | u->opcode, u->size, u->lit32, u->val2 ); |
| 2230 | break; |
| 2231 | case RealReg: synth_nonshiftop_reg_reg ( |
njn | 5a74eb8 | 2002-08-06 20:56:40 +0000 | [diff] [blame] | 2232 | readFlagUse(u), writeFlagUse(u), |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 2233 | u->opcode, u->size, u->val1, u->val2 ); |
| 2234 | break; |
| 2235 | case ArchReg: synth_nonshiftop_offregmem_reg ( |
njn | 5a74eb8 | 2002-08-06 20:56:40 +0000 | [diff] [blame] | 2236 | readFlagUse(u), writeFlagUse(u), |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 2237 | u->opcode, u->size, |
| 2238 | spillOrArchOffset( u->size, u->tag1, u->val1 ), |
| 2239 | R_EBP, |
| 2240 | u->val2 ); |
| 2241 | break; |
njn | e427a66 | 2002-10-02 11:08:25 +0000 | [diff] [blame] | 2242 | default: VG_(core_panic)("emitUInstr:non-shift-op"); |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 2243 | } |
| 2244 | break; |
| 2245 | } |
| 2246 | |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 2247 | case ROR: |
| 2248 | case ROL: |
| 2249 | case SAR: |
| 2250 | case SHR: |
| 2251 | case SHL: { |
njn | 5a74eb8 | 2002-08-06 20:56:40 +0000 | [diff] [blame] | 2252 | vg_assert(! readFlagUse ( u )); |
| 2253 | /* fall thru */ |
| 2254 | case RCR: |
| 2255 | case RCL: |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 2256 | vg_assert(u->tag2 == RealReg); |
| 2257 | switch (u->tag1) { |
| 2258 | case Literal: synth_shiftop_lit_reg ( |
njn | 5a74eb8 | 2002-08-06 20:56:40 +0000 | [diff] [blame] | 2259 | readFlagUse(u), writeFlagUse(u), |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 2260 | u->opcode, u->size, u->lit32, u->val2 ); |
| 2261 | break; |
| 2262 | case RealReg: synth_shiftop_reg_reg ( |
njn | 5a74eb8 | 2002-08-06 20:56:40 +0000 | [diff] [blame] | 2263 | readFlagUse(u), writeFlagUse(u), |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 2264 | u->opcode, u->size, u->val1, u->val2 ); |
| 2265 | break; |
njn | e427a66 | 2002-10-02 11:08:25 +0000 | [diff] [blame] | 2266 | default: VG_(core_panic)("emitUInstr:non-shift-op"); |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 2267 | } |
| 2268 | break; |
| 2269 | } |
| 2270 | |
| 2271 | case INC: |
| 2272 | case DEC: |
| 2273 | case NEG: |
| 2274 | case NOT: |
| 2275 | vg_assert(u->tag1 == RealReg); |
njn | 5a74eb8 | 2002-08-06 20:56:40 +0000 | [diff] [blame] | 2276 | vg_assert(! readFlagUse ( u )); |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 2277 | synth_unaryop_reg ( |
njn | 5a74eb8 | 2002-08-06 20:56:40 +0000 | [diff] [blame] | 2278 | writeFlagUse(u), u->opcode, u->size, u->val1 ); |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 2279 | break; |
| 2280 | |
| 2281 | case BSWAP: |
| 2282 | vg_assert(u->tag1 == RealReg); |
| 2283 | vg_assert(u->size == 4); |
njn | 4ba5a79 | 2002-09-30 10:23:54 +0000 | [diff] [blame] | 2284 | vg_assert(!VG_(any_flag_use)(u)); |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 2285 | emit_bswapl_reg ( u->val1 ); |
| 2286 | break; |
| 2287 | |
| 2288 | case CMOV: |
| 2289 | vg_assert(u->tag1 == RealReg); |
| 2290 | vg_assert(u->tag2 == RealReg); |
| 2291 | vg_assert(u->cond != CondAlways); |
| 2292 | vg_assert(u->size == 4); |
| 2293 | synth_cmovl_reg_reg ( u->cond, u->val1, u->val2 ); |
| 2294 | break; |
| 2295 | |
| 2296 | case JMP: { |
| 2297 | vg_assert(u->tag2 == NoValue); |
| 2298 | vg_assert(u->tag1 == RealReg || u->tag1 == Literal); |
| 2299 | if (u->cond == CondAlways) { |
sewardj | 2e93c50 | 2002-04-12 11:12:52 +0000 | [diff] [blame] | 2300 | switch (u->tag1) { |
| 2301 | case RealReg: |
| 2302 | synth_jmp_reg ( u->val1, u->jmpkind ); |
| 2303 | break; |
| 2304 | case Literal: |
| 2305 | synth_jmp_lit ( u->lit32, u->jmpkind ); |
| 2306 | break; |
| 2307 | default: |
njn | e427a66 | 2002-10-02 11:08:25 +0000 | [diff] [blame] | 2308 | VG_(core_panic)("emitUInstr(JMP, unconditional, default)"); |
sewardj | 2e93c50 | 2002-04-12 11:12:52 +0000 | [diff] [blame] | 2309 | break; |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 2310 | } |
| 2311 | } else { |
sewardj | 2e93c50 | 2002-04-12 11:12:52 +0000 | [diff] [blame] | 2312 | switch (u->tag1) { |
| 2313 | case RealReg: |
njn | e427a66 | 2002-10-02 11:08:25 +0000 | [diff] [blame] | 2314 | VG_(core_panic)("emitUInstr(JMP, conditional, RealReg)"); |
sewardj | 2e93c50 | 2002-04-12 11:12:52 +0000 | [diff] [blame] | 2315 | break; |
| 2316 | case Literal: |
| 2317 | vg_assert(u->jmpkind == JmpBoring); |
| 2318 | synth_jcond_lit ( u->cond, u->lit32 ); |
| 2319 | break; |
| 2320 | default: |
njn | e427a66 | 2002-10-02 11:08:25 +0000 | [diff] [blame] | 2321 | VG_(core_panic)("emitUInstr(JMP, conditional, default)"); |
sewardj | 2e93c50 | 2002-04-12 11:12:52 +0000 | [diff] [blame] | 2322 | break; |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 2323 | } |
| 2324 | } |
| 2325 | break; |
| 2326 | } |
| 2327 | |
| 2328 | case JIFZ: |
| 2329 | vg_assert(u->tag1 == RealReg); |
| 2330 | vg_assert(u->tag2 == Literal); |
| 2331 | vg_assert(u->size == 4); |
| 2332 | synth_jmp_ifzero_reg_lit ( u->val1, u->lit32 ); |
| 2333 | break; |
| 2334 | |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 2335 | case PUSH: |
| 2336 | vg_assert(u->tag1 == RealReg); |
| 2337 | vg_assert(u->tag2 == NoValue); |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 2338 | VG_(emit_pushv_reg) ( 4, u->val1 ); |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 2339 | break; |
| 2340 | |
| 2341 | case POP: |
| 2342 | vg_assert(u->tag1 == RealReg); |
| 2343 | vg_assert(u->tag2 == NoValue); |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 2344 | VG_(emit_popv_reg) ( 4, u->val1 ); |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 2345 | break; |
| 2346 | |
| 2347 | case CALLM: |
| 2348 | vg_assert(u->tag1 == Lit16); |
| 2349 | vg_assert(u->tag2 == NoValue); |
| 2350 | vg_assert(u->size == 0); |
njn | 5a74eb8 | 2002-08-06 20:56:40 +0000 | [diff] [blame] | 2351 | if (readFlagUse ( u )) |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 2352 | emit_get_eflags(); |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 2353 | VG_(synth_call) ( False, u->val1 ); |
njn | 5a74eb8 | 2002-08-06 20:56:40 +0000 | [diff] [blame] | 2354 | if (writeFlagUse ( u )) |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 2355 | emit_put_eflags(); |
| 2356 | break; |
| 2357 | |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 2358 | case CCALL: { |
sewardj | e104247 | 2002-09-30 12:33:11 +0000 | [diff] [blame] | 2359 | /* If you change this, remember to change USESEG above, since |
| 2360 | that's just a copy of this, slightly simplified. */ |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 2361 | /* Lazy: copy all three vals; synth_ccall ignores any unnecessary |
| 2362 | ones. */ |
| 2363 | UInt argv[] = { u->val1, u->val2, u->val3 }; |
| 2364 | UInt tagv[] = { RealReg, RealReg, RealReg }; |
| 2365 | UInt ret_reg = ( u->has_ret_val ? u->val3 : INVALID_REALREG ); |
| 2366 | |
| 2367 | if (u->argc >= 1) vg_assert(u->tag1 == RealReg); |
| 2368 | else vg_assert(u->tag1 == NoValue); |
| 2369 | if (u->argc >= 2) vg_assert(u->tag2 == RealReg); |
| 2370 | else vg_assert(u->tag2 == NoValue); |
| 2371 | if (u->argc == 3 || u->has_ret_val) vg_assert(u->tag3 == RealReg); |
| 2372 | else vg_assert(u->tag3 == NoValue); |
njn | 6431be7 | 2002-07-28 09:53:34 +0000 | [diff] [blame] | 2373 | vg_assert(u->size == 0); |
| 2374 | |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 2375 | VG_(synth_ccall) ( u->lit32, u->argc, u->regparms_n, argv, tagv, |
| 2376 | ret_reg, regs_live_before, u->regs_live_after ); |
njn | 6431be7 | 2002-07-28 09:53:34 +0000 | [diff] [blame] | 2377 | break; |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 2378 | } |
sewardj | e104247 | 2002-09-30 12:33:11 +0000 | [diff] [blame] | 2379 | |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 2380 | case CLEAR: |
| 2381 | vg_assert(u->tag1 == Lit16); |
| 2382 | vg_assert(u->tag2 == NoValue); |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 2383 | VG_(emit_add_lit_to_esp) ( u->val1 ); |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 2384 | break; |
| 2385 | |
| 2386 | case CC2VAL: |
| 2387 | vg_assert(u->tag1 == RealReg); |
| 2388 | vg_assert(u->tag2 == NoValue); |
njn | 4ba5a79 | 2002-09-30 10:23:54 +0000 | [diff] [blame] | 2389 | vg_assert(VG_(any_flag_use)(u)); |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 2390 | synth_setb_reg ( u->val1, u->cond ); |
| 2391 | break; |
| 2392 | |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 2393 | case FPU_R: |
| 2394 | case FPU_W: |
| 2395 | vg_assert(u->tag1 == Lit16); |
| 2396 | vg_assert(u->tag2 == RealReg); |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 2397 | synth_fpu_regmem ( (u->val1 >> 8) & 0xFF, |
| 2398 | u->val1 & 0xFF, |
| 2399 | u->val2 ); |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 2400 | break; |
| 2401 | |
| 2402 | case FPU: |
| 2403 | vg_assert(u->tag1 == Lit16); |
| 2404 | vg_assert(u->tag2 == NoValue); |
njn | 5a74eb8 | 2002-08-06 20:56:40 +0000 | [diff] [blame] | 2405 | if (readFlagUse ( u )) |
sewardj | 4a7456e | 2002-03-24 13:52:19 +0000 | [diff] [blame] | 2406 | emit_get_eflags(); |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 2407 | synth_fpu_no_mem ( (u->val1 >> 8) & 0xFF, |
| 2408 | u->val1 & 0xFF ); |
njn | 5a74eb8 | 2002-08-06 20:56:40 +0000 | [diff] [blame] | 2409 | if (writeFlagUse ( u )) |
sewardj | 4a7456e | 2002-03-24 13:52:19 +0000 | [diff] [blame] | 2410 | emit_put_eflags(); |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 2411 | break; |
| 2412 | |
| 2413 | default: |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 2414 | if (VG_(needs).extended_UCode) |
njn | 4ba5a79 | 2002-09-30 10:23:54 +0000 | [diff] [blame] | 2415 | SK_(emit_XUInstr)(u, regs_live_before); |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 2416 | else { |
| 2417 | VG_(printf)("\nError:\n" |
| 2418 | " unhandled opcode: %u. Perhaps " |
| 2419 | " VG_(needs).extended_UCode should be set?\n", |
| 2420 | u->opcode); |
njn | 4ba5a79 | 2002-09-30 10:23:54 +0000 | [diff] [blame] | 2421 | VG_(pp_UInstr)(0,u); |
njn | e427a66 | 2002-10-02 11:08:25 +0000 | [diff] [blame] | 2422 | VG_(core_panic)("emitUInstr: unimplemented opcode"); |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 2423 | } |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 2424 | } |
| 2425 | |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 2426 | /* Update UInstr histogram */ |
| 2427 | vg_assert(u->opcode < 100); |
| 2428 | histogram[u->opcode].counts++; |
| 2429 | histogram[u->opcode].size += (emitted_code_used - old_emitted_code_used); |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 2430 | } |
| 2431 | |
| 2432 | |
| 2433 | /* Emit x86 for the ucode in cb, returning the address of the |
| 2434 | generated code and setting *nbytes to its size. */ |
| 2435 | UChar* VG_(emit_code) ( UCodeBlock* cb, Int* nbytes ) |
| 2436 | { |
| 2437 | Int i; |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 2438 | UChar regs_live_before = 0; /* No regs live at BB start */ |
| 2439 | |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 2440 | emitted_code_used = 0; |
| 2441 | emitted_code_size = 500; /* reasonable initial size */ |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 2442 | emitted_code = VG_(arena_malloc)(VG_AR_JITTER, emitted_code_size); |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 2443 | |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 2444 | if (dis) VG_(printf)("Generated x86 code:\n"); |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 2445 | |
| 2446 | for (i = 0; i < cb->used; i++) { |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 2447 | UInstr* u = &cb->instrs[i]; |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 2448 | if (cb->instrs[i].opcode != NOP) { |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 2449 | |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 2450 | /* Check on the sanity of this insn. */ |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 2451 | Bool sane = VG_(saneUInstr)( False, False, u ); |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 2452 | if (!sane) { |
| 2453 | VG_(printf)("\ninsane instruction\n"); |
njn | 4ba5a79 | 2002-09-30 10:23:54 +0000 | [diff] [blame] | 2454 | VG_(up_UInstr)( i, u ); |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 2455 | } |
| 2456 | vg_assert(sane); |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 2457 | emitUInstr( cb, i, regs_live_before ); |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 2458 | } |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 2459 | regs_live_before = u->regs_live_after; |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 2460 | } |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 2461 | if (dis) VG_(printf)("\n"); |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 2462 | |
| 2463 | /* Returns a pointer to the emitted code. This will have to be |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 2464 | copied by the caller into the translation cache, and then freed */ |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 2465 | *nbytes = emitted_code_used; |
| 2466 | return emitted_code; |
| 2467 | } |
| 2468 | |
njn25 | e49d8e7 | 2002-09-23 09:36:25 +0000 | [diff] [blame] | 2469 | #undef dis |
| 2470 | |
sewardj | de4a1d0 | 2002-03-22 01:27:54 +0000 | [diff] [blame] | 2471 | /*--------------------------------------------------------------------*/ |
| 2472 | /*--- end vg_from_ucode.c ---*/ |
| 2473 | /*--------------------------------------------------------------------*/ |