1. 24f3579 by njn · 22 years ago
  2. 563f96f Renamed VG_(nameCondcode)() as VG_(name_UCondcode)() to make it consistent by njn · 22 years ago
  3. 5b3b0f3 by njn · 22 years ago
  4. 279236e Implement ADC Ib, AL. by sewardj · 22 years ago
  5. 48987df Fix bug in MOV Iv,Ev when Ev is a reg. Noticed by Magnus Christensson by sewardj · 22 years ago
  6. 5109643 by sewardj · 22 years ago
  7. 810086f by njn · 22 years ago
  8. 7a5ebcf by sewardj · 22 years ago
  9. 6d12f91 merge rev 1.29.2.8: by sewardj · 22 years ago
  10. 1cff0e0 merge rev 1.29.2.6: by sewardj · 22 years ago
  11. 6ca4c02 merge rev 1.29.2.7: by sewardj · 22 years ago
  12. ac6c176 by njn · 22 years ago
  13. be4015a vg_to_ucode: deploy handleSegOverride() in a couple of places where an by sewardj · 22 years ago
  14. c953984 by njn · 22 years ago
  15. e427a66 by njn · 22 years ago
  16. d077f53 Teach memcheck about instrumenting {GET,PUT,USE}SEG. by sewardj · 22 years ago
  17. e104247 by sewardj · 22 years ago
  18. 4ba5a79 by njn · 22 years ago
  19. c5d385d Get rid of nvidia_moan(); soon we might not have anything to moan about. by sewardj · 22 years ago
  20. 72bbd22 merge rev 1.29.2.5: by sewardj · 22 years ago
  21. e49d8e7 Files updated, added and removed in order to turn the ERASER branch into HEAD by njn25 · 22 years ago
  22. 12ffdac Print more helpful message on JIT failure to handle insns starting with 0x0F. by sewardj · 22 years ago
  23. 35a916c Support for x86 insn fldenv. by sewardj · 22 years ago
  24. 7cba715 by sewardj · 22 years ago
  25. 2a8141a Implement fnstenv (store FPU environment, but not regs AIUI) (Jeff Epler) by sewardj · 22 years ago
  26. 7d78e78 Implement CLC and STC (Pascal Massimino <pmassimi@ilog.fr>). by sewardj · 22 years ago
  27. a4b87f6 Implement ADC Eb,Gb. Truly an unpopular instruction if it took anyone this by sewardj · 22 years ago
  28. 363e606 Implement x86 insn popl m32. (Nikolay Igotti ) by sewardj · 22 years ago
  29. 95621db Yesterday's push/pop merging optimisations break the cache profiler: by sewardj · 22 years ago
  30. cfc39b2 Complain about NVidia's libGL.so also when an 0x8C opcode is encountered. by sewardj · 22 years ago
  31. e9c06f1 Implement SBB Ib, AL. by sewardj · 22 years ago
  32. 64a8cc4 Do LODSW / LODSL. (Sami Farin) by sewardj · 22 years ago
  33. a0f921a Only show the giant-basic-block message at verbosity >= 2. by sewardj · 22 years ago
  34. 4f51f9a Generate better ucode for back-to-back sequences of register pushes and by sewardj · 22 years ago
  35. 9316cba Improve accuracy of simulation of bsf/bsr instructions when the word by sewardj · 22 years ago
  36. 4f9c934 by njn · 22 years ago
  37. 5716dbb by sewardj · 22 years ago
  38. 969129d Add JCond-32 NP (long jump when parity odd) and CMOV NP too. by sewardj · 22 years ago
  39. 8d32be7 by sewardj · 22 years ago
  40. 79be106 Get rid of the muraroa.demon.co.uk references since that account is by sewardj · 22 years ago
  41. c7529c3 by sewardj · 22 years ago
  42. 0ece28b by sewardj · 22 years ago
  43. 22bafd9 by sewardj · 22 years ago
  44. 7f2a8bf by sewardj · 22 years ago
  45. 2e93c50 by sewardj · 22 years ago
  46. 4a7456e Detect FPU instructions which set %EFLAGS and mark the resulting by sewardj · 22 years ago
  47. fe8a166 Implement DAA as well as DAS. Byrial Jensen <byrial@image.dk> by sewardj · 22 years ago
  48. 3a72df0 (merge from 20020320) by sewardj · 22 years ago
  49. 4d0ab1f (merge from 20020320) Implement x86 das instruction. by sewardj · 22 years ago
  50. de4a1d0 Initial revision by sewardj · 22 years ago