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gerrit-public.fairphone.software / fp2-dev / platform / external / valgrind / ca82cc01fb1580551144b69d3f17213a80d952e1 / coregrind / vg_to_ucode.c
  1. 3b38c1d Increase the size of M_VG_ERRTXT from 512B to 4KB, increasing the size of C++ by nethercote · 20 years ago
  2. f1e5e15 by nethercote · 20 years ago
  3. b253abe by nethercote · 20 years ago
  4. 885dd91 by nethercote · 20 years ago
  5. 1f17f7c Move the decoding of SFENCE out of the SSE only part of disInstr as it by thughes · 20 years ago
  6. 2416868 Fix scary bug causing mis-identification of SSE stores vs loads. by jseward · 20 years ago
  7. b60be8b Fix extremely obscure bug in xadd picked up by QEMU's test suite. The by jseward · 20 years ago
  8. 43bfaee gcc sometimes generates "sbbl %reg,%reg" to convert the carry flag by jseward · 20 years ago
  9. 85cf45e Support FBLD, FBSTP. Patch courtesy of Jani Monoses. by nethercote · 20 years ago
  10. 4ee6496 Added VG_(cpuid) to replace the various bits of inline assembler used by thughes · 20 years ago
  11. 5305d41 Added "repne movs", not official but seems to occur. Also restructured the by nethercote · 20 years ago
  12. 5689938 When printing code and an insane instruction is encountered, ugly-print (giving by nethercote · 20 years ago
  13. 911cc37 Introduce uWiden, similar to uCCall, uCond, etc. by nethercote · 20 years ago
  14. 165ad33 Added comment clarifying RDTSC. by nethercote · 20 years ago
  15. 1052ce0 Fixed decoding of x87 instructions to handle those taking 16 bit by thughes · 20 years ago
  16. 96b466a Move the handling of PSHUFW from the SSE code to the MMX code so that by thughes · 20 years ago
  17. 91e082b Treat INT with an operand other than 0x80 as an undefined instruction. by thughes · 20 years ago
  18. 0ee72ef Add support for 16 bit pushes and pops of segment registers to fix bug #76762. by thughes · 20 years ago
  19. bd12691 Patch from Tom Hughes: by nethercote · 20 years ago
  20. 1018bdd Heroic patch from Tom Hughes: by nethercote · 20 years ago
  21. 2757417 Rearrange CPUID again. Moved most of the helper logic into C, since by fitzhardinge · 21 years ago
  22. e860112 by nethercote · 21 years ago
  23. 0df2ac2 Virtualize CPUID. Rather than just using the host CPU's CPUID, by fitzhardinge · 21 years ago
  24. c2dbbac Fix bug 73219. This adds a general mechanism for querying the host CPU's by fitzhardinge · 21 years ago
  25. 7cc9c23 Convert "skin" to "tool" in various places; almost entirely within comments, by nethercote · 21 years ago
  26. 46c7b8d Patch to add support for the alternate MOVQ encoding, from Tom Hughes. by nethercote · 21 years ago
  27. b1affa8 Patch from Tom Hughes, for bug 72643: by nethercote · 21 years ago
  28. 33dbc12 yet another SSE insn (rsqrtss) by mueller · 21 years ago
  29. fca6018 Support for FXSAVE/FXRSTOR (Tom Hughes). Fixes #71180. by jseward · 21 years ago
  30. bb1c991 Updated copyright dates for 2004. Also added a couple of missing headers and by nethercote · 21 years ago
  31. 97da476 movntpd/movntps support (patch by Tom Hughes) CCMAIL: 69782-done@bugs.kde.org by mueller · 21 years ago
  32. f217c73 implement cmpxchg8b, patch by Tom Hughes. CCMAIL: 69688-done@bugs.kde.org by mueller · 21 years ago
  33. a02f881 Make rep; nop (pause) yield the thread. Based on a patch by Tom Hughes; by fitzhardinge · 21 years ago
  34. 98abfc7 This jumbo-checkin is the Full Virtualization checkin. This eliminates by fitzhardinge · 21 years ago
  35. 382a892 by nethercote · 21 years ago
  36. cf539de Factor out repeated code for LOOP{E,NE} by nethercote · 21 years ago
  37. e33453f by nethercote · 21 years ago
  38. 8400154 Fix comment by nethercote · 21 years ago
  39. c29dcb5 add prefetch(w) support - the 3dnow! version of it. doesn't hurt by mueller · 21 years ago
  40. aa5c626 SHUFPD support by mueller · 21 years ago
  41. aa5fd3c add CVTPD2PS support, based on patch by Josef Weidendorfer by mueller · 21 years ago
  42. 07bf60a Move var declarations to start of block, for older versions of gcc. by nethercote · 21 years ago
  43. 561f6e0 Implemented PUSH/POP %{FS,GS}, and PUSH %CS (Nb: there is no POP %CS). Based by nethercote · 21 years ago
  44. e343649 Add SQRTSS: square root of scalar float by sewardj · 21 years ago
  45. 632b8a1 Implement UNPCKLPS and UNPCKHPS and improve UNPCKLPD. by sewardj · 21 years ago
  46. 77d30a2 SSE/SSE2 fixes needed to run the entire test suite of the GNU by sewardj · 21 years ago
  47. b270ea5 ucomisd support by daywalker · 21 years ago
  48. bb6ac7c Implement MOVNTDQ (a SSE/SSE2 insn) by sewardj · 21 years ago
  49. d1b5b1d Implement repe scas. by jsgf · 21 years ago
  50. 5efa4fd This creates a new UInstr for multiply. This is mainly so that memcheck by jsgf · 21 years ago
  51. 8399f6a Fixed "pop (%esp)", which must increment %esp before using it to calculate the by njn · 21 years ago
  52. 5428450 Added (trivially) support for "push %ss". Minimally tested, along with "pop by njn · 21 years ago
  53. 9e4c1f9 Added (trivally) support for "pop %ss". Untested. by njn · 21 years ago
  54. 737a375 Implement DIVPS/DIVPD (Tom Hughes <thh@cyberscience.com>) by sewardj · 21 years ago
  55. 79aad84 inc/dec %ESP support MERGE TO STABLE by daywalker · 21 years ago
  56. 8988f93 Implement MOVQ -- move 8 bytes of XMM reg or mem to XMM reg. by sewardj · 21 years ago
  57. b18d253 implement IN and OUT opcodes. by daywalker · 21 years ago
  58. 7443bb5 Add support for "movl imm32, %esp". Needed for 'grinding vg_startup.S :) by njn · 21 years ago
  59. 5d945de implement a couple more instructions. I've mailed this patch to Julian by daywalker · 21 years ago
  60. 7fd598c by njn · 21 years ago
  61. 6c84655 by njn · 21 years ago
  62. a51cc09 Handle XCHG eAX,eBP. by sewardj · 21 years ago
  63. 3058e04 The Pentium 4 recycles the CS segment override prefix (0x2E) to mean by sewardj · 21 years ago
  64. 7e73e5f spelling fixes by daywalker · 21 years ago
  65. 4395356 Added (trivially) "XCHG eAX,eSP" instruction. by njn · 21 years ago
  66. 2aaa2ca Move two variable declarations to the start of their enclosing blocks. by njn · 21 years ago
  67. 9dd209f A few more SSEs. by sewardj · 21 years ago
  68. 2db567e A few more SSE float (scalar,packed) insns. Something is not right; by sewardj · 21 years ago
  69. 1e86b8b - Add a few more SSE instructions by sewardj · 21 years ago
  70. 095c3bc Add some more SSE/SSE2 floating point instructions. by sewardj · 21 years ago
  71. abf8bf8 - Continue to clear up SSE insn emitters following recent cleanups re by sewardj · 21 years ago
  72. 4fbe6e9 Rename the SSE and MMX uinstrs which read/write integer registers, in by sewardj · 21 years ago
  73. bc148f2 Fill in a whole bunch of boring-ass SSE SIMD-integer insns. by sewardj · 21 years ago
  74. e3891fa Yet more SSE insns. by sewardj · 21 years ago
  75. 6bc4055 - Comment out SSE uinstrs which have not so far been used. by sewardj · 21 years ago
  76. 5d58cb4 Do SSE insns PSRLDQ, PSLLDQ by sewardj · 21 years ago
  77. a453fb0 More SSE instructions. by sewardj · 21 years ago
  78. ea691a1 Add yet more SSE/SSE2 instructions. The party never stops here at by sewardj · 21 years ago
  79. b31b06d Tonight's installment of SSE madness. Add a couple more nasties by sewardj · 21 years ago
  80. 02af6bc Fill in a few more SSE/SSE2 insns, with current aim of being able to by sewardj · 21 years ago
  81. bfa6bce Fix problem with LAHF. by njn · 21 years ago
  82. b7a818d Fixed bug in first attempt at 'lahf'. So much for my supposed testing. by njn · 21 years ago
  83. 4d1a9bf wibble by njn · 21 years ago
  84. d6251f1 by njn · 21 years ago
  85. 35a1779 Add some more SSE insns. by sewardj · 21 years ago
  86. de8aecf Fix a design flaw in the SSE decoder. Remove duplication and by sewardj · 21 years ago
  87. a60be0e Implement enough SSE/SSE2 insns so that all the GL demos in qt-3.1.0 by sewardj · 21 years ago
  88. febaa3b Implement a few SSE instructions, enough to run bzip2 when compiled by sewardj · 21 years ago
  89. 2e9b6a9 Removed statement with no effect. by njn · 21 years ago
  90. 0e1b514 Updated copyright notices for 2003. Only 4 months late. by njn · 21 years ago
  91. d1c9e43 Implement MMX movd where the src is an mmxreg and the dst is an ireg or memory. by sewardj · 21 years ago
  92. d797101 Rationalise ucode generation for 4-byte moves into the MMX unit (movd). by sewardj · 21 years ago
  93. 87c85ee the following small patch adds support for the (ancient and horrible) by sewardj · 21 years ago
  94. 6b46fa8 Fix a couple of missing MMX instructions. As far as I know, the only by sewardj · 21 years ago
  95. ca86001 More MMX stuff, including a bunch of prefetch insns. by sewardj · 21 years ago
  96. 6b627da More C++ syntax leakage fixes. by sewardj · 21 years ago
  97. 1ef2b1d Fix C++ syntax leakage. by sewardj · 21 years ago
  98. 3d7c9c8 by sewardj · 21 years ago
  99. 24f3579 by njn · 21 years ago
  100. 563f96f Renamed VG_(nameCondcode)() as VG_(name_UCondcode)() to make it consistent by njn · 21 years ago