Expand RS vector3 types to vector4.
BUG=5609007
The underlying LLVM implementation for vector3 types does this implicitly. If
RS does not adjust its implementation, we will always be misaligned for any
subsequent data after a vector3 type. We previously inserted padding into the
reflected layers from llvm-rs-cc (hence the skip padding part of this change).
We can safely ignore the padding now that the Java/native code is updated to
use the expanded size. The compiler will also need modification to ensure that
we don't mistakenly skip over any end-of-struct padding.
Fixing the 3 component vector padding problem.
Change-Id: If68af42287deb8f4b28addcd19a9fa314656be44
diff --git a/rsElement.cpp b/rsElement.cpp
index df90ce4..56c31b6 100644
--- a/rsElement.cpp
+++ b/rsElement.cpp
@@ -23,6 +23,7 @@
Element::Element(Context *rsc) : ObjectBase(rsc) {
mBits = 0;
+ mBitsUnpadded = 0;
mFields = NULL;
mFieldCount = 0;
mHasReference = false;
@@ -60,6 +61,18 @@
return total;
}
+size_t Element::getSizeBitsUnpadded() const {
+ if (!mFieldCount) {
+ return mBitsUnpadded;
+ }
+
+ size_t total = 0;
+ for (size_t ct=0; ct < mFieldCount; ct++) {
+ total += mFields[ct].e->mBitsUnpadded * mFields[ct].arraySize;
+ }
+ return total;
+}
+
void Element::dumpLOGV(const char *prefix) const {
ObjectBase::dumpLOGV(prefix);
ALOGV("%s Element: fieldCount: %zu, size bytes: %zu", prefix, mFieldCount, getSizeBytes());
@@ -146,14 +159,18 @@
void Element::compute() {
if (mFieldCount == 0) {
mBits = mComponent.getBits();
+ mBitsUnpadded = mComponent.getBitsUnpadded();
mHasReference = mComponent.isReference();
return;
}
size_t bits = 0;
+ size_t bitsUnpadded = 0;
for (size_t ct=0; ct < mFieldCount; ct++) {
mFields[ct].offsetBits = bits;
+ mFields[ct].offsetBitsUnpadded = bitsUnpadded;
bits += mFields[ct].e->getSizeBits() * mFields[ct].arraySize;
+ bitsUnpadded += mFields[ct].e->getSizeBitsUnpadded() * mFields[ct].arraySize;
if (mFields[ct].e->mHasReference) {
mHasReference = true;