commit 4c56e4505d7b0f66515667edd56ba49c84b63172
author Leonard Mai <leonard.mai@intel.com> Thu Oct 06 12:27:46 2011 -0700
committer Patrick Tjin <pattjin@google.com> Mon Jul 21 20:22:40 2014 -0700
tree 98c66a9a5face9656d72b579ccd24fecc0a75fbf
parent f2932284ab7ac1a0a6ff84025d2b5480eea9a796

bootstub: add cloverview support

Add cloverview support. Also bump up the version to 1.1.

Signed-off-by: Leonard D Mai <leonard.mai@intel.com>

VERSION

diff --git a/VERSION b/VERSION
index 5a9c4df..bfc9838 100644
--- a/VERSION
+++ b/VERSION
@@ -1,3 +1,4 @@
+1.1 add cloverview support. Oct 6, 2011
 1.0 fix alignment issue in SFI mmap searching. Oct 13, 2010
 0.9 support medfield. Jun 9, 2010
 0.8 changed default spi clock to 100mhz Aug 12, 2009

bootstub.c

diff --git a/bootstub.c b/bootstub.c
index bb5a3c8..e115834 100644
--- a/bootstub.c
+++ b/bootstub.c
@@ -154,27 +154,32 @@
 	CR_EBX
 };
 
-#define PENWELL_FAMILY	0x20670
-#define MRST_CPU_CHIP_LINCROFT  1
-#define MRST_CPU_CHIP_PENWELL   2
-
-static int mrst_identify_cpu(void)
+int mrst_identify_cpu(void)
 {
 	u32 regs[4];
 
 	cpuid(1, &regs[CR_EAX], &regs[CR_EBX], &regs[CR_ECX], &regs[CR_EDX]);
 	if ((regs[CR_EAX] & PENWELL_FAMILY) == PENWELL_FAMILY)
 		return MRST_CPU_CHIP_PENWELL;
+	else if ((regs[CR_EAX] & CLOVERVIEW_FAMILY) == CLOVERVIEW_FAMILY)
+		return MRST_CPU_CHIP_CLOVERVIEW;
 	return MRST_CPU_CHIP_LINCROFT;
 }
 
 static void setup_spi(void)
 {
-	if (! *(int *)SPI_TYPE)
+	if (!(*(int *)SPI_TYPE)) {
 		if (mrst_identify_cpu() == MRST_CPU_CHIP_PENWELL) {
 			*(int *)SPI_TYPE = 1;
 			bs_printk("Penwell detected ...\n");
+		} else if (mrst_identify_cpu() == MRST_CPU_CHIP_CLOVERVIEW) {
+			*(int *)SPI_TYPE = 1;
+			bs_printk("Cloverview detected ...\n");
+		} else {
+			*(int *)SPI_TYPE = 1;
+			bs_printk("Lincroft detected ...\n");
 		}
+	}
 }
 
 int bootstub(void)
@@ -182,7 +187,7 @@
 	setup_idt();
 	setup_gdt();
 	setup_spi();
-	bs_printk("Bootstub Version: 1.0 ...\n");
+	bs_printk("Bootstub Version: 1.1 ...\n");
 	setup_boot_params((struct boot_params *)BOOT_PARAMS_OFFSET, 
 		(struct setup_header *)SETUP_HEADER_OFFSET);
 	bs_printk("Jump to kernel 32bit entry ...\n");

bootstub.h

diff --git a/bootstub.h b/bootstub.h
index dbd9dbf..2bab652 100644
--- a/bootstub.h
+++ b/bootstub.h
@@ -4,6 +4,12 @@
 #ifndef _BOOT_STUB_HEAD
 #define _BOOT_STUB_HEAD
 
+#define PENWELL_FAMILY		0x20670
+#define CLOVERVIEW_FAMILY	0x30650
+#define MRST_CPU_CHIP_LINCROFT	1
+#define MRST_CPU_CHIP_PENWELL	2
+#define MRST_CPU_CHIP_CLOVERVIEW 3
+
 #define CMDLINE_OFFSET		0x1100000
 #define BZIMAGE_SIZE_OFFSET	0x1100100
 #define INITRD_SIZE_OFFSET	0x1100104

bootstub.spec

diff --git a/bootstub.spec b/bootstub.spec
index 178e3ab..89df23e 100644
--- a/bootstub.spec
+++ b/bootstub.spec
@@ -1,6 +1,6 @@
 Summary: this package provides bootstub binary for mrst/mfld platform
 Name: bootstub
-Version: 1.0
+Version: 1.1
 Release: 1%{?dist}
 License: GPLv2
 Group: System Environment/Shells

spi-uart.c

diff --git a/spi-uart.c b/spi-uart.c
index 21448b9..7ff8323 100644
--- a/spi-uart.c
+++ b/spi-uart.c
@@ -31,13 +31,22 @@
 
 	switch (*(int *)SPI_TYPE) {
 	case 0:
-		pspi = (struct mrst_spi_reg *)MRST_REGBASE_SPI0;
+		if (mrst_identify_cpu() == MRST_CPU_CHIP_CLOVERVIEW)
+			pspi = (struct mrst_spi_reg *)CTP_REGBASE_SPI0;
+		else
+			pspi = (struct mrst_spi_reg *)MRST_REGBASE_SPI0;
 		break;
 	case 1:
-		pspi = (struct mrst_spi_reg *)MRST_REGBASE_SPI1;
+		if (mrst_identify_cpu() == MRST_CPU_CHIP_CLOVERVIEW)
+			pspi = (struct mrst_spi_reg *)CTP_REGBASE_SPI1;
+		else
+			pspi = (struct mrst_spi_reg *)MRST_REGBASE_SPI1;
 		break;
 	default:
-		pspi = (struct mrst_spi_reg *)MRST_REGBASE_SPI0;
+		if (mrst_identify_cpu() == MRST_CPU_CHIP_CLOVERVIEW)
+			pspi = (struct mrst_spi_reg *)CTP_REGBASE_SPI0;
+		else
+			pspi = (struct mrst_spi_reg *)MRST_REGBASE_SPI0;
 	}
 	/* disable SPI controller first */
 	pspi->ssienr = 0x0;

spi-uart.h

diff --git a/spi-uart.h b/spi-uart.h
index f3fcf0b..21bedd1 100644
--- a/spi-uart.h
+++ b/spi-uart.h
@@ -12,6 +12,10 @@
 #define MRST_REGBASE_SPI1	0xff128400
 #define MRST_REGBASE_SPI2	0xff128800
 
+#define CTP_REGBASE_SPI0	0xff128000
+#define CTP_REGBASE_SPI1	0xff135000
+#define CTP_REGBASE_SPI2	0xff136000
+
 /* HW info for MRST CLk Control Unit, one 32b reg */
 #define MRST_SPI_CLK_BASE	100000000	/* 100m */
 #define MRST_CLK_SPI0_REG	0xff11d86c