commit 90847a8a794a6eedef1f61daab5a9e3afde33c5a
author Mark F. Brown <mark.f.brown@intel.com> Wed Sep 07 18:06:24 2011 -0400
committer Patrick Tjin <pattjin@google.com> Mon Jul 21 20:22:40 2014 -0700
tree 0da46a3a4531cc7a43d20acca98ce3ced107f741
parent aecaba3b298855b0ce93f94897a0e2b5269639a7

SSP: Added SPI UART via SSP5

BZ: 114933

Merrifield uses SPI via SSP rather than a dedicated SPI peripheral
Moved volatile definitions to types.h

Based off code by Courtney A. Drant

Change-Id: I3a8fbe364f2fcf860ac47f431b93868fb7b598d9
Signed-off-by: Mark F. Brown <mark.f.brown@intel.com>
Signed-off-by: Courtney A. Drant <courtney.a.drant@intel.com>
Reviewed-on: http://android.intel.com:8080/112531
Reviewed-by: Fourdan, Olivier <olivier.fourdan@intel.com>
Tested-by: Fourdan, Olivier <olivier.fourdan@intel.com>
Reviewed-by: Fert, Laurent <laurent.fert@intel.com>
Reviewed-by: cactus <cactus@intel.com>
Tested-by: cactus <cactus@intel.com>

ssp-uart.h

diff --git a/ssp-uart.h b/ssp-uart.h
new file mode 100644
index 0000000..8ae6863
--- /dev/null
+++ b/ssp-uart.h
@@ -0,0 +1,32 @@
+#ifndef _SSP_UART
+#define _SSP_UART
+
+#include "types.h"
+
+#define TNG_SSP5_ADDR_BASE      0xFF189000
+
+struct ssp_reg {
+	vu32 SSPx_SSCR0;      // 0x00
+	vu32 SSPx_SSCR1;      // 0x04
+	vu32 SSPx_SSSR;       // 0x08
+	vu32 SSPx_SSITR;      // 0x0C
+	vu32 SSPx_SSDR;       // 0x10
+	vu32 SSPx_DUMMY1;     //0x14
+	vu32 SSPx_DUMMY2;     //0x18
+	vu32 SSPx_DUMMY3;     //0x1c
+	vu32 SSPx_DUMMY4;     //0x20
+	vu32 SSPx_DUMMY5;     //0x24
+	vu32 SSPx_SSTO;       // 0x28
+	vu32 SSPx_SSPSP;      // 0x2C
+	vu32 SSPx_SSTSA;      // 0x30
+	vu32 SSPx_SSRSA;      // 0x34
+	vu32 SSPx_SSTSS;      // 0x38
+	vu32 SSPx_SSACD;      // 0x3C
+	vu32 SSPx_SSCR2;      // 0x40
+	vu32 SSPx_SSFS;       // 0x44
+	vu32 SSPx_FRAME_CNT;  // 0x48
+};
+
+extern void bs_ssp_printk(const char *str);
+
+#endif