dev: gcdb: display: remove macros for MIN and MAX vco frequency
Use variables for MIN and MAX VCO frequencies so that they can
be configured to change the frequency range. Add necessary
condition checks to configure the VCO frequency
range for zero and 90 phase.
Change-Id: Ib6e5deef73b22d05a86c4b5da4f836ee41cb8e49
diff --git a/dev/gcdb/display/gcdb_autopll.c b/dev/gcdb/display/gcdb_autopll.c
index 4a5ca26..2794203 100755
--- a/dev/gcdb/display/gcdb_autopll.c
+++ b/dev/gcdb/display/gcdb_autopll.c
@@ -148,7 +148,7 @@
{
uint32_t refclk = 19200000;
uint32_t vco_rate = pll_data.vco_clock;
- uint32_t tmp;
+ uint32_t tmp, mod;
vco_rate /= 2;
pll_data.dec_start = vco_rate / refclk;
@@ -161,11 +161,22 @@
pll_data.frac_start = tmp;
vco_rate *= 2; /* restore */
- tmp = vco_rate / (refclk / 1000);/* div 1000 first */
- tmp *= 1024;
- tmp /= 1000;
- tmp /= 10;
- pll_data.lock_comp = tmp - 1;
+ if (pll_data.en_vco_zero_phase) {
+ tmp = vco_rate / (refclk / 1000);/* div 1000 first */
+ tmp *= 1024;
+ tmp /= 1000;
+ tmp /= 10;
+ pll_data.lock_comp = tmp - 1;
+ } else {
+ tmp = vco_rate / refclk;
+ mod = vco_rate % refclk;
+ tmp *= 127;
+ mod *= 127;
+ mod /= refclk;
+ tmp += mod;
+ tmp /= 10;
+ pll_data.lock_comp = tmp;
+ }
dprintf(SPEW, "%s: dec_start=0x%x dec_frac=0x%x lock_comp=0x%x\n", __func__,
pll_data.dec_start, pll_data.frac_start, pll_data.lock_comp);
@@ -203,6 +214,24 @@
return NO_ERROR;
}
+#ifndef DISPLAY_EN_20NM_PLL_90_PHASE
+static void config_20nm_pll_vco_range(void)
+{
+ pll_data.vco_min = 300000000;
+ pll_data.vco_max = 1500000000;
+ pll_data.en_vco_zero_phase = 1;
+ dprintf(SPEW, "%s: Configured VCO for zero phase\n", __func__);
+}
+#else
+static void config_20nm_pll_vco_range(void)
+{
+ pll_data.vco_min = 1000000000;
+ pll_data.vco_max = 2000000000;
+ pll_data.en_vco_zero_phase = 0;
+ dprintf(SPEW, "%s: Configured VCO for 90 phase\n", __func__);
+}
+#endif
+
static uint32_t calculate_vco_20nm(uint8_t bpp, uint8_t lanes)
{
uint32_t vco, dsi_clk;
@@ -235,12 +264,12 @@
hr_oclk2 = 4;
/* If bitclock is more than VCO min value */
- if (pll_data.halfbit_clock >= HALF_VCO_MIN_CLOCK_20NM) {
+ if (pll_data.halfbit_clock >= ((pll_data.vco_min) >> 1)) {
/* Direct Mode */
vco = pll_data.halfbit_clock << 1;
/* support vco clock to max value only */
- if (vco > VCO_MAX_CLOCK_20NM)
- vco = VCO_MAX_CLOCK_20NM;
+ if (vco > (pll_data.vco_max))
+ vco = (pll_data.vco_max);
pll_data.directpath = 0x0;
pll_data.byte_clock = vco / 2 / hr_oclk2;
@@ -249,8 +278,8 @@
hr_oclk3 = hr_oclk2 * m / n * bpp_m / bpp_n / lanes;
} else {
/* Indirect Mode */
- mod = VCO_MIN_CLOCK_20NM % (4 * pll_data.halfbit_clock );
- ndiv = VCO_MIN_CLOCK_20NM / (4 * pll_data.halfbit_clock );
+ mod = (pll_data.vco_min) % (4 * pll_data.halfbit_clock );
+ ndiv = (pll_data.vco_min) / (4 * pll_data.halfbit_clock );
if (mod)
ndiv += 1;
@@ -288,6 +317,9 @@
calculate_bitclock(pinfo);
if (pinfo->mipi.mdss_dsi_phy_db->is_pll_20nm)
+ config_20nm_pll_vco_range();
+
+ if (pinfo->mipi.mdss_dsi_phy_db->is_pll_20nm)
ret = calculate_vco_20nm(pinfo->bpp, pinfo->mipi.num_of_lanes);
else
ret = calculate_vco_28nm(pinfo->bpp, pinfo->mipi.num_of_lanes);