diff --git a/arch/arm/crt0.S b/arch/arm/crt0.S
index 3a3d776..a1777f0 100644
--- a/arch/arm/crt0.S
+++ b/arch/arm/crt0.S
@@ -52,6 +52,11 @@
 #if WITH_CPU_EARLY_INIT
 	/* call platform/arch/etc specific init code */
 	bl __cpu_early_init
+
+	/* declare return address as global to avoid using stack */
+.globl _cpu_early_init_complete
+	_cpu_early_init_complete:
+
 #endif
 
 #if (!ENABLE_NANDWRITE)
diff --git a/platform/msm7x30/arch_init.S b/platform/msm7x30/arch_init.S
index 86949ff..8933bb1 100644
--- a/platform/msm7x30/arch_init.S
+++ b/platform/msm7x30/arch_init.S
@@ -313,7 +313,7 @@
         LDR     r5, =0
 
         //; routine complete
-        BX      LR
+        B       _cpu_early_init_complete
 
 .ltorg
 
@@ -459,15 +459,15 @@
 
         //; Make sure Link stack is initialized with branch and links to sequential addresses
         //; This aids in creating a predictable startup environment
-//;       BL      SEQ1
-//;SEQ1:  BL      SEQ2
-//;SEQ2:  BL      SEQ3
-//;SEQ3:  BL      SEQ4
-//;SEQ4:  BL      SEQ5
-//;SEQ5:  BL      SEQ6
-//;SEQ6:  BL      SEQ7
-//;SEQ7:  BL      SEQ8
-//;SEQ8:
+        BL      SEQ1
+SEQ1:   BL      SEQ2
+SEQ2:   BL      SEQ3
+SEQ3:   BL      SEQ4
+SEQ4:   BL      SEQ5
+SEQ5:   BL      SEQ6
+SEQ6:   BL      SEQ7
+SEQ7:   BL      SEQ8
+SEQ8:
 
         //; REMOVE FOLLOWING THREE INSTRUCTIONS WHEN POWER COLLAPSE IS ENA
         //;Make sure the DBGOSLSR[LOCK] bit is cleared to allow access to the debug registers
diff --git a/platform/qsd8k/arch_init.S b/platform/qsd8k/arch_init.S
index a9deb41..1e93696 100644
--- a/platform/qsd8k/arch_init.S
+++ b/platform/qsd8k/arch_init.S
@@ -198,7 +198,7 @@
         LDR     r5, =0
 
         //; routine complete
-        BX      LR
+        B       _cpu_early_init_complete
 
 //; L1 SA settings according to LVT speed
 PVR0F0_0bits:
@@ -406,15 +406,15 @@
 
         //; Make sure Link stack is initialized with branch and links to sequential addresses
         //; This aids in creating a predictable startup environment
-//;       BL      SEQ1
-//;SEQ1:  BL      SEQ2
-//;SEQ2:  BL      SEQ3
-//;SEQ3:  BL      SEQ4
-//;SEQ4:  BL      SEQ5
-//;SEQ5:  BL      SEQ6
-//;SEQ6:  BL      SEQ7
-//;SEQ7:  BL      SEQ8
-//;SEQ8:
+        BL      SEQ1
+SEQ1:   BL      SEQ2
+SEQ2:   BL      SEQ3
+SEQ3:   BL      SEQ4
+SEQ4:   BL      SEQ5
+SEQ5:   BL      SEQ6
+SEQ6:   BL      SEQ7
+SEQ7:   BL      SEQ8
+SEQ8:
 
         //; REMOVE FOLLOWING THREE INSTRUCTIONS WHEN POWER COLLAPSE IS ENA
         //;Make sure the DBGOSLSR[LOCK] bit is cleared to allow access to the debug registers