msm8226: Add support for blsp uart3.
Change-Id: Ibd9f93a0da06d15a5b90604b10803cedf58818f5
diff --git a/platform/msm8226/gpio.c b/platform/msm8226/gpio.c
index b19643c..b869367 100644
--- a/platform/msm8226/gpio.c
+++ b/platform/msm8226/gpio.c
@@ -53,11 +53,12 @@
/* Configure gpio for blsp uart 2 */
void gpio_config_uart_dm(uint8_t id)
{
- /* configure rx gpio */
- gpio_tlmm_config(5, 2, GPIO_INPUT, GPIO_NO_PULL,
+ /* Configure GPIOs for BLSP1 UART3. */
+ /* configure rx gpio */
+ gpio_tlmm_config(9, 2, GPIO_INPUT, GPIO_NO_PULL,
GPIO_8MA, GPIO_DISABLE);
- /* configure tx gpio */
- gpio_tlmm_config(4, 2, GPIO_OUTPUT, GPIO_NO_PULL,
+ /* configure tx gpio */
+ gpio_tlmm_config(8, 2, GPIO_OUTPUT, GPIO_NO_PULL,
GPIO_8MA, GPIO_DISABLE);
}
diff --git a/platform/msm8226/include/platform/iomap.h b/platform/msm8226/include/platform/iomap.h
index 9d47d11..7f3d1a1 100644
--- a/platform/msm8226/include/platform/iomap.h
+++ b/platform/msm8226/include/platform/iomap.h
@@ -88,15 +88,8 @@
#define MPM2_MPM_CTRL_BASE 0xFC4A1000
#define MPM2_MPM_PS_HOLD 0xFC4AB000
-/* CE 2 */
-#define GCC_CE2_BCR (CLK_CTL_BASE + 0x1080)
-#define GCC_CE2_CMD_RCGR (CLK_CTL_BASE + 0x1090)
-#define GCC_CE2_CFG_RCGR (CLK_CTL_BASE + 0x1094)
-#define GCC_CE2_CBCR (CLK_CTL_BASE + 0x1084)
-#define GCC_CE2_AXI_CBCR (CLK_CTL_BASE + 0x1088)
-#define GCC_CE2_AHB_CBCR (CLK_CTL_BASE + 0x108C)
-
/* GPLL */
+#define GPLL0_MODE CLK_CTL_BASE
#define GPLL0_STATUS (CLK_CTL_BASE + 0x001C)
#define APCS_GPLL_ENA_VOTE (CLK_CTL_BASE + 0x1480)
#define APCS_CLOCK_BRANCH_ENA_VOTE (CLK_CTL_BASE + 0x1484)
@@ -114,12 +107,12 @@
/* UART */
#define BLSP1_AHB_CBCR (CLK_CTL_BASE + 0x5C4)
-#define BLSP1_UART2_APPS_CBCR (CLK_CTL_BASE + 0x704)
-#define BLSP1_UART2_APPS_CMD_RCGR (CLK_CTL_BASE + 0x70C)
-#define BLSP1_UART2_APPS_CFG_RCGR (CLK_CTL_BASE + 0x710)
-#define BLSP1_UART2_APPS_M (CLK_CTL_BASE + 0x714)
-#define BLSP1_UART2_APPS_N (CLK_CTL_BASE + 0x718)
-#define BLSP1_UART2_APPS_D (CLK_CTL_BASE + 0x71C)
+#define BLSP1_UART3_APPS_CBCR (CLK_CTL_BASE + 0x784)
+#define BLSP1_UART3_APPS_CMD_RCGR (CLK_CTL_BASE + 0x78C)
+#define BLSP1_UART3_APPS_CFG_RCGR (CLK_CTL_BASE + 0x790)
+#define BLSP1_UART3_APPS_M (CLK_CTL_BASE + 0x794)
+#define BLSP1_UART3_APPS_N (CLK_CTL_BASE + 0x798)
+#define BLSP1_UART3_APPS_D (CLK_CTL_BASE + 0x79C)
/* USB */
#define USB_HS_SYSTEM_CBCR (CLK_CTL_BASE + 0x484)