platform: msm_shared: update the DSI PHY ON sequence for 28nm SoC
Update the DSI PHY initialization sequence for 28nm SoC based
targets as per the latest recommended settings from the DSI h/w
programming guide.
Change-Id: I31b1407987313137b2bdccfabeba31f08fa23ac6
diff --git a/platform/msm_shared/mipi_dsi_phy.c b/platform/msm_shared/mipi_dsi_phy.c
index 9a26a9d..b169d61 100644
--- a/platform/msm_shared/mipi_dsi_phy.c
+++ b/platform/msm_shared/mipi_dsi_phy.c
@@ -277,7 +277,8 @@
/* Regulator ctrl 4 */
writel(pd->regulator[4], DSI0_PHY_BASE + off + (4 * 4));
/* LDO ctrl */
- if (readl(MIPI_DSI0_BASE) == DSI_HW_REV_103_1) /* 8916/8939 */
+ if ((readl(MIPI_DSI0_BASE) == DSI_HW_REV_103_1) ||
+ (readl(MIPI_DSI0_BASE) == DSI_HW_REV_104_2)) /* 8916/8939/8952/8956 */
writel(0x05, phy_base + 0x01dc);
else if (readl(MIPI_DSI0_BASE) == DSI_HW_REV_103) /* 8994 */
writel(0x1d, phy_base + 0x01dc);
@@ -370,6 +371,8 @@
pd = (mipi->mdss_dsi_phy_db);
+ /* PHY_CTRL_0 */
+ writel(0x5b, phy_base + 0x0170);
/* Strength ctrl 0 */
writel(pd->strength[0], phy_base + 0x0184);
@@ -382,12 +385,6 @@
off += 4;
}
- /* MMSS_DSI_0_PHY_DSIPHY_CTRL_1 */
- writel(0x00, phy_base + 0x0174);
- /* MMSS_DSI_0_PHY_DSIPHY_CTRL_0 */
- writel(0x5f, phy_base + 0x0170);
-
- dmb();
/* 4 lanes + clk lane configuration */
/* lane config n * (0 - 4) & DataPath setup */
for (ln = 0; ln < 5; ln++) {
@@ -400,8 +397,9 @@
}
}
- /* MMSS_DSI_0_PHY_DSIPHY_CTRL_0 */
- writel(0x5f, phy_base + 0x0170);
+ /* MMSS_DSI_0_PHY_DSIPHY_CTRL_4 */
+ writel(0x0a, phy_base + 0x0180);
+ dmb();
/* DSI_PHY_DSIPHY_GLBL_TEST_CTRL */
if (phy_base == DSI0_PHY_BASE ||
@@ -410,6 +408,8 @@
else
writel(0x00, phy_base + 0x01d4);
+ /* MMSS_DSI_0_PHY_DSIPHY_CTRL_0 */
+ writel(0x5f, phy_base + 0x0170);
dmb();
off = 0x01b4; /* phy BIST ctrl 0 - 5 */